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JPS5231630A - Test ethod of digital equipment - Google Patents

Test ethod of digital equipment

Info

Publication number
JPS5231630A
JPS5231630A JP50106960A JP10696075A JPS5231630A JP S5231630 A JPS5231630 A JP S5231630A JP 50106960 A JP50106960 A JP 50106960A JP 10696075 A JP10696075 A JP 10696075A JP S5231630 A JPS5231630 A JP S5231630A
Authority
JP
Japan
Prior art keywords
test
input signal
ethod
digital equipment
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50106960A
Other languages
Japanese (ja)
Inventor
Eiji Wada
Yoichi Asano
Yoshikazu Suzumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50106960A priority Critical patent/JPS5231630A/en
Publication of JPS5231630A publication Critical patent/JPS5231630A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: Improvement of the test efficiency and simplification of the test circuit by delaying the relative input signal into a decision timing signal to test the second input signal of the digital instrument whose output signal timing deffers between the first input signal and the second input signal.
COPYRIGHT: (C)1977,JPO&Japio
JP50106960A 1975-09-05 1975-09-05 Test ethod of digital equipment Pending JPS5231630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50106960A JPS5231630A (en) 1975-09-05 1975-09-05 Test ethod of digital equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50106960A JPS5231630A (en) 1975-09-05 1975-09-05 Test ethod of digital equipment

Publications (1)

Publication Number Publication Date
JPS5231630A true JPS5231630A (en) 1977-03-10

Family

ID=14446888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50106960A Pending JPS5231630A (en) 1975-09-05 1975-09-05 Test ethod of digital equipment

Country Status (1)

Country Link
JP (1) JPS5231630A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55118155A (en) * 1979-03-02 1980-09-10 Chiyou Lsi Gijutsu Kenkyu Kumiai Test method and its device for logic circuit
JPS56116333U (en) * 1980-02-04 1981-09-05
JPS57184058A (en) * 1981-04-22 1982-11-12 Doerries Gmbh Method and device for arranging sheet
JPS647400A (en) * 1987-06-29 1989-01-11 Hitachi Ltd Ic tester
US5077690A (en) * 1989-08-09 1991-12-31 Atmel Corporation Memory input data test arrangement

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55118155A (en) * 1979-03-02 1980-09-10 Chiyou Lsi Gijutsu Kenkyu Kumiai Test method and its device for logic circuit
JPS56116333U (en) * 1980-02-04 1981-09-05
JPS5755241Y2 (en) * 1980-02-04 1982-11-29
JPS57184058A (en) * 1981-04-22 1982-11-12 Doerries Gmbh Method and device for arranging sheet
JPS647400A (en) * 1987-06-29 1989-01-11 Hitachi Ltd Ic tester
US5077690A (en) * 1989-08-09 1991-12-31 Atmel Corporation Memory input data test arrangement

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