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JPS52119053A - Multiiphase mos circuit - Google Patents

Multiiphase mos circuit

Info

Publication number
JPS52119053A
JPS52119053A JP1785477A JP1785477A JPS52119053A JP S52119053 A JPS52119053 A JP S52119053A JP 1785477 A JP1785477 A JP 1785477A JP 1785477 A JP1785477 A JP 1785477A JP S52119053 A JPS52119053 A JP S52119053A
Authority
JP
Japan
Prior art keywords
multiiphase
mos circuit
mos
circuit
multiiphase mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1785477A
Other languages
Japanese (ja)
Other versions
JPS5931894B2 (en
Inventor
Rintoshiyuteeto Giyuntaa
Merinetsuku Danieru
Gurotsuse Yohahimu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Publication of JPS52119053A publication Critical patent/JPS52119053A/en
Publication of JPS5931894B2 publication Critical patent/JPS5931894B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/05—Shaping pulses by increasing duration; by decreasing duration by the use of clock signals or other time reference signals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Pulse Circuits (AREA)
JP52017854A 1976-02-28 1977-02-22 Polyphase MOS circuit Expired JPS5931894B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE000P26082655 1976-02-28
DE19762608265 DE2608265C2 (en) 1976-02-28 1976-02-28 Polyphase MOS circuit for changing the pulse duration

Publications (2)

Publication Number Publication Date
JPS52119053A true JPS52119053A (en) 1977-10-06
JPS5931894B2 JPS5931894B2 (en) 1984-08-04

Family

ID=5971171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52017854A Expired JPS5931894B2 (en) 1976-02-28 1977-02-22 Polyphase MOS circuit

Country Status (4)

Country Link
JP (1) JPS5931894B2 (en)
DE (1) DE2608265C2 (en)
FR (1) FR2342585A1 (en)
IT (1) IT1078248B (en)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2753453C2 (en) * 1977-11-30 1982-01-28 Siemens AG, 1000 Berlin und 8000 München Digital frequency divider
JPS6025929B2 (en) * 1978-01-25 1985-06-21 ソニー株式会社 PWM modulation circuit
US4441037A (en) * 1980-12-22 1984-04-03 Burroughs Corporation Internally gated variable pulsewidth clock generator
DE3126747C2 (en) * 1981-07-01 1983-06-01 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Circuit arrangement for adapting the length of incoming pulses
US4818894A (en) * 1987-03-09 1989-04-04 Hughes Aircraft Company Method and apparatus for obtaining high frequency resolution of a low frequency signal
US5293628A (en) * 1991-11-04 1994-03-08 Motorola, Inc. Data processing system which generates a waveform with improved pulse width resolution
US5530298A (en) * 1993-09-03 1996-06-25 Dresser Industries, Inc. Solid-state pulse generator
US5696994A (en) * 1995-05-26 1997-12-09 National Semiconductor Corporation Serial interface having control circuits for enabling or disabling N-channel or P-channel transistors to allow for operation in two different transfer modes
DE102011080110B4 (en) 2011-07-29 2018-10-31 Siemens Aktiengesellschaft Method for generating a clock signal

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3440546A (en) * 1965-11-15 1969-04-22 Ibm Variable period and pulse width delay line pulse generating system

Also Published As

Publication number Publication date
FR2342585B1 (en) 1982-04-02
IT1078248B (en) 1985-05-08
DE2608265B1 (en) 1977-09-08
DE2608265C2 (en) 1978-04-27
FR2342585A1 (en) 1977-09-23
JPS5931894B2 (en) 1984-08-04

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