JPS51100269A - - Google Patents
Info
- Publication number
- JPS51100269A JPS51100269A JP50024562A JP2456275A JPS51100269A JP S51100269 A JPS51100269 A JP S51100269A JP 50024562 A JP50024562 A JP 50024562A JP 2456275 A JP2456275 A JP 2456275A JP S51100269 A JPS51100269 A JP S51100269A
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50024562A JPS5756796B2 (en) | 1975-02-28 | 1975-02-28 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50024562A JPS5756796B2 (en) | 1975-02-28 | 1975-02-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS51100269A true JPS51100269A (en) | 1976-09-04 |
JPS5756796B2 JPS5756796B2 (en) | 1982-12-01 |
Family
ID=12141587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP50024562A Expired JPS5756796B2 (en) | 1975-02-28 | 1975-02-28 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5756796B2 (en) |
-
1975
- 1975-02-28 JP JP50024562A patent/JPS5756796B2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5756796B2 (en) | 1982-12-01 |