JPS5995473A - Observation device for digital signal - Google Patents

Abstract

PURPOSE:To provide a titled device which does not overlook the change in a digital signal to be observed, permits measurement for a long time, facilitates observation and compresses storage data by detecting exactly the timing for the inversion in switching of said signal as a differentiation signal. CONSTITUTION:A detection circuit 7 for the change point of a digital signal has a differentiation circuit and therefore when the signal change of a digital input signal 19 switches from a logical ''0'' to a logical ''1'' or from the local ''1'' to the logical ''0'', said circuit detects exactly the change point of said signal switching and outputs a detection signal 18 for the change point. A signal 18 is used as a write signal W for a storage circuit 1 or as a clock signal for increasing by one step the content of an address counter 2 in the circuit 1 or further as a reset signal Rs for a 10-bit counter 3 and a 2-bit counter 4. The signal 19 stores successively the data in the time interval of 12 bits while advancing the address in the circuit 1 at every signal change point.

Description

[Detailed description of the invention] The present invention relates to a digital signal observation device.

Conventionally, as a digital signal observation device for this pile, a method is known in which a digital signal is sampled at equal intervals, and a level value of 1" or '0" of the sampled signal to be measured at that time is observed and stored.

FIG. 1 shows the basic method of waveform sampling in a conventional digital signal observation device. As shown in the figure, in order to observe a digital signal, the digital signal to be measured is clocked at constant frequency clocks 11, 12 . ... tn and the digital values d,, d2 . ... A method that attempts to accurately digitally observe digital signals by transmitting and storing the dn to a storage device.As shown above, the conventional digital observation equipment was a basic method of sampling the 6tll waveform to be monitored and processing the waveform. Furthermore, if the digital signal under test changes faster than the sampling frequency, there is a possibility that the signal change may be overlooked. In this case, the sampling theorem is to sample the measured frequency fc, and based on it, to restore the original measured frequency fc.As a guideline, when sampling the original measured frequency fc, the sampling frequency is 1 second. There is a theory that it is possible to recover the original measured frequency from the sampled signal by sampling it 2fc times or more, but this is especially necessary when using an A/B converter to process an analog signal with a digital computer. In the case of a digital signal observation device, the frequency at the time of signal switching is extremely high, so when applying the above sampling method, the sampling frequency can be avoided to be quite high (although it is not necessarily optimal): IL(ゝO In addition, when continuously observing signals in which signal changes occur sporadically at long time intervals, there is a practical problem in the memory of sampled data, so
The drawback is that there are practical restrictions on the opening time.

The present invention has been developed in order to eliminate the above-mentioned conventional drawbacks, and by accurately detecting the switching and inversion timing of the digital signal to be measured as a differential signal,
It is possible to measure over a long period of time without overlooking signal changes, and it is easy to comprehensively view signals that occur sporadically at long intervals (1), making it easy to store stored data. The purpose of the present invention is to provide a digital signal observation device that achieves compaction.

An embodiment of the present invention will be described below with reference to the drawings.

First, when observing a digital signal, as shown in FIG. 2, the switching differential signal of signal inversion, that is, the time intervals Δt□, Δt2, . . . , 31m and the measured digital No. 48 value dm at the end of π.

FIG. 3 is a block diagram showing an embodiment of the digital signal observation device of the present invention, in which 1 is a storage circuit, and 2 is the storage circuit 1.
3 is a 1° bit counter capable of counting from O to 999 which also inputs the data signal 9 to the memory circuit 1, and 4 receives the over 70-signal 13 of the 10-bit counter 3. A 2-bit counter capable of counting up to 0 or 4 which operates to provide output data to the memory circuit 1; Give as a signal. 7 is a digital signal change point detection circuit which provides a change point detection signal 18 to the memory circuit 1, address counter 2, 10-bit counter 3, and 2-bit counter 4, respectively; and 8 is an address of the address counter 2 which is provided to the memory circuit 1. signal, 9
Similarly, 10 is the data signal of the 10-bit counter 3 given to the memory circuit 1, 10 is the measurement clock selection signal to the measurement clock selection switching circuit 5, 11 is each of the 11 measurement clock signals given to the measurement clock selection switching circuit 5, 12 is a measurement clock signal selected by the output signal of the measurement clock selection switching circuit 5; 13 is the 10-bit counter 3;
14 is the basic clock signal (T (no.
Similarly, the X105 signal and 16 are Tx106 signals that are output once every 140106 times of the basic clock signal,
17 is similarly outputted once every 109 times of the basic clock signal 14. is used as a write signal, a clock signal for address counter 2, and a reset signal for 10-bit counter 3 and 2-bit counter 4. 19 is the digital input signal to be observed, 20 is the observation 1:1] End Signal 21 indicates the measured digital signal value at the end of observation.

In this way, when a digital signal that changes with random time intervals Fffi is observed continuously over a long period of time, the present invention can detect changing points of the digital signal as shown in FIG. It is a digital signal observation method that covers the entire digital signal as a wave observation range using the time interval Δt1.Δt2゜...31m between the change points and the final digital signal value dm, and is a realistic method. In order to cope with the constraint of increasing the storage capacity, a method is adopted in which data is compressed and stored at time intervals.

The operation will be described below with reference to the block circuit diagram shown in Figure TA3 of the present invention.

First, the digital input signal 19 to be observed is input to the digital signal change point detection circuit I. Since the digital signal change point detection circuit IS7 has a differentiating circuit, the signal change of the digital input signal 19 is changed from logic "0" to logic '
1" or from logic 1" to logic 0", the change point of the signal switching is accurately detected and the change point detection signal 18 is output. The change point detection signal 18 is the write signal W of the memory circuit 1. Also, the memory circuit 1
The contents of the address counter 2 are used as a clock signal for incrementing by one step, and also as a reset signal Bs for the 10-bit counter 3 and the 2-bit counter 4. Next 1
The 0-bit counter 3 counts the measurement clock signal 12, and when the counted value exceeds 999, an overflow signal 13 is generated and transmitted to the 2-bit counter 4.
Therefore, the 2-bit counter 4 counts the overflow signal 13 of the 10-bit counter 3. The 12-pit data b11 including the 10-bit counter 3 and the 2-bit counter 4 is reset by the change point detection signal 18.) The 10-bit counter 3 and the 2-bit counter 4 are reset by the write signal W just before being Re. The data is written into the memory circuit 1 as data 9. On the other hand, the measurement clock signal 12 is the count value signal b11. of the 2-bit counter 4. blo and its count value signals b□□, b□. The output of the 2-bit counter 4 is (b, , blo) - (0, O) by the measurement clock selection switching circuit 5 which uses the measurement clock selection signal 1o as the measurement clock selection signal 1o.
When [Basic switch signal 14 ('r signal) is changed to 1tC]
Ha(bll, bto) −(0,1),(1,0)
, (1, 1), the TXIO3 signal 15, the TXIQ6 signal 16, and the TX109 signal 17, which are frequency-divided by the basic clock frequency dividing circuit 6, are automatically selected.

At i4, the digital input signal 19 (if) advances the address in the storage circuit 1 at every change point and stores data for a time interval of 12 pits, and finally, due to some condition, the observation ends. When the observation end signal 2o is input to the digital signal change point detection circuit 7, the digital signal 4J@change point detection circuit 1 stops the yi effort, and at the same time, the measured digital signal value 210 at that time is input.
Outputs level ``0'' or 1''.

In order to reproduce the digital signal observed and stored in this manner, the digital signal to be measured 48 and the stored contents of the storage circuit 1 can be read out and processed by another central processing unit (not shown) or the like. It becomes possible to reliably reproduce the observed digital input signal with high reliability.

In the above embodiment, logic '1' or logic '0'
When reproducing observation data, the observation end signal is used as the final signal state as the original signal value, but it is also possible to use another signal state at another time determined by predetermined conditions. do not have.

In addition, the various measurement clock signals 11 and their selection signal clock numbers, and the number of bits b1□, b of the data value of the measured time interval are input to the measurement clock selection switching circuit 5 described above.
Yo. , . . b□, and bo need not be changed, it goes without saying that the same effect can be obtained.

As described above, according to the present invention, by differentiating the change state of a digital signal to be observed that changes randomly over time, the time interval of signal switching changes can be accurately calculated by differentiating the change state of the digital signal to be observed, which changes randomly over time. Since this method is used as a storage method, the precision of the observed digital input signal is greatly improved, and observation data with high precision can be obtained, which is a remarkable effect.

Furthermore, since the data is compressed as an efficient data storage method, the storage capacity can be significantly reduced, and at the same time, it is possible to handle long-term data observation.

[Brief explanation of the drawing]

FIG. 1 is a waveform diagram showing the basic method of conventional digital signal measurement and measurement, FIG. It is a block circuit diagram showing an example. 1... Memory circuit, 2... Address counter, 3...
・10-bit counter, 4...2-bit counter, 5
--Measurement clock selection switching circuit, 6. Basic clock frequency dividing circuit, 7. Digital signal intensification point detection circuit, 8. Address signal, 9. Data signal, 10.
...Measurement clock selection signal, 11...Various measurement clock signals, 12...Measurement clock signal, 13...Overflow signal, 14...Basic clock signal (T signal)
, 18... Change point detection No. 46, 19... Digital input signal, 20... Viewing shelf end signal, 21... Digital signal value to be measured. Agent Makoto Kuzuno - (and one other person) Commissioner of the Japan Patent Office 1. Indication of the case: Japanese Patent Application No. 57-207069 2. Title of the invention: Digital signal observation device 3. To the representative of the person making the amendment: Hitoshi Katayama. 4. , Agent 5, Subject of amendment (1) Detailed explanation of the invention in the specification, drawing 6, content of amendment (11 Mei MA book, page 5, line 3, "from O to 41" (Corrected "10-bit counter 3" on page 5, line 12 of the 21 Mei A to read "10-bit counter 3 and 2-bit counter 4"). 13 + Amend Figure 3 as shown in the attached sheet. 7. One or more documents showing Figure 3 after the revised list of attached documents.

Claims (1)

[Claims] a digital signal change point detection circuit that detects a change point of a digital input signal to be measured and generates an output signal; an address counter of a storage circuit that is incremented by an output signal of the digital signal change point detection circuit; a measurement clock selection switching circuit that receives a plurality of frequency-divided output signals from a basic clock frequency divider circuit that inputs and counts a basic clock signal generated in another circuit and outputs a plurality of frequency-divided signals, and generates a measurement clock signal; a multi-bit counter that counts the output measurement clock signal and takes the resulting counter circuit bit information into the storage circuit as a data signal; While the change point detection signal of the point detection circuit is given as an operation signal, the above! 21+
Digital signal observation characterized in that in order to reproduce one data, an operation is performed using the 8111 constant digital signal value at the end of observation of the digital signal change point detection circuit and the data stored in the storage circuit. Device.