JPS5978390A - Digital tv type display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a digital television type display device that is used in an ultrasonic diagnostic apparatus equipped with a digital television monitor and displays biological signals together with ultrasound images.

Conventionally, electrostatic or electromagnetic deflection type
-Y monitors have been used, but in recent years, devices have been proposed that can display ultrasound tomographic images and biological signals simultaneously using digital television monitors. To explain in more detail, for example, a digital television monitor as shown in FIG.
When drawing B, in order to obtain data in units of 1 pixel corresponding to 1 square divided in the horizontal and vertical directions of the screen, as shown in Figure 3, biological signals are expressed with a period T having a width of 1 pixel. Sample A and B. The data obtained is temporarily stored in a digital memory or the like, read out in time with the scanning of the television, and displayed together with the tomographic image US, etc., as shown in Figure 4, but it is displayed in dots. Put it away. For this reason, a means to connect and display the sampled data as shown in FIG. 5 (○ marks are sample data) can be considered, but in this case, the sampling black.

As shown in Figure 6 (○ marks are sample data), if the biological signal has a high frequency, sufficient data cannot be obtained and accurate waveforms cannot be obtained. There was a problem that it could not be displayed.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art and provide a digital television type display device for use in ultrasonic diagnostic equipment and the like that can depict good biological signals.

The present invention has been made to achieve the above object, and its characteristics include sampling biological signals at intervals as short as one pixel width, determining the maximum value and minimum value in each pixel,
A method of embedding and connecting each maximum value and minimum value, and when calculating the maximum value and minimum value, the maximum value and minimum value in the pixel immediately before the pixel to be calculated are exchanged, and the corresponding The reason is that the maximum value and minimum value in this pixel are determined as the initial value in the pixel.

7 to 14 are diagrams for explaining the present invention in detail. The mark indicates the maximum value, and the 0 mark indicates the minimum value.

As shown in FIG. 7, the principle of the present invention is to sample biological signals at an interval t shorter than the period T of the pixel width, and to calculate the maximum value [Fmax(t):) and the minimum value ( Find Fmin(t)). Then, when displaying on the screen, each pixel is connected by embedding the space between the determined maximum value and minimum value in synchronization with the period T of the pixel width. A display image obtained by this method is shown in FIG.

As can be seen from FIG. 8, in the above method, it is possible to render in the horizontal direction pixel by pixel, and in the vertical direction, it is possible to render an area embedded between the maximum value and the minimum value, so that the conventional problems can be solved to some extent.

However, as shown by ■ in Figure 7, the maximum or minimum value of the pixel is separated from the minimum or maximum value of the next pixel at the boundary between pixels, and as shown by ■ in Figure 8, As shown, there may be discontinuity. In order to solve this problem, as shown in Figure 9, the maximum and minimum values found in each pixel are exchanged, and these values are used as the initial values for calculating the maximum and minimum values in the next pixel. Find the maximum and minimum values in that pixel. That is, find the maximum value and minimum value of the first pixel, replace the maximum value and minimum value in this pixel and use it as the initial value of the next second pixel, and calculate the maximum value and minimum value in this second pixel. Find the value. Similarly, 2
The maximum value and minimum value in the next third pixel are determined by exchanging the maximum value and minimum value in the third pixel. This action is number 4.

The maximum value and minimum value in each pixel are sequentially determined, and as in the case of FIG. 7, the space between the maximum value and minimum value in each pixel is embedded to connect each pixel.

The displayed image obtained by this method is as shown in Fig. 10.
The image looks like a continuous analog signal.

In order to make the principle of this method more understandable, an example will be given.

(1) When the upper right is a waveform of
Let be the minimum value bo, and let the minimum value bnl be the maximum value ao.

If the sampling of the second pixel is continued using this minimum value 1)0+maximum value aO as the initial value, the minimum value will be reached.

is maintained, and the maximum value aO is al, a2, a3・
...an, and finally the maximum value an2 in the second pixel is determined. That is, the maximum value a in the first pixel
nl and the second minimum value. will match, so
There are no gaps between pixels.

In the same way, the maximum and minimum values in each pixel are determined based on the relationship between the second and third pixels, and the third and fourth pixels.

(2) Case of falling to the right Similarly to the case of FIG. 11, as shown in FIG. .

Therefore, the minimum value bn4 in the first pixel is the maximum value a of the initial value. becomes. and the maximum value a. becomes the maximum value an2 in the second pixel and is held, and the minimum value bo becomes bl, b2
．． b3 ·bn, and finally becomes the minimum value bn2 in the second pixel. That is, the minimum value b of the first pixel
Since n1 and the maximum value anz (=ao) of the second pixel match, there is no gap between pixels. In the same way, the maximum and minimum values in each pixel are determined based on the relationship between the second and third pixels, and the third and fourth pixels.

(3) In the case of decreasing midway: In the same way as in the case of (1) and f2) above, as shown in Fig. 13, the minimum value bnl and maximum value anl in the first pixel are The maximum value aQ and the minimum value of the initial values. However, if a point smaller than the minimum value bo is found, the minimum value bl is set.

b2. b3 bn and finally the minimum value bn2
is obtained, and the maximum value an2 is obtained in the same manner as in the case of upward upward movement in (1) above.

(4) When the value rises midway: Similar to the case (3) above, as shown in FIG. 14, the maximum value an1 and minimum value bnl in the first pixel are 2.
The maximum value a (and the minimum value bo
However, when a point larger than the maximum value aQ is found, the maximum value a1+a2+a3...an is obtained, and finally the maximum value an2 is obtained, and the minimum value bn
2 is obtained in the same manner as in the case of downward sloping to the right in (2) above.

Next, embodiments based on the principle of the present invention will be described.

FIGS. 15 to 19 are diagrams showing the configuration of an embodiment of the present invention in a professional manner.

In the figure, 1 is a biological signal receiving circuit such as an electrocardiograph, 2 is an analog-to-digital converter (hereinafter referred to as an A/D converter),
A/I of biological signals at high frequency (sampling interval [L)]
) This is a conversion method that samples the digital signal and converts it into a digital signal. 3 is a first sampling clock generation circuit, which generates the sampling signal A, / of the A/D converter 2;
It is used to create D-conversion black and ri. 4 is a maximum value measuring circuit, and as shown in FIG.
It consists of a gate circuit A, a gate circuit 4B, and a child circuit 4C for maximum value measurement. 5 is a minimum value measuring circuit, and as shown in FIG. 17, a comparator 5A for determining the minimum value.

It is composed of a gate circuit 5B and a latch circuit 5C. 6 is a maximum value storage section, and as shown in FIG.
One for writing, one for child circuit 6A, one for reading.

Child circuit 6B, storage device 60. write signal generation circuit 6D,
It is composed of a write address generation circuit 6B, a read address generation circuit 6F, and a read signal generation circuit 6G. 7
is a minimum value storage section, as shown in FIG. 19, a sub circuit 7A for writing, a sub circuit 7B for reading, a memory device 7Q, a write signal generation port #7D, and a write address generation circuit 7B.

Read address generation circuit 7F, read signal generation circuit 7G
It consists of 8 is a second sampling clock generation circuit that creates timing for writing into the storage units 6 and 7; 9;
is a television synchronization signal generation circuit. 10 is a embedding circuit for embedding between the maximum value and the minimum value, and is a Y-axis address generator 10A.

Comparators 10B and 100. It consists of an AND gate circuit 1°D. 11 is a display device.

Next, the operation of this embodiment will be explained with reference to FIGS. 15 to 19.

The biological signal received by the biological signal receiving circuit 1 is input to the A/D converter 2. The A/D converter 2 samples the biological signal and converts it into a digital signal using the A/D conversion signal from the first sampling signal generation circuit 6 at a sample interval t. This sample digital signal is the maximum value
The maximum value judgment comparator 4A of the sub-circuit 4 and the maximum value side measurement,
The output of the maximum value measurement latch circuit 4C is compared with the sample digital signal, and when the output of the maximum value measurement latch circuit 4C is smaller, the output of the maximum value judgment comparator 4A is input to the child circuit 4c. When the gate circuit 4B is fully opened and the sampling clock is turned on, the newly sampled digital signal is stored as the maximum value in the maximum value measurement latch circuit 4C.

The sample digital signal is similarly input to the minimum value measuring circuit 5, and when the output of the sub circuit 5c is larger than the sample digital signal input to the minimum value judgment comparator 5A, sampling is performed. The newly sampled digital signal is raised to the minimum value by the clock and then stored in the child circuit 5c for minimum value measurement. The maximum value and minimum value of the sample digital signal obtained in this way are determined by the write latch circuit 6A of the maximum value storage unit 6 and minimum value storage unit 7 using the pixel width sampling clock signal T and the television monitor synchronization signal.
and 7A, and are stored in storage devices 6C and 7C via write signal generation circuits 6D and 7D. Storage devices 6C and 7
I7nimple digital data stored in C,
TV synchronization signal generation circuit9. Read address generation circuit 6
F and 7F, read signal generation circuits 6G and 7G read from storage devices 6C and 7C, and read out child circuit 6
It is input to the comparator +oB and 10C of the embedded circuit 1o, which fills the gap between the maximum value and the minimum value, through B and 7B.

Here, as shown in FIG. 20, comparators 10B and 10
Q is output from the comparator 1013 when the Y-axis address (in the vertical direction of the TV) is compared with the maximum value, and when the Y-axis address is smaller than the maximum value, and similarly when the Y-axis address is larger than the minimum value. , is outputted from the comparator 10C, ANDed in the AND gate circuit 10D, and the output is outputted to the display device 11.
, and fill in the space between the maximum and minimum values.

Next, FIG. 21 shows a circuit configuration for exchanging the maximum value and minimum value. In FIG. 21, the same parts as in FIG. 15 are given the same reference numerals, and their explanation will be omitted.

In FIG. 21, 12 and 16 are selection circuits, selection circuit 1
2 is the second sampling clock, as shown in FIG.
When the switching signal S from the error generation circuit 8' is low level (L), the minimum value is output to the maximum value measuring circuit 4', and when it is high level (I), the output of the A/D converter 2 is output. Output to maximum value measurement circuit. Further, when the switching signal S is at a low level (L), the selection circuit 13 outputs the maximum value to the minimum value measuring circuit 5', and when it is at a high level (H), the selection circuit 13 outputs the output of the A/D converter 2 to the minimum value. It is designed to be output to the measurement section.

The maximum value measuring circuit 4' includes a gate circuit 4D that gates the output of the second sampling cross-currency generation circuit 8' in the maximum value measuring circuit 4 shown in FIG. 15, and ORs the outputs of the gate circuits 4B and 4D. A gate circuit 4E is provided for gate. Similarly, the minimum value measuring circuit 5' is connected to the gate circuit 5D and the gate circuit 5D shown in FIG.
It is provided with an R gate circuit 5E and has the same circuit configuration as the maximum value measuring circuit 4', so it is omitted in FIG. 21.

The second sampling black and RI generation circuit 8' outputs the sampling black and RI T in the same manner as the second sampling black and RI generating circuit 8 shown in FIG. Switching signal S as shown in Fig. 22
is starting to occur.

Next, the operation of this circuit will be explained with reference to FIGS. 21 and 22.

1st '5, with the maximum and minimum values open as shown in the figure,
The sampling clock transfers the maximum value from the maximum value measurement latch circuit 4C of the maximum value measurement circuit 4' to the child circuit 6A for writing in the maximum value storage section 6, and at the same time transfers the maximum value to the minimum value measurement circuit 4C through the selection circuit 13. Measure the minimum value side of 5',
Transfer the maximum value to child circuit 5C. In the case of the minimum value, in the same way, the minimum value measurement circuit 5C is used for minimum value measurement.
At the same time, the minimum value is transferred to the child circuit 7A for writing in the minimum value storage section 7, and at the same time, the minimum value is transferred through the selection circuit 12 to the child circuit 4C for maximum value measurement in the maximum value measuring circuit 4'.

In this way, the maximum value storage section 6 and the minimum value storage section 7 are
At the same time as storing the maximum value and minimum value, the maximum value measuring circuit 4' uses the minimum value as an initial value for measuring the maximum value in the next pixel, and the minimum value measuring circuit 5' stores the maximum value in the next pixel. The measurement is repeated as an initial value for minimum value measurement.

Next, when considering the maximum value measuring section 4', the data exchanged and inputted to the maximum value measuring circuit 4' and the minimum value measuring circuit 5' is the sampling clock T output from the sampling clock generation circuit 8'. Gate circuit 4D from switching signal S
is opened and stored in the child circuit 4C for maximum value measurement. Using this maximum value side, the replaced data stored in the child circuit 4C is compared with the new sample data,
When the new sample data is larger than the replaced data, it is output from the maximum value measurement comparator 4A, and when this output is present and it is not switching, the gate circuit 4B opens and a new sample is generated by the sampling clock. The data is stored in the child circuit 4C for maximum value measurement.

Here, when there is an output from the maximum value measurement comparator 4A, it is a case of an upward-sloping waveform as shown in Fig. 11, and when there is no output, it is a case of a downward-sloping waveform as shown in Fig. 12. This is the case for waveforms. It can be seen that when there is an output from the maximum value measurement comparator 4A, a new maximum value is obtained, but when there is no output, the previous minimum value is held and becomes the maximum value in this pixel.

It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without changing the gist thereof.

As explained above, according to the present invention, each pixel is connected by finding the maximum and minimum values in a pixel and embedding between them, so that biological signals can be displayed as lines instead of dots. be able to.

Also, when calculating the maximum and minimum values in the pixel, the maximum and minimum values are exchanged and the maximum and minimum values in this pixel are calculated as the initial values of the next pixel, so Continuity can be provided by concatenation, and even biological signals with frequency components in the high range can be displayed accurately like analog signals. As a result, images suitable for diagnosis can be provided.

[Brief explanation of the drawing]

Figures 1 to 6 are diagrams for explaining the problems of conventional digital television type display devices that display biological signals as well as ultrasound images, and Figures 7 to 14 are diagrams showing details of the present invention. 15 to 22 are diagrams for explaining one embodiment of the present invention. 1 biological signal receiving circuit, 2. , , A/'D converter, 6 first sampling clock generation circuit, 4, 4' maximum value measuring circuit, 5, 5' minimum value measuring circuit, 6 maximum value storage section,
7 Minimum value storage unit, 8 Second sampling clock generation circuit, 9 Television synchronization signal generation circuit, 10 Maximum value and minimum value embedding circuit, 11 Display device. Agent Patent Attorney Aki 1) Collection Ki 41st Sword Figure 5 Figure 6 = 1 element 746- Figure 8 Figure 10 Figure 11 Figure 13 Figure 12 Flash Figure 14

Claims (2)

[Claims] (1) In a digital television type display device, an analog-to-digital converter samples the displayed signal at a cycle shorter than the pixel width and converts it into a digital signal, and the maximum value in each pixel is calculated from the output of the analog-to-digital converter. A maximum value/minimum value measuring circuit for determining the minimum value, a storage device for storing the output of the maximum value/minimum value measuring circuit, a circuit for loading and reading data into the storage device, and the maximum value and minimum value. What is claimed is: 1. A digital television type display device comprising: an embedded circuit that is embedded between the embedded circuit and a digital television type display device that displays the output of the embedded circuit. (2) In a digital television type display device, an analog-to-digital converter samples the displayed signal at a cycle shorter than the pixel width and converts it into a digital signal, and the maximum value in each pixel is calculated from the output of the analog-to-digital converter. A maximum value/minimum value measuring circuit that replaces the maximum value and minimum value in the pixel immediately before the pixel to be determined and obtains the maximum value and minimum value as the initial value of the pixel when determining the minimum value; A storage device that stores the output of the maximum value/maximum J/value a1 measurement circuit, a circuit that writes and reads data in the storage device, an embedding circuit that embeds between the maximum value and the minimum value, and the embedding circuit. 1. A digital television type display device comprising a digital television type display device for displaying the output of.