JPS5968949A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain flat surface by allowing a single crystal to grow on an Si substrate having a pattern of insulator and selectively etching polycrystal by making use of difference in impurity diffusion speed betwen single crystal and polycrystal. CONSTITUTION:A silicon is epitaxially formed opening to SiO2 2 on the Si substrate 1 and a poly-Si 3 is formed on the film 2 and a single crystal Si 1' is formed within the window. When phosphorus is diffused, it is diffused deep in the film 3 but shallow in the film 1'. The heat treatment is carried out in order to perfectly diffuse phosphorus into the film 3. Thereby, the film 4 is formed. Thereafter the layer 4 is selectively etched with a mixed solution of fluoric acid, nitric acid and acetic acid and etching is stopped when the layer 4 is almost perfectly removed. Thereby, the single crystal Si 1' is not almost etched, the substrate surface is flattened, a micro-miniature buried pattern can be obtained, disconnection can be prevented. Moreover, since there is no difference in size conversion as the reverse pattern of insulating film, a high integration density LSI can be obtained with good yield.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a semiconductor device, and in particular to a method of embedding a conductor in an insulating film, and a method of manufacturing a semiconductor device to achieve high density and high integration.
With the increasing density and integration of semicircular integrated circuits, it has become desirable to have a flat substrate surface for the purpose of miniaturizing one element. Therefore, conventionally, as shown in FIG.
Silicon oxide film 2 (approximately 5000A) and PSG film (Ph
A layer of ospho 5 illicate glass) 2' (approximately 30 ooA) is deposited, and a resist mask (not shown) is used to perform dry etching such as reactive spanometric etching or wet etching. An opening is formed, and then the polycrystalline silicon film 3 is coated by CVD (Chemistry) to a thickness approximately equal to that of the step of the opening (approximately 500A).
It is formed by vapor deposition (vapor phase growth method).

Next, heat treatment is performed in an iR*i electric furnace at about 10,000 C to diffuse phosphorus from the PSG film 2' into the polycrystalline silicon film 3. Next, when the polycrystalline silicon film 3 is etched using a mixed solution of hydrofluoric acid, nitric acid, and acetic acid, the polycrystalline silicon portion where phosphorus is diffused is etched several tens of times faster than the polycrystalline silicon portion (within the opening) where phosphorus is not diffused. Due to the etching speed, as shown in b, the polycrystalline silicon film on the PSG film 2' is completely etched, and most of the polycrystalline silicon film in the opening where impurities have not been diffused remains, leaving the entire substrate surface flat. becomes.

However, in this method, phosphorus easily diffuses into the polycrystalline silicon film in contact with the side surfaces of the opening of the PSG film, and the smaller the opening size and the larger the opening step and the psG film thickness, the more the polycrystalline silicon film inside the opening becomes Phosphorus is diffused deeply from the lateral direction. This means that many parts are removed by etching, the sides of the polycrystalline silicon film inside the opening are not concave, and the substrate surface is uneven, making it difficult to form fine patterns, and when metal wiring etc. are formed next, disconnections occur. It becomes easier to do. This is high density,
This shows that manufacturing highly integrated ICs is not easy.

OBJECTS OF THE INVENTION The present invention takes the above-mentioned problems into consideration and provides a simple method for forming a reverse pattern of an insulating material using a conductive material in a self-aligned manner and for making the substrate surface flat.

Structure of the Invention The method of the present invention is based on a pattern of an insulator (by growing a semiconductor crystal on a plate and utilizing the difference in impurity diffusion rate between a polycrystalline semiconductor layer on the insulator and a single crystal semiconductor layer on the substrate). , the polycrystalline semiconductor layer is selectively etched to make the substrate surface flat.

Description of examples An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 2(a), first, a silicon oxide film 2 is formed on a single-crystal semiconductor silicon substrate 1 by a thermal oxidation method or a vapor phase epitaxy (CVD method), and then a resist pattern is masked using a photolithography technique (see FIG. (not shown), the silicon oxide film 2 is etched to expose a part of the silicon substrate 1.

In this case, dry etching is preferred over wet etching to form a steep opening.

(b) Crystals of silicon are grown on the surface of the substrate by, for example, an epitaxial method. By this process, an H-poly A silicon film 3 is formed on the pattern of the silicon oxide film 2, and a single crystal silicon film 1' is formed on the silicon substrate within the opening.

Next, in (C), an n-type impurity such as 1 phosphorus is implanted from the surface of the substrate by thermal diffusion or by diffusion or ion implantation through a silicon glass film containing phosphorus, and a high 1t'll.
When phosphorus is diffused into the silicon epitaxial layer by the L heat treatment, it is deep in the polycrystalline silicon film 3 and the crystalline silicon film 1
′ is shallowly diffused. This is due to the description of the diffusion coefficient, which means that polycrystalline silicon IrJ, 1 o-10
c4/sec, single crystal silicon is 1O-12c+fi
/SeC and polycrystalline silicon are about two orders of magnitude larger. Here, it is preferable to carry out the heat treatment under conditions in which the polycrystalline silicon film 3 is completely diffused with phosphorus, and to prevent phosphorus from being diffused into the single crystal silicon film 1' as much as possible. However, this is easy because the diffusion coefficients differ by two orders of magnitude as described above. Through the above processing, a phosphorus diffusion layer 4 is formed.

Next, in (d), the phosphorus diffusion layer 4 of the silicon epitaxial layer is etched. In this case, when a mixed solution of hydrofluoric acid, nitric acid, and acetic acid is used as the etching method, the etching rate of the phosphorus diffused layer is several tens of orders of magnitude higher than that of the undiffused layer. Since etching is several times faster than etching, if etching is stopped when the polycrystalline silicon film 3 is completely etched, the monocrystalline silicon film 1' will hardly be etched and the substrate surface will become flat as shown in the figure. can be controlled. In addition, even if the silicon epitaxial layer is etched by plasma etching using a dry etching method using cF4 gas, the polycrystalline silicon film 3 can be etched quickly and the substrate surface can be made flat in the same manner as described above. Although phosphorus is diffused into the silicon epitaxial layer as an impurity,
As or sb may also be used.

Note that if % is used as the above impurity, the difference in etch rate between diffusion and non-diffusion is better, but there is also a difference in etch rate even for P type, and the effect is ffJ. By controlling the step difference in the film opening, the film thickness of the silicon epitaxial layer, and the diffusion conditions, the substrate surface can be made flat with high precision.

In Example 2, crystal growth of silicon was carried out by epitaxial method, but as another method, molecular beam epitaxy (MBE: m
A crystal growth method called olecular beam epitaxy may also be used. In the above explanation, we have only shown a simple method of embedding a conductive film to flatten the surface of the substrate, but after flattening, impurities are diffused into the conductor and the base substrate Furthermore, it is also possible to make ohmic contact between the two layers and a wiring layer or an electrode part of a metal or semiconductor film. It is possible to create a device by forming an active region in a conductor (silicon single crystal in this case), taking into account the thickness and dimensions of the insulating film.

Effects of the Invention As described above, by using the method of the present invention, the surface of the substrate can be flattened, and the buried conductor portion can be used as an electrode or an active region, so that the field of application can be further expanded. In addition, fine patterns are possible, there is no need to worry about disconnections in the final metal wiring layer, etc., and there is no difference in dimensional conversion as the insulating film is reversely patterned, allowing high-density, high-integration LSIs to be manufactured with good yield, which is industrially beneficial. It is.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are cross-sectional views of the manufacturing process of the main parts of a conventional semiconductor device, and FIGS. 2(&) to (d) are cross-sectional views of the manufacturing process of the semiconductor device of the present invention. It is a diagram. 1...Silicon substrate, 1'...Single crystal silicon layer, 2...Silicon oxide film, 2'...
...PSG film, 3...polycrystalline silicon layer,
4... Phosphorus diffusion layer. Name of agent: Patent attorney Toshio Nakao and 1 other person22
9

Claims (1)

[Claims] ") 1. Semiconductor crystal growth is performed on the surface of a semiconductor crystal substrate having an insulating film pattern with a part of the crystal substrate exposed, and impurities are implanted from the surface of the single crystal semiconductor layer and insulating film on the middle crystal substrate; = ratio Mini-7'' is characterized by comprising the steps of forming impurities deeply in the polycrystalline half-core layer and shallowly in the single-crystalline semiconductor layer, and etching the polycrystalline lower core layer in which the impurities are diffused. A method for manufacturing one line of semiconductor devices.