JPS5960683A - Array processor device - Google Patents

Abstract

PURPOSE:To set the number of stages and parallelism of a pipeline by connecting input buses of plural processor groups by switches in common or connecting the input/output buses of adjacent processor groups adequately. CONSTITUTION:Movable contacts S21-Sn1 constituting switches S2-Sn are provided to input buses I2-In of processor groups 212-21n constituting titled array processor device. Switches S2-Sn1 are provided. One-side fixed contacts S22-Sn2 of those switches S2-Sn2 are connected to other-end parts of output buses O1-On-1 of the processor groups 211-21n-1. The other-side contacts S23- Sn3 of the switches S2-Sn are connected to the input bus I1 of the processor group 211. This input bus I1 is connected to a mass-storage memory 23 through an input/output control part 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an array processor device that performs matrix and vector operations on large-capacity data such as image data.

[Technical drawbacks of the invention and its problems]

As is well known, array processor devices are applied to processes that perform repetitive calculations such as matrix and vector operations at high speed, such as image processing.

In addition, in its general usage form, as shown in FIG. Peripheral equipment 1
3 is controlled by a general-purpose computer 11, and necessary data is input and output thereto.

Since the configuration of this type of array processor device performs high-speed processing, the signal processors (single processors that make up the array) often have a linear structure or a parallel structure.

However, even with such a structure, if it is used only for limited processing, it is difficult to make full use of all the functions of the array processor device. In other words, if only a part of the inline structure or a part of the processors in a parallel structure can perform sufficient processing, there is a margin for processing, but there is a lot of waste. However, if you develop all the dedicated hardware for a certain amount of fixed processing, you will be able to obtain a device with sufficient performance, but it will be difficult to use it for other processing. This has the disadvantage that the device is not versatile.

[Purpose of the invention]

This invention was made based on the above-mentioned circumstances, and its purpose is to make it possible to set the number of eve line stages and parallelism to any desired value by changing the switch, and to achieve an excellent p1 configuration with the minimum necessary configuration. The present invention aims to provide an array processor device that can achieve high speed and versatility.

[Summary of the invention]

This invention connects multiple signal processors to input/output buses to configure a complete processor group, connects the output paths of the multiple processor groups to all storage units, and shares the input buses of the multiple processor groups with a switch. The input/output buses of adjacent processor groups are connected in parallel, and the number of pipeline stages and degree of parallelism can be arbitrarily set.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to all the drawings.

Figure 2 shows an array processor device, which, like in Figure 1, is a general-purpose computer (such as a minicomputer or microcomputer).
is comprehensively controlled by. Here, 211, 2
Each of 12-1-2 I n is a processor group.

This grosse.

The groups 211 + 222 to 21n are the input bus 01 + I2 NI n and the output bus 01, respectively.
+ A plurality of signal processors PIl, P2! connected between 02~On! ~Pml, PI3,222~
2m11. .

P 1 n+ P 2 n ” pmn. Each processor group 211 to 21n with such a configuration
One end of the output paths O, . This large-capacity memory 23 is constituted by, for example, a semiconductor memory or a magnetic disk device. In the case of a semiconductor memory, it is built into an array processor device, and in the case of a magnetic disk device, it is built into a data bus similar to the peripheral devices M and 13 shown in FIG. connected to. Further, the input paths 2 to 2In of the processor groups 212 to 2In each include switches Sz+S.
s ~ S n Movable contact piece S 211831 ~ S
n1 is provided. One fixed contact S2z+Ssz-Sn2 of the switches 52tS3-Sn is connected to the processor group 211. 272-2 Jn-, (not shown) connected to the other end of output bus 01+02-On-■, switch 8! +83~Sn other fixed connection S23. S33～
Sn3 are each connected to the input bus II of the processor 61'21+. This input path Tl is connected to a large capacity memory 23 via the input/output control section 22.

It should be noted that the signal processors P, . FIG. 3 shows an example of a signal processor, and 3 is an input/output interface connected to an input/output path. Further, 32 is a program memory, and the data memory 33 and coefficient memory 34 are accessed by the program stored in this memory 32, and the processing memory 35. A predetermined calculation is performed via an adder 36 and an integrator 37. The output of the calculation results and the input/output of data to/from other signal processors or the large capacity memory 23 are performed via the input/output interface 31.

In the above configuration, the movable contact pieces 821 to Sn1 of the switches S and Is2 to Sn are all fixed contacts S as shown in FIG.
When connected to Z'l-8T12, a maximum of n stages of line processing can be performed. In addition, the movable contact piece 521-8y
When all 1tk are connected to fixed contacts 823 to Sn3,
Parallel processing can be performed by all signal processors from Pll to Pmn. Such switches 82~S
n is set by switching manually or by software. For example, when performing fixed processing, the switch is fixed at a predetermined state, and when performing processing that changes in time series, the switch is switched to the zologram pull by the general-purpose computer to enable high-speed calculation.

According to the above configuration, by switching the switches 82 to sn, it is possible to set the number of eve line stages or the degree of parallelism of the signal processors to any desired value. Therefore, the array processor vi1-X can have a necessary and sufficient configuration depending on the processing purpose and amount of data, so that superior high-speed performance and versatility can be achieved compared to the prior art.

In addition, since one Alleygro Tsusa Equipment W can be used for various processing purposes, there is no need to develop dedicated equipment for each processing purpose, which is highly economical.

Further, since the signal processors are arranged in a matrix, the structure can be easily changed by simply switching the switches 82 to Sn'jk, and this control is also easy.

Further, when processing is performed in a certain structure, a signal processor for hacking up the system can be connected as necessary by operating the switches 82 to sn, so a highly reliable design is possible.

〔Effect of the invention〕

As detailed above, according to the present invention, the number of stages and parallelism of the pie line can be set to any desired value by changing all the switches, and excellent high speed and versatility can be achieved with the minimum necessary configuration. It is possible to provide an array processor device capable of

[Brief explanation of drawings]

FIG. 1 is a block diagram showing how an array processor device is used, FIG. 2 is a block diagram showing an embodiment of the array processor device according to the present invention, and FIG. 3 is a block diagram showing an example of a signal processor. 2 Jl, 272 to 21n... processor group,
P 11-Pmn...Signal Procera? , 1. ~I
n...Input bus xO1-On...Output bus, sZ~
sn...Switch, 23...Large capacity memory. Applicant's agent Patent attorney Takehiko Suzue Figure 1 11 n3 Figure 3 3

Claims (1)

[Claims] A processor group in which a plurality of signal processors are connected in parallel between output buses, a storage section to which a plurality of these processor groups are connected via an output bus, and a common input/mass for these plural processor groups. Alternatively, an array processor device comprising a switch for connecting all the input/output buses of adjacent processor groups to connect the processor groups in series or parallel to the storage section.