JPS5957690A - Automatic sewing machine - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sewing machine, and more particularly to a program-controlled automatic sewing machine.

2. Description of the Related Art Sewing machines are known that include a workpiece holder that moves a workpiece in a predetermined pattern relative to the sewing needle of the sewing machine. Such a sewing machine is particularly advantageous when sewing the same pattern repeatedly. The earliest sewing machines of this type were relatively complex cam-controlled machines, and each time a person wanted to change from one sewing pattern to many, the entire cam device had to be replaced, making for time-consuming adjustments. It must be made. Cam-controlled sewing machines for buttonhole stitching and bartacking have no ability to change to other sewing patterns.

More recently, sewing machines have become popular in which a workpiece holder is moved by a sequence of information stored on mechanically controlled elements such as perforated paper tape, cards or magnetic tape. In such sewing machines, the sequence of information in the recording medium controls the movement of the workpiece holder while the needle is withdrawn from the workpiece in each cycle.

However, automatic sewing machines that use paper, magnetic tape or cards to control the movement of the workpiece have several drawbacks. First, in these tape sewing machines and card sewing machines, it takes a considerable amount of time to move the stored information to one location. Therefore, in order to operate the sewing machine at high speed, complete commands must be stored and stored in a single storage location.

Furthermore, the complexity of sewing machine operation is limited by the amount of information that can be stored in each storage location. The second, which is mechanical in nature
The limitation is that the sewing machine number is limited by the speed at which the storage medium can be mechanically moved from one storage location to the next. Third, paper, magnetic tape or card readers are expensive compared to cam controlled sewing machines. Also, although higher speeds can be achieved by using buffer units, they significantly increase the cost of the sewing machine.

A principal feature of the present invention is to provide an automatic sewing machine with randomly addressable memory means that increases the speed and sewing capabilities of the machine.

The sewing machine of the present invention includes a sewing needle, a means for reciprocating the sewing needle,
It is equipped with a workpiece holder that moves the workpiece during sewing. The sewing machine includes memory means having randomly addressable storage locations in which position information and command information can be stored, and address means for sequentially selecting these storage locations.

The sewing machine also includes means for sequentially reading information from the selected storage location, means for generating a signal representative of the read information, and means for controlling the needle reciprocating means and moving the workpiece holder in accordance with the symbol. has.

A feature of the invention is that the storage location has a plurality of information bits forming a plurality of separate data machines.

Another feature of the invention is that it provides a means to separately select any data sewing machine in a selected storage location.

A further feature of the invention is that the reading means sequentially reads information from selected storage locations of the selected data bank.

Yet another feature of the invention is the provision of means for initializing the addressing means so that the addressing begins at a predetermined storage location.

Yet another feature of the invention is the provision of means for automatically changing the bank selection means to select a different bank at a given storage location of a selected bank.

A feature of the invention is the provision of switch means for sequentially switching the bank selection means to select different banks.

Another feature of the invention is the provision of means for displaying selected databanks.

A further feature of the invention is the provision of a means for generating a clock signal asynchronous to the operation of the sewing machine to sequence the addressing means.

Yet another feature of the invention is that the sewing machine selection means selectively enables or disables certain output signals from the memory means to form data signals.

Another feature of the invention is the provision of means for timed and discrete pulses to the sewing machine for selectively starting the drive means at different times for operation of the sewing machine.

Yet another feature of the invention is the provision of means for decoding a number of selected pieces of data information from the memory means during one cycle of the sewing machine.

A feature of the invention is the provision of first and second clamping means and means for selectively engaging the clamping means with a workpiece.

Yet another feature of the invention is the provision of temperature measuring means connected to the -portion of the drive means and means for deenergizing the drive means to prevent damage caused by overtemperature conditions.

Still other features of the invention include means for determining whether the clamping means is disengaged from engagement with the workpiece and shutting off the drive means to prevent sewing while the clamping means is in the disengaged position. The purpose is to provide the means.

Yet another feature of the invention is the provision of means for moving the workpiece holder to a predetermined position spaced from a reference (home) position.

Another feature of the invention is the provision of means for generating a pulse train for the drive means and means for modifying the pulse train by data information selected at the storage location.

A feature of the invention is the provision of means for generating a reference pulse train and means for modifying the reference pulse train for energizing the drive means.

Still other features of the invention include means for activating the drive means to move the workpiece holder into position relative to the needle;
It is an object of the present invention to provide means for stopping this driving means when a predetermined period of time has elapsed after starting the driving means.

Another feature of the invention is that the reciprocating means provides a means for driving the working holder while the needle is stationary.

Yet another feature of the invention is the provision of a means for cutting the thread on the sewing machine while the needle is stopped reciprocating and prior to driving the work holder.

Yet another feature of the invention is that while the needle is reciprocating or stopping,
The object of the present invention is to provide a means for forming a pulse for starting the drive means.

Yet another feature of the invention is the provision of means for automatically releasing the clamping means of the sewing machine when the needle stops moving back and forth at the end of a sequence of sewing operations.

A feature of the present invention is the provision of sensor means for detecting thread breaks in a sewing machine and means responsive to the sensor means for forming a signal indicative of thread breakage.

Yet another feature of the invention is that the signal forming means is enabled when the sewing machine is in a predetermined operating mode in order to prevent false signals by the signal forming means.

Further features will become more fully apparent in the following description of embodiments of the invention.

1-3, a program controlled sewing machine 50 according to the present invention is shown having a projecting arm 52 for transmitting mechanical power to a sewing needle 54. Referring to FIGS. The workpiece to be sewn (not shown) is held by a workpiece holder 56 which is moved in a horizontal plane by means of a novel power transmission system. The power train is driven by a pair of step motors 58, 60 positioned on opposite sides of arm 52.

These motors provide driving forces for moving the workpiece holder in two coordinate axes, referred to as coordinate axes or base directions X, Y. This power transmission system functions to convert the rotational drive force of the step motor into motion of the workpiece holder in two coordinate directions, the Y-axis direction being approximately aligned with the longitudinal axis of the arm 52, and the X-axis direction being approximately aligned with the longitudinal axis of the arm 52. The direction that crosses the vertical axis of

The step motor is driven by an electrical signal from a new electrical circuit in the control system. These signals are synchronized by electromechanical synchronization unit 62 to the movement of needle 54 into and out of the workpiece. The unit 62 is connected to the handwheel 64 of the sewing machine and is driven by the handwheel to provide a synchronizing signal to the electrical circuit.

In this particular embodiment, the workpiece holder is moved in a predetermined pattern relative to the movement and position of the sewing machine needle. The sequence of commands directing the desired pattern of movement and sewing of the workpiece holder 56 is stored in a storage element or memory unit having a plurality of randomly addressable storage locations. These commands include command information that controls the movement of the holder and the reciprocation of the needle, and position information that guides the movement of the workpiece holder relative to the needle over various distances in two coordinate axes. .

Preferably, the storage element is a programmable read-only memory (ROM). In this device,
Commands stored at various locations are changed to create the desired new movement pattern. This storage element may be, for example, a randomly addressable read-only memory that cannot be changed to indicate a new movement pattern.

Both types of solid state memory elements are readily available and preferred. As known to those skilled in the art, this memory or storage element is non-volatile, ie, retains data during power outages, and non-destructive, ie, the data is not destroyed by read operations.

An electrical control circuit is provided for reading information from as many addressable locations of the storage element as necessary to obtain complete command for each movement of the workpiece holder. This circuit converts each command into a sequence of pulses to be applied to the step data and thus drives the motor when the needle 54 does not engage the workpiece as commanded by the synchronization unit 62. In this way, the movement of the workpiece holder is timed so as not to adversely affect the movement of the sewing machine needle 54.

As best shown in FIG.
The power transmission system used to transmit power from 0 to the workpiece holder 56 consists of two cable systems or other suitable means such as gears, one corresponding to each coordinate direction. The configuration of the cable system is as follows. The pulleys 66, 68 are connected to the shafts 70, 72 of the step motors 58, 60.
are installed in each. Cables 74, 76 are secured around pulleys 66, 68 as described below. In this way, the step motor shaft 70,
The rotational motion of cables 74 and 76 is converted into the linear motion of cables 74 and 76.

Since both pulleys 66, 68 and their associated structures are substantially the same, one pulley 66 will be described as a representative in connection with FIGS. 4 and 5.

As shown, the pulley 66 has a pair of screws 77a.
, 778 to the corresponding morph axis 70.

The corresponding cable is wound several times, for example 21/4 to 21/2 times, in a helical groove 82 formed on the outer surface of the pulley;
The central part of the cable thus wound is accommodated in a circumferential recess 84 in which the cable is fixed to this pulley by means of a screw 78. Thus, at least a portion of one turn of the cable is formed above the notch 84, and the other portion is formed below the notch.

In this way, a suitable cable is firmly fixed to each pulley.

Referring to FIGS. 1-3, 6, and 7, a pivot pin 108 fixed to a base plate 86 of the sewing machine
A cable 76 about which the workpiece holder pivots is secured at both ends to a substrate 86 by a pair of hooks and shoulder screws 88 and 89. As best shown in FIG. 3, portions of cable 76 are threaded through the upper and lower grooves of freely rotating pulley 90 in opposite rotational directions.

As shown in FIGS. 3, 6 and 7, the pulley 90
is an end 94 of a connecting member 96 extending from a pivot arm 92 which is pivoted to the base plate 86 by a pivot pin 108.
It is rotatably mounted nearby. Referring again to FIG. 3, one turn of cable 76 passes from pulley 90 to motor pulley 68, and the other turn of cable passes from pulley 90 to a freely rotating pulley 98 which is pivoted to base plate 86. As shown, the cable 76 passes around a pulley 98, from which the cable 76 passes through the motor pulley 68, and around the pulleys 90, 98, 68 between its ends.

Since the cable end is fixed, the step motor 60
rotates the motor pulley 68, the pulleys 90, 68
The cable course between the pulleys 90, 9 simultaneously shrinks or expands based on the direction of rotation of the motor shaft 72.
The cable course between 8 expands or contracts inversely. Thus, when motor pulley 68 is driven clockwise by motor 60 as viewed in FIG. 3, pulley 90 is moved generally toward and away from motor pulley 68. Conversely, pulley 90 is moved approximately toward pulley 93 and away from pulley 68 in response to the counterclockwise rotation of pulley 68.

Referring to FIGS. 3, 6 and 7, pulley 90 is brought close to member 96 so that movement of pulley 90 is translated into pivot movement of pivot arm 92 about pin 108. Referring to FIGS. As will be seen below, pivot arm 92 displaces extension arm 110, which is attached at its negative end to workpiece holder 56, during its pivot movement. Therefore, as arm 92 rotates about pivot pin 108, arm 110 and workpiece holder 56 also rotate. Accordingly, as motor pulley 68 rotates clockwise as seen in FIG. 3, workpiece holder 56 moves toward edge 100 of substrate 86, which is a movement in the - In response to the counterclockwise rotation of the plate 86, the workpiece holder moves toward the opposite edge 102 of the plate 86, which is in the +X axis direction.

Referring to FIGS. 1-3, 9 and 10, one corner of the step motor 60 is connected to the plate 86.
The bolt 104 passing through the hole 104a and the washer 1048 located between the head of the bolt 104 and the plate 86 and the bolt 10
It is pivoted to the underside of the base plate 86 by suitable means such as a pair of lock nuts 104c threaded onto the base plate 86. Two adjacent corners of motor 60 are slidably attached to base plate 86 by similar nut and bolt assemblies as shown, with bolts 95, 97 of each assembly attached to plate 86.
6 are inserted into slots 95a and 97a that pass through them, respectively. The opposite corner of the motor is also slidably attached to plate 86 by a nut and bolt assembly, the bolts 99 of which pass through slots 99a in plate 86. End 1 of a helical spring 106 or other suitable spring means
01 are connected to the heads of bolts 99 and a bracket assembly 106, respectively, and the bracket assembly 106 is fixed to the upper surface of the substrate 86 as shown. Spring 103 and associated structure are arranged such that bolt 99 is located near the longitudinal center of elongated slot 99a when the sewing machine is at rest.

While the sewing machine is running, the step motor 60 is connected to bolts 95 and 97.
, 99 slides into the corresponding slot, the bolt 104
The spring 103 applies a force to the bolt 99 to maintain continuous tension on the cable 76 via the motor pulley 68. It has already been proposed to use the motor mounting structure described above to use the motor mass to dampen shocks on the cable system.

As shown in FIGS. 1-3, 6, and 7, a cable 74 for controlling the radial movement of the extension arm 110 is connected to the
The end is fixed to a post 112 depending from near the end of the arm 110 on the opposite side from the workpiece holder. Cable 74 passes from this point around a free rotating pulley 114 which is pivoted to base plate 86 on the underside of arm 110 by suitable means such as screws. Cable 74 passes from pulley 114 to motor pulley 66, where the cable makes approximately 21/4 turns. The cable 74 is connected from the motor pulley 66 to the screw 11.
Free rotating pulley 11 pivoted to base plate 86 by 8
6 and arm 110 by suitable means such as screws.
The free-rotating pulley 120 is pivoted to the lower base plate. The other end of the cable 74 coming out of the pulley 120 is fixed to a post 122 depending from the other end of the arm 110 near the workpiece holder 56.

As best shown in FIG.
The two corners are pivoted to the underside of base plate 86 by nut and bolt assemblies 123 similar to those described in connection with step motor 60. As previously stated, adjacent corners of step motor 58 are slidably supported on the underside of base plate 86 by nut and bolt assemblies 124 and 125, and opposite corners are supported by nut and bolt assemblies 124 and 125. It is slidably supported under the substrate by 126. Spring 128 connects its ends to assembly 126 and bracket assembly 130, with the bracket assembly being connected to substrate 8.
It is fixed on the top surface of 6. As mentioned before, spring 1
28 applies a force to assembly 126 such that cable 74 is maintained under continuous tension via motor pulley 66.

When the motor shaft 70 rotates, the pulley 120 and the column 122
The cable portion between the two pulleys 114 and the column 112 simultaneously expands or contracts depending on the direction of rotation of the shaft. Therefore, the third
As seen in the figure, the clockwise rotational movement of the motor pulley 66 is converted into a linear movement of the cable end portion, and the extension arm 11
0 and the workpiece holder 56 and the needle and pivot pin 108.
This movement is in the +Y-axis direction by causing a radial movement toward the outer edge 132 of the substrate with respect to. Also,
As motor pulley 66 rotates counterclockwise, arm 110 and workpiece holder 56 radiate away from edge 132, which is in the -Y axis direction. Therefore, energizing both the X and Y step motors 60, 58 simultaneously causes the workpiece holder to pivot and radiate in the X and Y directions simultaneously.

- At first glance, the coordinate system in which the workpiece holder moves appears to be polar coordinates, i.e. the radiation component provided by the movement of the extension arm 110 on the pivot arm 92 and the rotation of the pivot arm 92 about the pivot pin 108. Although it appears to be a coordinate system with an angular component provided by rotation, this system is provided with means for moving the workpiece holder relative to the needle 54 in a manner that approximates a Cartesian coordinate system. ing. This means includes a device for transforming the circular raphe normalized by this movement as the workpiece holder rotates about the pivot pin 108 to approximate a straight raphe as would occur in the Cartesian coordinate system. This approach to a straight raphe is automatically accomplished by reducing the effective length of extension arm 110 by an amount based on the rotational momentum imparted to the workpiece holder by pivot arm 92. The amount by which the effective length of the extension arm is reduced for a particular angular position of arm 92 is: (1) column 12;
(2) the distance from both needle 54 and pivot pin 108 from post 12 to the axis around which pulley 120 rotates;
(3) the inner radius of the circumferential groove of pulley 120. Pulleys 120 are spaced on the negative side of the line between pivot pin 108 and needle 54 by a distance equal to the radius of the pulley plus half the thickness of the cable.

According to the illustrated structure, the post 122 is a circle (the circle that is the inner circumference of the pulley 120) at the fixed position of the step motor 58.
The post 122 follows a path called an involute, so that the post 122 is increasingly drawn radially inward as the angle of rotation of the arm 92 increases from the central position. As already mentioned, the required radial movement is achieved by ensuring that the sewing operation is performed along a nearly straight path when only rotational movement is applied to the workpiece holder by the cable 76. be.

As pivot arm 92 pivots about pin 108 from its central position, cable 74 wraps and unwraps around pulley 120 in either a clockwise or counterclockwise direction. As a result, for the same angular rotation of the arm 92 from the center position, the compensation effect differs depending on the direction of rotation from the center position. In order to keep this compensation as symmetrical as possible, it is desirable to make the radius of pulley 120 as small as possible to accommodate proper handling of cable 74.

As discussed below, each step motor 58, 60 has a homing assembly and a limit assembly. Homing assemblies for these step motors are used to position the work holder at a predetermined home position in the X and Y axes during a homing operation. The control system automatically enters a homing operation before starting and after completing the sewing pattern operation, during which the work holder is moved to the reference (home) position.

The home position can be preselected for the needle by appropriately adjusting the X- and Y-axis homing assemblies;
The position is selected to allow movement of the workpiece through the full range of the sewing pattern allowed by the limit assembly. Since the step motor is used in an open loop during sewing operations, even under program control, the homing assembly eliminates cumulative errors in reference position between successive sewing operations by starting each sewing operation at the same home position. To prevent.

The workpiece holder and the workpiece held in it are positioned very precisely at the beginning and end of the sewing operation, so even when a high degree of positional accuracy is required, it is convenient to use an auxiliary tool such as a slit knife for cutting buttonholes on the sewing machine. Can be used in conjunction with

The limit assembly is used to confine the movement of the workpiece holder to a predetermined range of positions, thus limiting the movement of the workpiece holder relative to the needle in the X and Y axes.

In this way, interference between the clamp of the workpiece holder and the sewing machine needle is prevented. If this obstruction occurs, there is a risk of damage to the sewing machine and injury to the operator of the sewing machine.

As will be seen below, the limit assembly is adjustable to vary the freedom of movement by the workpiece holder relative to the needle.

Since the homing and limiting assemblies for both step motors are substantially the same, the X-axis step motor 6
The homing assembly and limit assembly related to 0 will be described in detail. As shown in FIGS. 1, 2, and 11, a support plate 134 is attached to the top surface of a substrate 136, and a fork-shaped support bracket 138 is attached to a pair of screws 14.
The support plate 134 is fixed by 0a and 1408.

Screws 140a, 1408 pass through slots in support plate 134 to allow slight adjustment of bracket 138. As shown in FIG. 1, a shaft 142 is journaled in plates 146a, 1468 of bracket 138 by suitable bearings 144a, 1448, and rotatably mounted shaft 142 extends through base plate 136 and connects pulley 14.
8 is fixed to the lower end of this shaft. A pulley 150 is fixed to the lower end of the motor shaft 72, and the endless belt 15
2 extends around pulleys 148, 150 such that shaft 142 is driven by motor shaft 72.

The X-axis homing assembly 154 is shown in FIGS.
This is best shown in Figure 2. This homing assembly 1
54 includes a homing disk 156 having a notch 158 and defining a radially extending edge 160 intermediate the notch and external portion 162, and a pair of bolts or screws 166a.
, 1668, and an optical sensor 164 attached to the support plate 134 by means of . The shaft 142 is inserted into a hole 168 passing through the disc 156, and the disc 156 is secured to the shaft 142 by a pair of screws 170 passing through threaded holes in a depending portion 172 thereof to the inner surface of the hole 168. . Therefore, the rotational movement of the shaft 142 is caused by the homing disk 156.
will be rotated.

As shown, the outer portion 162 of the disk 156 is passed between spaced legs 174 of the optical sensor 164, with one leg containing a light emitting diode and the other leg containing a blocking phototransistor. It is accommodated. Therefore, sensor 164 detects the presence or absence of notch 158 and leg 174
In response to a change in the state of passing or blocking light between the disc edge 1
60 generates a signal that changes state each time it passes the sensor leg 174. Based on the rotational position of disc 156 and disc edge 160, an output signal indicates to the control system the current position of disc edge 160 relative to the sensor;
This is used to determine the rotational direction in which the motor shaft 72 should be moved so as to drive the motor shaft 72 toward the sensor. As the edge 160 passes the sensor legs 174, the change in state of the sensor signal indicates to the control system that the edge is just passing between the sensor legs. If desired, the step motor can be stopped as the edge passes, and if the edge moves from the desired position, the controller reverses the direction of the motor to return the disc to the proper position. However, in a preferred embodiment, the homing assembly uses a somewhat different tool to provide greater precision in the alignment of the disk edge to the sensor and, therefore, the workpiece holder to the needle, as detailed below. It is used in a different way. In either case, it is clear that the homing assembly is used in closed loop with the control system and step motor to precisely position the workpiece holder in the homing mode.

The rotational position of the disk 156 and its edge 160 is
When fixing to 2, it can be adjusted using the screw 170.

Thus, by varying the angular position of the disc edge 160 relative to the shaft 142, the edge 160 is moved between the legs 174 of the sensor at different rotational positions of the shaft 142 and correspondingly different positions of the workpiece holder relative to the needle. It can be adjusted appropriately to pass through. In this way, the home position of the workpiece holder relative to the needle can be easily modified as desired. The operation of the Y-axis homing assembly in conjunction with the control system and the operation of the Y-axis step motor to home the workpiece holder along the Y-axis direction is the same as described above for the X-axis homing assembly.

As shown in FIGS. 1 and 13, the X-axis limit assembly 178 includes a pair of elongated mechanical stops 180, 182.
and a mechanical abutment rod 18 associated with these stops and extending between the projections 146a, 1468 of the support bracket 13.
It consists of 4.

The shaft 142 is inserted into a hole 186 passing through the vicinity of the negative ends of the stops 180, 182, and the stops 180, 182 are secured to the shaft 142 by a pair of screws 188, 190, respectively. are inserted into screw holes 192 and 194 passing through the holes 186, respectively. Thus, the angular position of the stops 180, 182 relative to the shaft 142 is adjusted by bringing the stops to the desired angular position before being secured to the shaft using screws 188, 190.

As shown in FIG. 13, the shaft 142 is allowed to rotate clockwise until the stop 182 abuts the rod 184. The mutually engaged stopper 182 and rod 184 then prevent further rotation of the shaft 142 and motor shaft 72, thus allowing the X-axis step motor to force the needle into a predetermined position in the X-axis direction. Stop the driven workpiece holder at the position. Similarly, the shaft 142 is connected to the stopper 1.
80 is allowed to rotate counterclockwise until it engages rod 184, at which time the workpiece holder is
It is stopped in a predetermined position in the opposite direction of the axis. Therefore, the axis 14
2 is allowed to rotate by an angle determined by the angular position of the stops 180, 182, and the workpiece holder moves within a range of positions along the X-axis until the movement is stopped by the stops. It turns out that this is permissible.

In this manner, limit assembly 178 limits the range of movement of the workpiece holder relative to the needle to prevent the workpiece holder clamp from impinging on the needle. Stopper 1 on shaft 142 is placed at the position where the workpiece holder stops.
This can be changed by appropriately adjusting the angular positions of 80 and 182.

This adjustment is particularly desirable with clamps of various sizes used to hold the workpiece in the sewing machine, each clamp having an appropriate adjustment of the stops 180, 182 based on how these clamps drive the sewing needle in the X-axis direction. Requires adjustment. The Y-axis limit assembly used to limit the range of allowable positions of the workpiece holder in the Y-axis direction is similar to that described above in connection with the X-axis limit assembly.

As shown in FIGS. 1 and 2, a pulley 198 is fixed to the lower end of a shaft 70 driven by a Y-axis step motor 58, and an endless belt 200 is used for driving a Y-axis limiting and homing assembly 204. It extends around pulley 202 and pulley 198 which are fixed to the shaft. As mentioned earlier, the Y-axis limit and homing assembly is
It is substantially identical to the shaft assembly and similarly operates to home the workpiece holder and limit its movement along the Y-axis direction. Therefore, the X- and Y-axis limiting and homing assemblies work together with the control system and the X- and Y-axis step motors to limit the movement of the workpiece holder over the entire range of positions and to control the workpiece. It has the function of positioning the object holder at a preselected home position in the directions of the X and Y axes.

Referring to FIGS. 6-8, the pivot arm 92 is attached to the pivot arm 92 by a screw 214.
It has a pair of free rotating rollers 210 and 212 and a pair of free rotating rollers 216 and 218 attached to levers 220 and 222, respectively, by screws 224. Lever 2
20, 222 are both connected to the pivot arm 92 by a screw 226 which is the center of their free pivoting movement.
installed on. The helical spring 228 is connected to the lever 220,
222, and the ends of spring 228 pass through appropriate holes in the lever. This spring 228 is the lever 220
. There is. rollers 210, 21
2 are spring-loaded toward a track extending longitudinally along the other side of the extension arm 110, so that these rollers are spring-loaded toward a track to hold arms 92 and 110 against the body. , and along their respective trajectories, the extension arm 110 moves longitudinally relative to the pivot arm 92 on these rollers. The extension arm 110 is +
When the posts 112 and 122 reach the radially farthest position in the Y-axis and -Y-axis directions, they are inserted into the notches 232 and 233 formed in the pivot arm, respectively, and the distance between these posts and the arm 92 is increased. Prevent interference.

As shown, a retaining plate 231 is mounted above the substrate 86 and forms a retaining edge 234 facing the pivot pin 108. The pivot arm 92 has a pair of holding members 235a.
, 2358, and these holding members depend from the front portion of the arm 92 at a position where the negative portion near the edge 234 of the holding plate 231 is inserted into the groove 236 formed in these holding members. Members 235a, 2358 move along edge 234 as arm 92 swings about pin 108 to maintain the forward portion of arm 92, 110 in a desired vertical position relative to substrate 86. In particular, the holding members 235a, 2
358 prevents the arms 92, 110 from lifting relative to the base plate 86 when a clamping force is applied to the working surface of the needle area of the sewing machine.

When assembled in this manner, the forward portion of the extendable arm 110, which is the portion closest to the workpiece holder, is connected to the roller 21.
2, 218, and the rear portion of the negative arm 110 rides on rollers 210, 216. A workpiece holder attached to extension arm 110 pivots with the pivot arm about pin 108 by means of a hole 217 in pivot arm 92 through which pin 108 passes. As mentioned before,
This pivoting movement is controlled by cable 76 which is also driven by step motor 60. Orbit 229,2
Extendable arm 110, which rides on thirty rollers 210, 212, 216 and 218, moves along pivot arm 92 in a generally radial direction relative to pivot pin 108. Cable 74, driven by step motor 58, controls the radial movement of extendable arm 110. Therefore,
Based on the direction of rotation of the motor, the post 11 of this cable
The negative end on the second side is pulled, and the other end on the post 122 side becomes loose, or vice versa. In this way there is always a positive drive controlling the radial movement of the extension arm.

Workpiece holder 56 includes a suitable clamping device or other structure to hold the fabric while being sewn. For example, the workpiece holder includes a lower clamp member located near the work surface of the sewing machine, and an upper clamp member that presses against the lower clamp member to hold the fabric or separates from the lower clamp member to release the fabric. including. Alternatively, the workpiece holder may include a releasable clamping member that holds the fabric and the label sewn onto the fabric separately. In either case, this control system is compatible with dual shaft clamp assemblies and others.

1-3 and 14, there is shown a lower clamp member 238 positioned near the working view 242 of the sewing machine, which clamp member forms a window 241 through which the fabric is sewn. It has a peripheral edge portion 239 . As shown in FIGS. 1, 3, and 7, the clamp member is secured to the front end 245 of the extension arm 110 by a pair of screws 247 so that its lower surface is located near the work surface 242. There is.

As shown in FIGS. 1-3 and 14, the workpiece holder also extends over the upper surface of the lower clamp member 238 to hold the fabric between the two clamp members 238 and 240 during sewing. fabric clamping member 24 to be pressed against
has 0. As shown, this fabric clamping member 24
0 has a pair of spaced holding elements 243 that form notches 244 through which the fabric is sewn, and these elements are attached to the sides of the lower clamping member when the fabric clamping member 240 is pressed against the lower clamping member. A distance approximately equal to the distance between the sides of the lower clamp member is spaced so as to abut the peripheral edge portions of the lower clamp member. As will be seen below, the dimensions of the notch 244 extending from the front end of the clamp member 240 are selected to be approximately equal to the dimensions of the label to be sewn onto the fabric.

Clamp member 240 also has a tab 246 extending upwardly from its rear portion and a pin 248 projecting forwardly from a front surface 250 of the tab. As shown, the clamp member 240 has a protrusion 252 extending rearwardly from near the lower end of the protrusion 246 for purposes described below. As best shown in FIG. 2, the upper clamp member 240 is attached to a clamp frame 254, and the prongs 246 are slidably received within the frame 254. As shown, the protrusion protrudes through the slot 256 in the frame of the pin 248, and the protrusion is located between the pin 248 and the first lower position where the pin 248 is located at the lower end of the slot 256.
is moved within the frame between a second upper position located at the upper end of slot 256.

As shown in FIGS. 1 and 3, the clamping device is
A pair of lower legs 260 and an ear 262 extending from the lower end of each leg 260
a forked retaining member 258 having a forked retaining member 258; This retaining member is secured by screws 264 passing through slots 266 such that adjustment thereof with respect to the longitudinal direction of arm 110 is effected by moving a pair of screws 264 within slots 266 of ears 262 prior to its fixation. and is fixed to the upper end of the extension arm.

Arcuate locking member 268 has a rear end 270 pivoted between legs 260 near the lower end of forked member 258 by suitable means such as a pin 272 extending through legs 260 and locking member 268 as shown. have

An air cylinder 274 is also provided for actuating the locking member 268 and clamping device. A rear end 276 of cylinder 274 is pivoted between ears 278 by suitable means such as a pair of spaced ears 278 extending from the upper end of retaining member 258 and a bolt 280 extending therethrough. ing. The locking member 268 has a bracket 282 extending upwardly from its central portion and a cylinder 274.
The front threaded end 284 of plunger 286, which is housed in
It is fixed in position by suitable means such as 90. As shown, a flange 29 extends from the clamp frame 254.
1 is secured to the front end 292 of the locking member 268 by a pair of screws 294.

Prior to the sewing operation, the pressure in cylinder 274 is reduced and plunger 286 is retracted into the cylinder.

In this condition, locking member 268 is driven around pin 272 to lock locking member 268 and associated clamping frame 254.
and in the raised position, the clamping member 240 is spaced from the lower clamping member 238 while in the first lower position to permit further extension of this member below.

As shown in FIGS. 1-3, an air cylinder 296 fixed to the clamp frame 254 is supplied with an air source.

The air cylinder has a movable piston 298 that abuts the upper surface of the protrusion 252 of the fabric clamping member 240.

Air cylinder 296 connects piston 298 to protrusion 252
, the clamping member 240 is driven to the first lower position and the pin 248 on the lug 246 abuts the lower part of the slot 256, which acts as a stop. In this condition, fabric clamping member 240 is spaced apart from upper label clamping member 300 by a distance approximately equal to the length of slot 256, and fabric clamping member 240 is also spaced above lower clamping member, as previously discussed. Open.

When the operator wants to perform a sewing operation, the operator must hold the lower clamp member 2.
38 and the portion of the fabric to be sewn is positioned in the window 241 of the lower clamp member 238. Next, the operator applies the petal clamp no. 1 switch and pedal clamp no. Press on the first leg of a known type with a separately actuatable single-pole, double-throw switch, referred to as a 2-switch. As discussed in connection with the control system of the present invention, both switches have normally closed contacts, normally open contacts, and a common ground terminal. Therefore, the normally closed contacts of these switches are each grounded via a common terminal before activation. When the foot pedal is pushed down to the first position, Betal Clamp No. 1 switch is activated and this switch opens the normally closed contact and closes the normally open contact, thereby grounding the normally open contact and removing the normally closed contact from ground via the common terminal.

As described below, this control system operates as follows for pedal clamp No. The signal from one switch is used. When the switch is actuated and the normally open contact is grounded, the control system generates a signal that provides a moderate air pressure to the air cylinder 274 from the air source. To this end, plunger 286 is partially driven by cylinder 274 and thus locking member 238 and fabric clamping member 2
40 is lowered to a position where it abuts the lower clamp member 238, so that the fabric is held between the clamps 238 and 240 at this time. However, the force exerted by cylinder 274 on clamping frame 254 through locking member 268 is less than the force exerted by air cylinder 296 on clamping member 240 through piston 298 and projection 252, and thus clamps the fabric. The member 240 is in a first lower position with the pin 248 at the lower end of the slot 256 and the fabric crank member 240 spaced from the upper label clamp member 300 even when abutting the fabric.

Next, the operator attaches the label to be sewn to the clamp member 2.
40 notches 244, so the label is on top of the fabric. Since the notch 244 is approximately the same size as the label as described above, it acts as a guide for placing the label. After inserting the label, the operator moves the first foot pedal overcoming a slight force exerted by the pedal's spring means, which indicates to the operator the condition of the pedal between the first and second positions. Press down fully to the second position. When the pedal is in the second position, the pedal clamp No. 2 switch is activated, so the normally open contact of this switch is grounded, and the normally closed contact of this switch is removed from ground.

In response to the signal from this switch, the control system generates a signal to create sufficient pressure in cylinder 274 from the air source. While in this state, cylinder plunger 2
86 through the locking member 268 to the flange frame 25.
4 is applied to this frame 254 and the clamp member 24.
0 and is greater than the force applied by air cylinder 296. Accordingly, the clamping frame 254 is driven toward the sewing machine work surface 242 with the upper clamping member 300 attached to the frame 254 by a pair of screws 302, and the protrusion 252 of the fabric clamping member 240 on the opposite side is driven towards the sewing machine work surface 242.
collides with piston 298 and returns piston 298 into cylinder 296.

When the lock member 268 and the clamp frame 254 are sufficiently lowered, the label clamp member 300
40 to hold the label on the fabric. As shown, the clamping member 300 allows the fabric and the label to form a window 306.
In order to be sewn through the lower clamp member 2
38 and a peripheral edge 304 forming a window 306 aligned with the window 241 of the clamp member 240 and the notch 244 of the clamp member 240. In this state, the fabric clamping member 240 is placed in the second upper position, with the clamping protrusion 246 positioned at the upper end of the slot 256 and the piston 298 pushed fully into the cylinder 296 by the clamping protrusion 252. Can be lowered.

At this time, the fabric and label are held in position for the purpose of starting the sewing operation, and the operator then depresses the second pedal to begin operation. As can be seen in connection with this control system, the operator may or may not release the first pedal as he prefers at this time, but eventually The 1st pedal must be released.

When the first pedal is released, the normally closed contacts of the switch are grounded again and the normally open contacts are removed from ground.

The second foot pedal also has a single-pole, double-throw activation switch of the known type known as a pedal go switch, the normally closed contact of which, as before, is connected to ground via a common terminal. When the switch is activated by pressing down on the pedal, the switch closes the normally open contacts and opens the normally closed contacts, thus grounding the normally open contacts and removing the normally closed contacts from ground.

Assuming the various clamps are in proper position for further extension, the control system generates a signal responsive to the activated pedal go-inch and enters the homing state to continue the sewing operation, during which time the fabric is The label is sewn.

When the second pedal is released, the pedal go switch is in its normal state with its normally closed contacts grounded and its normally open contacts removed from ground.

As shown in FIG. 1, a clap detection switch 308 is mounted between legs 260 of retaining member 258, with a contact member 310 of the switch abutting the rear surface of locking member 268. When locking member 268 and associated clamp are lifted by cylinder 274, locking member 268
68 moves contact member 310 toward switch 308 .

In this condition, the switch opens its normally open contact and removes it from ground. The locking member 268 descends and the label clamping member 300
is driven toward fabric clamping member 240 , contact member 310 is moved away from switch 308 . In this state, the switch closes the normally open contact and is grounded.

It can therefore be seen that the signals from switch 308 indicate whether the various clamps are in proper condition to perform a sewing operation. Since it is undesirable to begin operation when the machine is in a condition where the clamp is not fully locked, the control system uses the signal from switch 308 to prevent the initiation of a sewing operation unless the clamp is in the proper condition. After activation of the pedal clamp switch of the first foot pedal,
Due to the time delay in completing the clamping operation, it is possible for the operator to activate the pedal go switch of the second foot pedal before the clamp is locked.

Additionally, the control system prevents the initiation of a sewing operation if the clamp is not properly locked due to machine malfunction.

Therefore, the necessary conditions for starting the sewing operation are that the sewing operation is activated by operating the pedal go switch or the second pedal, and that the clamp is sufficiently locked as determined by the clamp detection switch 308. It is that you are. Of course, the first condition is never met unless the pedal clamp switch is activated before the pedal go switch is activated. This is because the clamp is not lowered and movement is prevented by the signal from switch 308. If the pedal go switch is activated before the clamp is fully locked, the control system will delay until the clamp is fully locked, as indicated by switch 308.
After the locking is completed, the homing state is entered and the sewing operation is started without further activation of the pedal go switch.

As shown in FIG. 1, a thread breakage detector 312 is mounted above the needle 54 of the sewing machine. This detector 312 measures thread tension and provides a signal to the control system indicating whether the thread being fed to the needle is broken.

Thread cutter 314 is shown in FIGS. 1 and 2. The thread cutter has a dual actuating air cylinder 316 actuated from an air source by a four-way solenoid. During the cutting of the thread, air is supplied to the - side of the piston of the cylinder through the connector 318, and air is discharged through the second connector 320 on the - side, so that the piston of this cylinder is moved to the left as seen in Figure 1. and moves the activation arm 322 connected to this piston away from the cylinder 316. The thread cutter pivots on a locking member 324, and a first swinging blade 326 is fixed to the upper end of this locking member 324.
A lever arm 328 extends from the lower end of locking member 324. The lever arm 328 has a ball member 320 depending from its outer end which is pivotally inserted into a U-shaped portion 332 of the activation arm 322.

Therefore, during the cutting operation of the thread cutting machine, the activation arm 322 driven by the cylinder piston is activated by the ball member 330.
moves lever arm 328 while rotating within U-shaped portion 332 of activation arm 322 . − side lever arm 32
8 rotates the locking member 324, which drives the first blade 326 and the thread toward the second blade 334, so that the time series in which the swinging blade passes under the second blade is It can be cut.

As shown in FIG. 1, the piston and swinging blade 32 during cutting
The travel distance of 6 is the rod 3 connected to the opposite end of the piston.
38 so that the blade 32
6 is in the desired final position to cut the thread.
collides with cylinder 316.

After the thread is cut, air is introduced into the - side of the piston through connector 320 and exhausted from the other side of the piston through connector 318, when the piston returns to its original position.
The swinging blade 326 is then positioned to begin cutting. As shown in FIG. 1, a continuous force is applied to activation arm 322 by a compression spring 340 extending between a bracket 342 secured to the sewing machine and a connecting rod 344 extending from arm 322. This spring ensures smooth movement of the blade 326 and the resulting cutting action, and the coupling arm 32
2 and the blade 326 to be easily returned to their original positions for the next cut. As stated in connection with the control system, the cutter is automatically activated to cut the thread at the end of the sewing operation, and the workpiece holder is moved from the first position to the second position while the fabric is not being sewn. Moved to spaced positions.

For proper operation of the device, the needle must move the workpiece holder to the home position after the sewing cycle is complete so that the clamp can be raised to remove the sewn workpiece from the holder. The sewing machine must be stopped in the raised position to complete the tightening cycle. Cutting of the thread also takes place as part of the "needle up" sequence. These functions are provided by a commercially available device 46, Click Model No. 8, shown in FIG.
Figures 1 and 1 carried out by 00-ST-362
As shown in FIG. 6, the electro-mechanical synchronization unit 62 has an adapter 350 attached to the sewing machine hand wheel 64 so that the adapter rotates therewith. Bearing 352, rotating slip ring assembly 34
8 and photovoltaic commutation ring 554 are adapter 3
A screw 358 is attached to a shaft 356 extending from 50 and extends into the outer end of this shaft so that they rotate together with the hand wheel.
The position is fixed by Fixed connector portion 360 of assembly 348 includes four electrical brushes 362, 364, 36.
6, 368, insulating portions 370, 372 and 374
are three slip rings 376, 378, when brought into contact by brushes 362, 364, 368, respectively.
380 is electrically disconnected. Brush 366 is used to supply current from quick device 346 to the slip ring. Current from the three active slip rings is supplied to quick device 346 to cycle its operation and separately supply the needle down position, needle out position and cut signals. As discussed further below, the synchronization unit 62 associated with the control system and the quick device allows the sewing machine to (a) operate at high or low speeds and (b) operate the thread cutter 314 in conjunction with a thread tension release solenoid. (c) Set the needle to the raised position and stop the sewing machine. Figures 1 and 15
As shown, synchronization unit 62 and the sewing machine are driven by quick drive 346 via an endless belt 382 passing around pulleys 384 and 386 connected to the unit and quick drive 346, respectively.

As best shown in FIG. 16, a fixed support member 388 is attached to the bearing 352.

A first bracket 390 is attached to the end of the support member 338 by suitable means such as screws 392, and a plate 394 is secured to the upper flange 396 of the bracket 390 by a pair of screws 98. second bracket 40
0 is also attached to the outer end of support member 388 by a pair of screws (not shown) that pass through holes 402 and slots 404 in bracket 400. Bracket 400 is adjusted to the desired position through the range of motion allowed by slot 404. The second plate 406 is 1
Flange 4 of bracket 400 is secured by a pair of screws 410.
It is installed on 08.

As shown, light reflective transducers 412, 414 are mounted on the inner surfaces of plates 394, 406, respectively, in a position where their notches 416 are aligned when rotated with ring 354, and have a non-reflective surface coating therein. has. In operation, light from the transducers 412, 414 impinges on the surface of the ring 354 and is reflected to the light sensing portion of the transducer to generate an output current. The output current of the transducer is passed through the non-reflective notch 4 in the ring 354.
16, the amount of reflected light is significantly reduced when aligned with the notch.

Therefore, as the edge of the notch aligns with each transducer, the output signal changes, and as discussed below, the signal change when this notch first aligns with the transducer can be used in the control system to Indicate the position of the needle.

During normal operation of the sewing machine, a signal from the main transducer 414 is fed into the control system, and this signal, referred to as the needle pull sensor P signal, is detected when the needle attempts to pull out of the fabric and when the work holder damages the needle. Instruct when it is okay to move without giving. The position of transducer 414 can be modified by making appropriate adjustments to bracket 400 to signal the exact time desired.

During normal operation, the auxiliary converter 412 is removed from the control system as controlled by the normal-repair selection switch.

However, the sewing machine enters the repair state by using the switch, and during this time the functions of the sewing machine are inspected by the repair person, but at this time the signal from the main converter 414 is removed from the control system and the auxiliary converter A signal from 412 is supplied to the control system and used as the needle removal sensor P signal. Although it is under the control of the program, while in the repair state, the sewing machine operates slowly even if it receives a quick command. Therefore, during repair conditions to ensure movement of the workpiece holder while the needle is out of the workpiece, the timing of the sewing machine is controlled by the auxiliary transducer 4.
12 to be determined.

The quick device 346 is designed commercially to be activated by stepping on the foot, but the device in this example is fully automated, and for ease of understanding with reference to FIGS. 15 and 17. More on that.

This quick device 346 has a sweater 418 that drives the shaft 420, and a flywheel 422 that drives the shaft 420.
A pulley 424 is fixed near the opposite end of this shaft. Device 346 has another shaft 426 slidably and rotatably mounted to its housing 428. The motor pulley 386 that drives the belt 382 has two
A main clutch and brake disc 430 is attached to the opposite end of the shaft 426 and is secured to the other end of the shaft 426. The worm wheel 432 is rotatably mounted to the shaft 426 intermediate the disc 430 and the wall of the housing 428 and has a main braking surface 434 facing the disc 430 , and the flywheel 422 has a main braking surface 434 facing the disc 430 . It has a clutch surface 436.

The shaft 426 moves between a first position where the disc 430 abuts a clutch surface 436 of the flywheel 422 and a second position where the disc 430 abuts the main braking surface 434 of the worm wheel 432. Therefore, in the first position, the axis 426
is directly coupled to motor shaft 420 through the main clutch assembly, and shaft 426 and the sewing machine are driven at relatively high speeds. As will be seen below, the worm wheel 432 is driven at a relatively slow speed and then stopped. The worm wheel 432 rotates at a slow speed, and the shaft 426 rotates at a slow speed.
, the shaft 426 and the sewing machine are driven at a slow speed. Because the disk 430 is the flywheel 422
This is because the main clutch surface 436 of the worm wheel 432 comes off and abuts against the main brake ai 454 of the worm wheel 432, and the main clutch 55 has a brake solenoid (not shown) connected to the air cylinder 468 and a lever connected to the shaft 426. (not shown). When this clutch-brake solenoid is energized by the control system, a lever is actuated to operate the sewing machine at a slow speed, braking the sewing machine and moving the shaft to a second braking position for thread cutting. 426 and disk 430 are moved.

A free rotating pulley 440 is mounted on a worm wheel 442 which is coupled to worm wheel 432 by a worm gear 444 . Worm wheel 442 is splined to an auxiliary clutch and a brake disc 446 which is moved by a pair of solenoids (not shown) to a first position where disc 446 abuts auxiliary clutch 448 on pulley 440. Which disk is the auxiliary brake surface 45 of the housing 428?
and a second position meeting zero. As shown, the endless belt 452 is wrapped around the pulleys 424 and 440 so that the free rotating pulley 4
Drive 40.

When disc 446 moves to the first clutch position, pulley 440 drives disc 446 through clutch face 448. Since the disc 446 is splined to the shaft 442, the disc 446 and the shaft 442 drive the worm wheel 432 through the worm gear 444, and the speed is controlled by the pulley 424.
, 440 and the worm gear, it is appropriately smaller than the motor shaft 420. When the disc 446 moves to the second braking position, the braking surface 450 stops the rotation of the disc 446 splined to the worm ring 442, thereby stopping the rotation of the worm ring 452.

Under program control, the control system typically starts the sewing machine at a high speed in response to a sequence of high speed commands already stored in the program memory. In this state, the control system connects the faceplate 436 to the clutch face 436 of the flywheel 422 in order to operate the sewing machine at a high speed as previously described.
Activate the main clutch/brake solenoid to hit 0.

At the same time, the disc 446 can be brought into abutment against the auxiliary clutch surface 448 of the pulley 440.

In this case, the worm wheel 432 rotates, but since it only rotates freely on the shaft 426, it does not affect the operation of the sewing machine.Just before the sewing operation is completed or just before the workpiece holder is moved without sewing. Then, the control system operates the sewing machine at a slow speed during the learning period in response to a small number of slow sewing commands in memory. At this time, the control system de-energizes the main brake/clutch solenoid so that the disc 430 is connected to the worm wheel 432.
engages the braking surface 434 of. Since the worm wheel 432 is driven at a slow speed, the shaft 426 and the sewing machine are decelerated to a slow speed. Quick device 3
43 utilizes the needle drop position signal from slip ring assembly 348 of synchronizer unit 62 to determine when the sewing machine is decelerated to the desired slow speed, as previously discussed. When the sewing machine is running at a slow speed and the last signal in response to the slow speed command is sent to the quick device 3 by the control system.
46, device 346 performs the following operations.

The thread cutting signal from unit 62 changes state on the way from the needle down position to the needle up position of the sewing machine.

Once the above two conditions have been met, the quick device 346 waits for a first needle down condition as indicated by one of the signals from the slip ring assembly of the unit 62. After receiving the needle down signal, The quick device determines the change in state of the cut signal that occurs before the next needle up position of the sewing machine. After receiving this signal, the quick device 346 begins activating the tension release solenoid to release tension on the thread, and then
Activation of cutter 314 is initiated to cut the thread as described in connection with FIGS. Once the thread is cut, a cut complete signal is generated to the control system indicating that the cutting operation is complete. - On the other hand, the quick device 346 stops the sewing machine at the needle raised position in the following manner.

That is, immediately upon receiving the thread cutting signal from unit 62, quick device 346 moves disc 446 to brake surface 450 as shown in FIG. The reciprocation of the needle is stopped at the needle raised position, and the needle is pulled out of the workpiece.

As mentioned above, the preferred addressable storage element in this embodiment is a programmable read-only memory unit, hereinafter referred to as a PROM. According to a suitable device, the PR of the operator of the automatic sewing machine according to the invention
Programs (ie, commands or sequences of commands) for the OM can be modified or added. Depending on the information capacity of each storage location and the information content of each command, a single command can be transmitted to a single storage location. On the other hand, in the preferred embodiment, each command utilizes multiple storage locations. The stored sequence of commands dictates the pattern that the automatic sewing machine's workpiece holder follows. In this particular embodiment, the PROM has a randomly addressable binary 8-bit word for each storage location, for a total of 256 locations.

It includes commands and workpiece holder positioning data in the X-axis and Y-axis directions. In the preferred embodiment, there are four types of commands. The first command instructs the movement of the workpiece holder without sewing, the second command instructs the movement of the workpiece holder in slow sewing mode,
The third command directs movement of the workpiece holder in the high speed sewing mode, and the fourth command instructs the end of the sequence of commands and directs movement of the workpiece holder to the home position. Each of the first three commands above utilizes two groups of positioning data to form a complete command. Each data group includes the movement direction and step information (movement amount) of the workpiece holder in each of the two coordinate directions in order to determine the next position of the workpiece.

Although this information can be obtained in a variety of ways, it is preferred that each data group be constructed as a number with a positive or negative sign representing the direction of force of movement of the workpiece holder and the number of steps. Therefore, this particular embodiment of the invention utilizes an open-loop approach, i.e., the workpiece holder is moved from one position to the next during a sewing operation without the need for feedback to indicate the current position. Ru. The maximum allowable number of steps in the coordinate direction in each sewing cycle is 15 per command, but the number of steps allowed while the machine is running at high speed is subject to possible timing limitations, as discussed below. and decreases slightly, for example 12.

In this embodiment, each command utilizes only 12 bits written in binary. The specification of the command portion of each command requires 2 bits, and the workpiece holder positioning data requires 5 bits for each coordinate direction, of which 1 bit is in the (positive or negative) direction, and the step is 4 bits. The control system reads three separate 4-bit words for use as a single 12-bit command.

- Once the PHOM is programmed, i.e. PR
Once the OM has received a sequence of commands in a predetermined order to indicate the desired sewing pattern, the sewing machine is ready for operation.

Referring now to FIG. 18, there is shown a cabinet 454 housing the control system of the present invention.

As shown, cabinet 454 has a swing door 460 that opens to connect a programmed PROM 458 to the control system, and the PROM's electrical connector 460 is inserted into socket 462.

A program selection rotary switch 464 is used to select a mode of operation for program control by setting the switch to one of a plurality of positions 466, as indicated by an appropriate display on the front panel of the cabinet. It is provided.

As seen below, each PROM has two machines, designated Bank A and Bank B, containing 256 4-bit words. The control system begins reading the 4-bit words at the low-order bit address of one bank and reads the three 4-bit words from the sequential storage locations in this given bank to generate the 12-bit command for each timing cycle of the sewing machine. form. In this manner, the control system sequentially reads data from the banks. If the two programs are short enough to each be programmed into 256 4-bit words, one program can be placed entirely in bank A and the other program can be placed in bank B.

Prior to commencing the sewing operation, the operator selects the desired program by setting switch 464 to the appropriate position 466. One of the locations 466 is provided for bank A and the other is provided for bank B. When the sewing operation is completed in this state, the control system remains selected in the selected bank until the switch setting is changed. For example, if bank B is selected by switch 464, each sewing operation will be performed as directed by the program contained in bank B as long as the switch remains in the bank B setting. As shown, lamps 467, 469 are provided to indicate the particular program bank currently being utilized by the control system;
67 represents bank A, and lamp 469 represents bank B.

Alternatively, the operator may set switch 464 to a third position, referred to as remote setting or remote mode. In this state, the operator can change the program control between backs A and B as desired by depressing the foot pedal. Assuming that a given sewing operation is being performed as directed by the program contained in bank A, each subsequent sewing operation will be controlled by the program in bank A until the foot pedal is depressed. Ru. When the operator presses the foot pedal, the remote program selection switch is activated.

For this reason, the next sewing operation will be carried out according to the program in bank B. By depressing the foot pedal again, bank A will be selected again, and if desired, the banks can be selected so that sewing operations can be carried out alternately with the two banks. You can.

If a program is too long to fit into a single bank, the first portion of the program is placed in bank A and the remaining portion is placed in bank B. In this case, the operator selects the fourth position 466 with switch 464 to place the control system in the "extension mode." In this state, the control system during each sewing operation first reads the program portion included in bank A. Once this program portion is completed, the control system automatically begins reading the remaining portions of the program placed in bank B to complete the sewing operation. In this way, a relatively long program can be used to perform long sewing operations without interrupting the sewing sequence. lamps 467, 469
also indicates which program bank is being used by the control system during remote mode and extended mode.

Of course, the PROM may be replaced between sewing operations in order to connect different programs to the control system. Just to be safe, power is removed from the control system while the PROM is being replaced. As shown, an interlock switch 468 is provided which is activated by door 456. When the same door 456 is opened when replacing PROM, interlock switch 4
Contact 68 is also opened to remove power from the control system. PROM
When the door is closed after the switch 468 has been changed, the contacts of the switch 468 are also closed, connecting the power source to the control system. Therefore, a necessary condition for operation of the control system is that door 456 be closed.

A plurality of suitable switches 4 are installed on the cabinet front panel 474 to control and monitor the operation of the control system and the sewing machine.
70 and a lamp 472 are provided. As discussed in more detail below, one of the lamps 472 indicates that a step motor drive circuit overtemperature condition exists, and the other lamp indicates that control system power is on.

As you can see below, the -hour reset switch 4 on the panel
When 70 is activated, the control system is initialized for the purpose of performing a sewing operation. Activation of this switch may also be used in an emergency situation to terminate the sewing operation before normal completion. Other switches, called clamp switches, are used to lower the clamps or to place these clamps under automatic control of the foot pedal and the control system, without thread, e.g. when using a sewing machine for inspection purposes. A third switch is used to disable the operation of the thread breakage detector. A fourth switch, referred to as the pattern trigger switch, inhibits control of the X- and Y-axis step motors during machine inspection. used for. Of course, one of the switches 470 may be used to control power on and off to selectively power the control system and the sewing machine.

The normal-repair selection switch has already been mentioned, but when this switch is set to ``normal,'' the main needle dropout detector 414 of unit 62 is activated to synchronize the start of movement of the workpiece holder.
Since the sewing operation is performed using signals from the machine, it operates in a normal state. Setting the Normal-Repair selection switch to "Repair" is done by a repair person while servicing the sewing machine. In this state, the sewing machine is in the JOG position on panel 474.
It will not work until the switch is activated. When the jog switch is activated, it will sew at a slow speed under program control until it is reset. As previously mentioned, the control system uses the auxiliary needle drop detector 412 of unit 62 to synchronize movement of the workpiece holder during repair.

Referring to FIG. 19, the operation of the sewing machine is controlled by central control logic 676. First, the operator places the workpiece at an appropriate position on the workpiece holder. Then,
While fully depressing the first foot pedal 678 of the sewing machine and placing the fabric and label on the workpiece holder as shown above, the pedal light no. 1 and no. Upon activation of the 2 switch, central control logic 676 generates a signal to lower the clamp and hold the fabric and label. After the clamp has been lowered, the operator depresses the second foot pedal 679 to activate the pedal go switch and the sewing machine begins automatic operation when the clamp is fully closed as indicated by the clamp detection switch 308. In normal operation, a homing cycle is first started. Thereafter, the first command from the PROM, that is, the storage element 458 is sent to the logic circuit 676 according to the setting of the program selection switch 464 on the front panel 474.
reads. This logic circuit is the appropriate number to drive the workpiece holder. ) responds by supplying pulses of electricity -
These pulses are sent to motor drive logic 684, 686 after the signal from mechanical synchronization unit 62. These drive logic circuits 684 and 686 are each connected to the power drive circuit 6.
These drive circuits drive the step motors 58, 60 in a desired direction and by a desired amount of rotation.

The pulses to the drive logic circuits 684, 686 are made irregular to increase the cycle rate of the sewing machine and to prevent unwanted vibrations and thus undesirable feeding of the workpiece toward the needle. be. Therefore, the workpiece actually moves intermittently, and the workpiece is stationary when the needle is inserted into the workpiece. More specifically, central control logic 676 includes means for spacing the first three pulses and the last two pulses of the series of pulses further apart than the remaining intermediate pulses.

If the number of pulses supplied to the step motor is three or less, the amount of current from the power drive circuits 688, 690 is reduced (by known means not shown) to further minimize step motor vibration. Make it.

Successive commands are then read and executed, then the next command is read and executed, and finally the last command is executed. In response to the last command, which is a stop command, the central control logic causes the quick switch to stop the sewing machine, cut the thread, and then begin a second homing cycle. The homing cycle is controlled by a central control logic circuit, which controls the homing optical detector 1.
The step motor is stepped in response to signals from 64 and 694 to return the workpiece holder to the home.

As another input to the central logic circuit, circuit 6 after cutting the thread
The cutting completion signal given from 97 and the thread breakage detector 31
2 is a thread breakage signal indicating that the thread in the needle is broken. Upon receiving the thread breakage signal from detector 312, control logic circuit 676 stops the quick device (stops the sewing machine) and stops the address counter 772 (FIG. 20) which sequentially addresses the storage elements to stop the workpiece. Further movement of the object holder is suppressed. Therefore, the address in address counter 772 is saved and control logic 676 waits for a signal from the front panel before starting again. As discussed below, once the thread or needle has been repaired and replaced, the operator restarts the sewing machine at the beginning of the sewing pattern or on a command following the command in which the thread breakage occurred.

Based on whether the command requests low-speed sewing or high-speed sewing, the control logic circuit 676 responds to the command by outputting a signal to the quick device control box 706 via the drive circuit 700 so that the sewing machine starts. Stitch at desired speed. When a stop command is read, logic circuit 676 deenergizes the main brake and clutch valve solenoid 708 associated with the quick device via drive circuit 704 to initiate a machine stop sequence.

The control logic circuit 676 of FIG. 19 is shown in greater detail in FIG. 20. The sequence circuit 722 connects (a) input from the synchronization unit 62, (b) clamp detector 308, (c) thread breakage detector 312, (d) cutter circuit 697, ( e) front panel 474 and (f) optical detector 164 in both coordinate directions.
, 694.

The signals from the switches on the foot pedals 678, 679 are read through the line labeled "Start". A gate logic circuit within this sequence circuit serves to shut down the sewing machine and workholder if proper motion conditions are not maintained. When the operator depresses pedal 679 to activate the go pedal switch, an enable signal on line 724 appears to begin the first homing cycle when the clamp detector indicates the workpiece holder is closed. This homing ensures that the workpiece holder is in a predetermined initial position at the beginning of the sewing sequence.

Homing circuit 726 cooperates with the homing detector and assembly to preset the workpiece holder at the desired sewing position in each of the two coordinate directions. As previously mentioned, these coordinate directions are referred to as the X and Y axes, corresponding to a direct coordinate system, but in the preferred embodiment this coordinate system has been modified to correspond more or less to a linear system. Based on polar coordinates. The homing circuit is responsive to an enable signal provided from sequence circuit 722 over line 724 and provides an output signal through lines 732, 734 to direction steering circuit 736 based on inputs from optical detectors 164, 694 through lines 728, 730. supply These output signals indicate the direction in which the step motor should rotate. Directional steering circuit 736
gates signals on lines 732 and 734 to drive logic circuits 684 and 686 to control circuit direction of motors 58 and 60.

Homing circuit 726 also enables pulse modification circuit 744 with a signal on line 745.

That is, the pulse modification circuit is enabled to output signal pulses from slow oscillator 768 via lines 746 and 748. Upon passing the home position (after approaching the first home position), this output is sent to the command line 7 from the homing circuit 726.
The signal through 51 is sent to motor drive logic circuits 684 and 686 in frequency reduced form by high speed correction circuit 749 as described below.

The pulse correction circuit 744 is connected to the line 75 from the driving/sewing circuit 750.
2,754 to gate these pulses to the motor drive logic. A signal on one of these lines controls gating pulses to motor 58 or 60, and a signal on the other line controls gating pulses to the other motor. The signals on lines 752 and 754 are provided by drive and sew circuit 750 when the circuit is in homing mode. That is, line 72 from the sequence circuit.
An enable signal on homing circuit 726 is provided by a set of signals on strands 756, 758 when drive/sew circuit line 750 is in the homing mode. - of line 756 or 758, thus lines 752, 754
When either signal is removed, the pulse modification circuit ceases to supply pulses to the corresponding stepper motor. This occurs when the home position in the corresponding coordinate direction is achieved. For the pulse modification circuit to operate properly during the homing cycle, there must be an enable signal on both line 745 and lines 752 and 754.

In all cases, the step motor will exceed the home position. When this occurs, the optical detector generates a signal that causes the appropriate motor to reverse and aim to the correct home position. This is determined by information from the optical detector on lines 732 and 73.
This is accomplished by changing one or both of the signals in step 4 to reverse the direction of one or both step motors. The homing circuit also includes additional logic to ensure that the final approach of each motor to its home position always occurs from the same direction regardless of the initial position of the workholder prior to homing. Furthermore, in the basic homing scheme, all homing movements after the first home arrival are accomplished at lower speeds generated by speed correction circuit 749. Homing circuit 726 includes means for providing a signal via command line 751 to reduce the step rate in response to the output of the optical detector. This mixing of step speeds results in rapid and accurate homing cycles.

In this particular embodiment, there is always at least one change in direction of approach to the home position for each motor at least once. While in the auxiliary homing state after motor reversal, if the second approach direction is not the same as the predetermined approach direction, the motor rotation direction is determined by the homing circuit logic that detects the approach direction. By automatically switching the direction again, the third (final) approach in the next auxiliary homing mode can be made from the predetermined approach direction. In this way, the positioning of the workpiece holder is achieved with high level accuracy.

As can be seen below, the workpiece holder passes slightly through the zero crossing position indicated by the home detectors 164, 694 for the X-ray and Y-axes.

Upon completion of the first homing cycle, a homing complete signal is sent from homing circuit 726 to sequence circuit 722 via line 760.

In response to this signal, the enable level on line 724 is immediately removed by the sequencing circuit, thus preventing further movement of the workpiece holder at this time. The sequence circuit then initiates a memory cycle by generating the level of the enable signal on line 762. This signal level allows words from storage element 458 to be addressed and read as follows. The output of the high speed oscillator 766 is the output of the low speed oscillator 7, which has an output of one-tenth the frequency of the high speed oscillator 766.
Decreased by the counter marked 68. A low speed oscillator 768 provides periodic pulses that determine the speed at which the step motor is driven. The enable signal on line 762 enables address counter 772 whose output on line 774 indicates the address of the word read from the storage element. The enable signal on line 762 is also 1-
3 counter 776, the output of which determines which one of the three receiving units the 4-bit word from storage element 458 is placed separately.

The three units are a storage unit 778 that receives the command part of the command and the positive/negative coordinate direction, and an up counter 778.
It consists of 80,782. The two up counters and storage units each receive workpiece holder position data and command information for each coordinate axis direction in an inverted form by an inverter 784 consisting of several invert gates.

To summarize the operation, after enabling the line 762, the high speed oscillator 766
The first clock pulse output of address counter 77
As the count increases by 2, a new 4-bit word is available from storage element 458 through line 790. The same clock pulse increments the count of counter 776, and this counter increases its output line, line 7 corresponding to a count of 1.
An enable signal is generated at 92. - This signal enables the up counter 782 to produce an inverted form of Y.
Stores a 4-bit word containing location data.

This reverse 4-bit word is sent to up counter 782 by the trailing edge (falling edge) of the same first clock pulse on line 793.
can be placed in

In the same manner, the next clock pulse from the fast oscillator increments the counts in counters 772, 776 and then inverts the addressed 4-bit word by the enable signal provided on line 794 from counter 776. It is read by up counter 780. This corresponds to two counts.

The third clock pulse from the fast oscillator is clocked at counter 7.
72,776 and then the addressed 4-bit word is read in reverse form into storage unit 778 by an enable signal provided from counter 776 via line 796. This corresponds to a count of 3. The enable signal on line 796 is also provided to sequence circuit 722, in response to which the enable signal on line 762 is removed. As a result, counter 776 is reset to zero and address counter 772 does not increase its count. Thus, one complete command of 12 bits is read from memory, portions of which are stored in each of up counters 780, 782 and storage unit 778.

All that remains to utilize this command is to translate it into motion of the step motors 58, 60 and into the desired sewing machine operation.

If the read command requires sewing operation, this is a "check"
A signal is provided by synchronization unit 62 to the sequence circuit through one of the lines marked , in response to which the sequence circuit generates an enable signal on line 797 indicating that the needle is away from the workpiece. . If the read command does not require a sewing operation, a signal equivalent to the needle removal signal from unit 62 is generated internally by logic means in the sequence circuit, which is possible on 797 immediately after reading the new command. generates a conversion signal. In either case, the enable signal on line 797 enables the pulse modification circuit, and the enable signal on line 75
2. When appropriate signals are present at 754, 842 and 844, the step motors are driven in response to the outputs of up counters 780 and 782. Lines 842 and 844 are from directional steering circuit 736.

After the enable signal is provided on line 797, the clock signal from the slow oscillator is routed from the count enable circuit 800 to lines 802,
Through step 804, the counts of up counters 780 and 782 are increased. At the same time, the same clock signal from the slow oscillator is provided to pulse modification circuit 744. The pulse train for driving each step motor from the pulse modification circuit is derived from these slow clock signals.

The outputs of up counters 780 and 782 step each motor in a predetermined direction, and the direction in which it steps is determined by the portion of the word stored in storage unit 778 representing the direction instruction. These directional portions are gated to the step motor drive logic by directional steering logic 736. The number of output pulses to each motor corresponds to the data and vice versa initially stored in the up counter. These up counters have a separate carry output on line 80 when the count has increased by a number equal to the number of steps specified by the command.
6,808. The carry output is sent to the driving/stitching circuit 750, and depending on the response of this circuit 750, it is sent to the pulse correction circuit 7 via lines 752 and 754.
44. As can be seen from the above, lines 752,
The - or other signal at 754 indicates that the correct number of input pulses have been accepted from the slow oscillator for a particular coordinate axis direction. When both carry outputs appear (of course they need not appear on the same clock cycle), sequence circuit 722 causes the enable signal on line 797 to be removed so that the last command read from memory is Indicates that the included information has been used.

The operation of the pulse modification circuit is as follows. During the homing cycle when there is an enable signal on line 745, pulses from the low speed oscillator are provided to the step motor in the coordinate axis(s) directed by the signals on lines 732, 734.

To utilize a single command during this operation, the periodic pulses from slow oscillator 768 when there is an enable signal on line 797 are gated according to data stored in up counters 780, 782 on line 746. , 748 to the step motor drive logic. If the number of steps in one coordinate axis direction is at least 4, then
A pulse train in that direction is obtained as follows.

After the enable signal appears on line 797, the first clock signal from this slow oscillator passes through a pulse modification circuit to the drive logic circuit. The second and third clock signals of the slow oscillator are blocked and a pulse modification circuit adds an initial delayed pulse that occurs approximately midway between the second and third clock signals. After the third clock signal passes through circuit 744, the clock signal from the slow oscillator remains essentially unchanged unless there is a change in the signal level on either line 752 or 754 corresponding to the associated coordinate axis direction. . line 752 or 7
The clock signal from the low speed oscillator after the change in signal level on the - side of 54 is prevented from forming part of the output pulse train in the direction of the coordinate axis. Two additional terminal delay interval pulses are then automatically added to the output pulse train by the pulse modification circuit. These pulses are added at predetermined time intervals following the last pulse in the train, the time interval being greater than the pulse interval from the slow oscillator. As a result, the drive pulses to the step motor are irregular, somewhat coarse at the beginning and end of the pulse train, and dense in the middle of the pulse train. Therefore, vibration is small, accurate positioning is possible, and machine cycle speed can be increased. If the number of steps in a given coordinate axis is equal to three, only one pulse of the pulse train is added, as detailed below.

The information from the storage element 458 is stored in the up counter 7.
80,782, if the number of steps specified for either coordinate axis direction is 1 or 2, this information is stored in the decoding or decoding circuit 798 and
9 is made available to the pulse correction circuit. The pulse modification circuit responds to this information from the decoding circuit to modify normal operation as described above. That is, if only two step pulses are required, only the initial delay pulse is added, and if only one pulse is required, neither the initial delay pulse nor the terminal delay pulse is added.

When the desired number of X steps and Y steps have been obtained, as indicated by the change in the carry signal from the up counter, the enable signal 797 is removed and after a short delay time the sequence circuit is activated. A memory cycle is initiated and an enable signal is provided on line 762 to read the next command from memory. The operation of control circuit 676 is then repeated until the program signal ends.

Storage element 778 stores command and direction information as described above. Each bit of the command is provided to a decoding circuit 830. Each output line of this decoding circuit has a total of 832
It is indicated by and corresponds to a particular command. The decode circuit decodes the command stored in unit 778 and produces an enable signal level on one output line 832 corresponding to the command. These output lines are connected to a sequence circuit which amplifies the signals and controls the operation of the sewing machine before passing them on line 867 to the quick switch.

The sequence circuit utilizes the signal on line 832 for two purposes. The first purpose is to distinguish between sewing and non-sewing commands in order to operate the quick device properly, and the second purpose is to cut the thread and move the workpiece holder to its position in response to the stop command. Executing a program completion sequence that includes sending a signal to thread cutting circuit 697 to return to the home position. To effectuate the return operation of the work holder, an "end of program" signal or command is present on one of lines 832 and an enable signal is generated on line 724 when a cut complete signal from cut circuit 697 is present. After this second homing cycle is finished, the central control logic circuit 6
In response to a signal provided from 76 via drive circuit 812 to solenoid actuated air valve 814, the clamp is lifted so that the workpiece can be removed.

The quick device utilizes signals on line 867 from sequence circuit 722 to sew at high or low speeds and to initiate needle raise and thread cutting in response to a stop command or to move without a sewing command.

As shown in FIG. 20, a program selection circuit 860 responsive to a program selection switch has an output on line 862 that indicates whether the PROM is selecting a program from bank A or bank B. Instruct.

Program selection circuit 860 and address counter 772
are interconnected by lines 864, 866 to control switching between memory banks as further discussed below.

The detailed electrical circuit of the control system is shown in Figures 21a to 21o.
Write in relation to figures. As shown in Figure 21m, the front panel 474 of the gabinet 454 (see Figure 18) contains the +5 volt and -12 volt power supplies for the sewing machine.
When the power switch is closed, these power supplies are connected to the control system as +5 volts and -12 volts. When the desired PROM is placed in the cabinet and the cabinet door is closed, the interlock switch is also closed and the 5 volts and -12 volts are interlocked and connected to each power control system as shown in Figure 21a. be done. Therefore, power will not energize the control system until the cabinet door and interlock switch are closed. The power supply switched to +5 volts and interlocked (hereinafter referred to as Vcc) is mainly used to energize the electrical circuits of the control system described below, and the power supply switched to -12 volts and interlocked is used for control. It is used for other circuits in the system and for the sewing machine. As shown, the +5 volt power supply and the -12 volt power supply are grounded.

As shown in Figure 21b, +5 volt Vcc power is supplied to the reed relay when the power is turned on with the interlock switch closed, or when the interlock switch is closed with the power on. This reed relay is of the type sold by Sigma Instruments, Inc. of Braintree, Massachusetts and designated part number 191TE1C6-55. When Vcc power is initially supplied to the circuit shown in Figure 21b, the reset N line is clamped to ground by the reed relay, and the energization of the reed relay by Vcc is performed by resistor H74 and capacitor C109. There is a delay of about 10 milliseconds. During this delay, the RESET N line or signal remains grounded or low. When the reed relay is energized after a 10ms delay,
Reset N is removed from ground, Vcc power supply, resistor H75
, about 31/2 to 4 depending on R76 and capacitor 108
Set to bolt. Thereafter, the Reset N signal remains high through operation of the control system unless it is reapplied to the reed relay by using a power supply or interlock switch, or the reset switch on the front panel of the cabinet is closed. . As shown in Figures 21b and 21m, the reset switch is normally open and can be closed by the operator in the event of an emergency condition or when it is desired to restart the entire control system sequence without turning off power. It will be done. As shown, the reset N signal is grounded while the momentary reset switch is closed by the operator.

While the RESET N signal is grounded or in a low state, RESET N is used to initialize various flip-flops and other components of the control system.

As seen in the various circuits described below, the reset N
Reset N is isolated from the flip-flop by various components when the signal returns to the high state by various diodes. An example of how the reset N signal initializes the control system will be described with reference to FIG. 21g. As shown in the figure, the program P end signal and reset N signal, which are in the low state at this time, are supplied as inputs to the NOR gate of flip-flop ff59A. Therefore, when the Reset N signal goes low, the flip-flop is reset so that the flip-flop output 10 is reset high and the Program P End signal is reset low.

As shown in FIG. 21c, the high speed oscillator H. S. O is energized by Vcc through a circuit 500 of various resistors and capacitors. High speed oscillator H. S. O is H. S. A square wave signal is generated as a clock signal at a rate of 8500 cycles per second. H. from this oscillator. S. The clock signal is applied to inverter 124A, which inverts the clock signal at its output 24A (10), as shown in FIGS. 21c and 22. Inverted H. S. Since the clock signal is differentiated by a differentiating circuit 501 consisting of a capacitor C86 and a grounded resistor R22, a positive pulse train is generated by the differentiating circuit 501 at the tip of the signal 124A (10) and applied to the input 13 of the inverter 124B. Supplied. The stop pulse generated by the differentiating circuit 501 is inverted by the inverter 124B and supplied to the input 12 of the NOR gate NO38A.

When the memory cycle enable N signal goes low, NO
Since the low pulse train of 38A (12) is inverted by gate NO 38A, a clock pulse signal is formed as shown in FIG. This clock pulse signal is an H. S. It consists of a narrow series of positive pulses that occur at the end of the clock signal. However, as shown in Figure 21d, the RESET N signal resets the MEMORY CYCLE ENABLE N signal to a high state during control system startup. This occurs because both inputs 5 and 6 of flip-flop ff34A are low while reset N is temporarily low, thus resetting the memory cycle enable N signal high. In this way, as shown in Figure 21c, after startup, the clock pulse signal is inhibited by the memory cycle enable signal to go low until the memory cycle enable signal is later set low as described below. maintained.

As further shown in FIG. 21c, H. S. The clock signal is applied to input 1 of a 10 count counter CT2 of known type. This counter has an internal divide-by-5 circuit and an internal divide-by-2 circuit, which are connected for use as follows. As shown in FIGS. 21c and 23, the counter output CT2 (12) is the H. S. It changes state on every fifth pulse of the clock signal, corresponding to its termination. In this way, counter CT2 acts as a frequency divider with a division of 10, so that a pulse train of 850 cycles/second is formed at the output of counter CT2. As shown in the figure, this frequency-divided pulse train is processed by two counting counters CT1
It is supplied to the NOR gate NO23A of the input 14 of No.3. The output of counter CT13 is every pulse from counter CT2 and H. S. It changes state corresponding to the end of every tenth pulse of the clock signal. Therefore, the counter CT connected to the inverter 124C
In order to form a pulse train of 425 cycles/sec at the output CT13 (12) of 13, counters CT2 and CT13 act as a frequency divider of 20.

The low-speed pulse train from counter CT13 is sent to inverter 1.
24C, and the inverted pulse train is supplied to input 11 of NOR gate NO23B. 21st
As shown in figure e, the flip-flop f of the NAND gate
Since input 2 of f45A is reset by the reset N signal during initialization, LS shift N is reset to high at this time. Therefore, as shown in FIG. 21c, when the LSFT N signal is high, this signal inhibits the output of NOR gate NO23B, so that the homing LS is disabled until the LS SHIFT N signal is quickly set low.
The Osc-P signal remains low.

The LS shift N signal is also supplied to inverter 124D,
Therefore, input 3 of NOR gate NO23A is low when the LS shift N signal is high. Therefore, now that LS shift N is high, the 850 cycles/second modified pulse train is inverted by NOR gate NO23A and enters input 5 of NOR gate NO23C. Gate NO23B
Since the homing LSOsc-P output of is low, the inverted pulse train from gate NO23A is again inverted by gate NO23C to produce a modified pulse train of 850 cycles/sec or LS in accordance with the output of counter CT2.
Formed at the output as the Osc-N signal.

Thereafter, when the LS shift N signal is set low, the NOR gate NO23B inverts the pulse train from the inverter 124C again and forms a 425 cycle/second slow pulse train as the LSOsc-P signal at the output in accordance with the output of the counter CT13. do. The LS Shift N signal is inverted by inverter 124D and the output of NOR gate NO23A is accordingly set low when LS Shift N is low. LSOsc for homing
Since the -P signal is supplied to input 6 of NOR gate NO23C, and since input 5 of gate NO23C is low, the homing LSOsc-P low-speed pulse train is inverted by NOR gate NO23C, and the inverted pulse train is applied to this gate. is formed as the LSOsc-N signal by the LSOsc-N signal. This signal corresponds to the inverted low-speed pulse train of the homing LSOsc-P when the LS shift N signal is low. Therefore, when LS shift N is high, the homing LSOsc-P signal is low and LSOsc
-N signal is a modified pulse train of 850 cycles/sec, and the homing LSO when LS shift N is low.
LSO with a slow pulse train with sc-P of 425 cycles/s
The sc-N signal is a 425 cycles/second inverted slow pulse train. As already mentioned, during initialization LS
The shift N signal is set high and therefore the homing LSOsc-P is set low and the LSOsc-N
The signal now corresponds to the modified pulse train from counter CT2.

For convenience, the remaining circuitry of FIG. 21c related to the generation of the needle disengagement or needle withdrawal pulse-P signal will be described next. As shown in Fig. 21m, the normal repair selection switch on the front panel is selected to the normal setting, and the signal from the main needle extraction sensor 414 of the unit 62 is output as the needle extraction sensor P signal by the contacts in this switch. and the signal from the auxiliary needle removal sensor 412 is provided by its switch contacts as the needle removal sensor P signal in the repair side setting of this switch. As shown in Figure 21c, the needle removal sensor P signal from the selected photosensor is applied to the base of transistor Ti.

For the optical sensor, the converter is located in the notch 4 of the commu data ring 354.
16, the needle removal sensor P signal is set high and the output of transistor Ti at pin 1 of the Schmitt trigger circuit ST37 is set low. Conversely, when the optical sensor is not aligned with the notch 416,
The needle removal sensor-P signal is low and the output of transistor Ti, which is supplied to the Schmitt trigger circuit, is high.

Therefore, when the notch first becomes aligned with the light sensor, the input of the Schmitt trigger circuit changes from a high to a low state. The Schmitt trigger circuit ST37 sharpens and inverts the signal of the input ST37(1) from the transistor, and the shaped output ST37(6) from the Schmitt trigger circuit is the input of a known monostable multivibrator or single shot circuit SS48A. Or supplied to pin 2.

The operation of single shot circuit SS48A and other single shot circuits used in this control system will be discussed below in connection with FIG. Each single shot circuit SS has two inputs, inputs a and b, which are used to trigger the single shot circuit. Input a corresponds to pin 9 or 1 of the single shot circuit SS, and input b corresponds to pin 10 or 2 of the single shot circuit. Single shot circuit SS has an internal inverter I and an AND gate A, the output of AND gate A triggers single shot circuit SS. Input a is supplied to inverter I, the output of inverter I is supplied as the negative input of AND gate A, and input b
is supplied as the other input of AND gate A. Since the high output of AND gate A triggers the single shot circuit SS, this single shot circuit is triggered by the appropriate state of the inputs as follows. Both the high state of input b and the low state of input a of the AND gate trigger the single shot circuit. If desired, both inputs a and b can be utilized by feeding different parts of the circuit to trigger the single shot circuit.

Alternatively, the single shot circuit SS can be triggered by a low signal on input a by connecting input b to the power supply Vcc so that the input of AND gate A from input b is always in the high state. Good too. Therefore, in this state, when input a changes from high to low, the input from inverter I to AND gate A changes from low to high, triggering the single shot circuit.

The output Q of the single shot circuit SS is normally low, and the output Q, hereinafter referred to as Q-bar, is normally high. When the single shot circuit SS is triggered by these inputs, its output Q goes immediately high and its output Q immediately goes low.

The trigger output of the single shot circuit is maintained in a shaped state for a period of time controlled by an RC circuit connected to the single shot circuit and by appropriate adjustment of the circuit's potentiometer. When the single shot circuit times out, outputs Q and Q-bar return to their normal low and high states, respectively.

Continuing with reference to Figure 21c, the output from Schmitt trigger circuit ST37 to single shot circuit SS48A triggers the single shot circuit when this signal goes high; This is because the other input of pin 1 of the circuit is grounded in accordance with the above. Therefore, the output Q of the triggered single shot circuit is set high for a period of time to negate any flickering that may occur in the signal from the optical sensor and Schmitt trigger circuit. As shown, the Q output of single shot circuit SS48A is supplied to input 4 of flip-flop ff12A and input 12 of NAND gate NA12B, both of which are high at this time, but return to a low state when the single shot circuit times out. Pulse signal LSOsc-N is inverted by inverter I1A, and the pulse train from inverter I1A thus inverted is connected to capacitor C7 and resistor R2.
5 by a differentiator circuit 502 which produces a relatively sharp series of pulses at the trailing edges of the pulses of the inverted pulse train from inverter I1A. Therefore, when input 12 of NAND gate NA128 is set high by single shot circuit SS48A, at least one pulse is inverted by gate NA128, and the low pulse causes flip-flop 12A to have its output and 3 high. Set it so that When flip-flop output ff12A(3) is set high, circuit 504 consisting of capacitor C114 and resistor R3 generates a positive pulse that is amplified and inverted twice by inverters I1B and I1C. Needle removal pulse - This is a positive pulse for the P signal. Therefore, the positive pulse of the needle extraction pulse -P is formed immediately after receiving the first pulse of the NAND gate NA12B after the optical sensor detects the notch of the commutator and the needle extraction sensor P signal goes high. be done. This signal is used to initiate movement of the clamp as described below.

When single shot circuit SS48A times out and its Q output returns low, flip-flop f
Since f12A is reset by the low state of input ff12A(4) and the high state of the output of NAND gate NA12B connected to this flip-flop, output 3 of flip-flop ff12A is reset to low.

The circuitry primarily associated with the pedal and clamp is shown in Figure 21f. During the initialization or start-up state of the control system, the reset N signal is used to reset a number of flip-flops in the circuit: input 4 of flip-flop ff92A, input 12 of flip-flop ff92B, input 5 of flip-flop ff90A, and input 12 of flip-flop ff78A. .

The circuit of FIG. 21f remains initialized until the first foot pedal of the sewing machine is activated.

As already mentioned, before the worker steps on the first pedal,
Pedal clamp no. As shown in the figure, the normally closed contact of switch 1 is connected to the ground side, so input 2 to the opto-isolator or opto-coupler OP94 is grounded through this switch. The optoisolator acts as a noise filter and has a photo-sensing transistor with a photo-sensing base. When radiation enters the base junction, a current flows through the collector of the transistor. Therefore,
Pedal clamp no. 1 switch is in the normally closed position before the first pedal of the sewing machine is depressed, or output 5 of obt isolator OP94 is in a low state with the clamp switch Off-N signal being low at this time.

The worker steps on the pedal and presses the pedal clamp No. 1 switch, the corresponding pedal clamp No. 1 switch opens the normally closed contact and opens the normally open contact and the isolator OP9.
Close input 2 of 3. Therefore, input 2 of isolator OP94 is removed from ground, and its output and clamp switch Off-N signal are set high. On the other hand, input 2 of Opto Isolator OP93
is grounded, and input 9 of flip-flop ff92B and output of obto-isolator OP93 are set low to set the flip-flop.

In this way, the output of flip-flop ff92B and the NOR gate NO90Bno input 9 of 8 are both set high, so the output of gate NO90B and the input of open collector drive circuit DC89A are set low.

Under this condition, the clamp No. from the drive circuit DC89A
．． The 1 Cmd output applies an appropriate amount of pressure to the air cylinder 274 to close the fabric clamp 240 as before. On the other hand, when the output of gate NO90B and the input of drive circuit DC89A are in a high state, clamp 240 is released. In this way, if the operator releases the first pedal before continuing, flip-flop ff92B will be activated by pedal clamp no. 1 switch so that the clamp 240 is lifted.

The operation of label clamp 300 is very similar to that described in connection with fabric clamp 240. Pedal clamp no.
．． 2 Before starting the switch, put the isolator OP7
The input 2 of 7 is grounded through the normally closed contact of this switch, and the flip-flop ff78 from the isolator
A's input 13 is therefore low. Pedal clamp no. 1 When the first pedal is further depressed to activate the switch, the pedal clamp No. 2 switch opens the contact connected to input 2 of isolator OP77, thus opening input 13 of flip-flop ff78A.
is set high. Furthermore, the pedal clamp No. activated in this way. 2 switch is optolisolator O
Since the contact connected to input 2 of P76 is closed, input 2 of this opto-isolator is grounded. In this way, since flip-flop ff78A is set by the low state of input 9, output 8 of flip-flop ff78A and NOR gate NO90 are set.
C's input 12 goes high. Therefore, the output of gate NO90C and the open collector circuit D
Since the corresponding input to C89B is set low, the clamp NO2Cmd signal from this drive circuit applies sufficient pressure to air cylinder 274 to close label clamp 300. Conversely, if the drive circuit D
When the C89B input is set high, the clamp N. The label clamp 300 is released by the 2Cmd output. Noah Gate NO90B,
All inputs on NO90C are set low by flip-flops ff92B, ff78A, and ff90A during initialization of the control system.

In this way, the clamp is lifted until the first foot pedal is depressed.

If only one movable clamp is used on the sewing machine, pedal clamp no. There is no need to use circuitry associated with two switches. In that case, the pedal number that can be included in the same pedal as the pedal for the pedal go switch. Only one switch is used, but pedal no. There is no need to change the circuit as the circuit connected to the 2 switch remains idle. Therefore, the control system is used in conjunction with one or two clamps as appropriate.

After activating both pedal clamp switches, the operator
The pedal is pressed to request the start of the sewing operation, and the pedal go switch activated in this way activates the opto-isolator OP.
The normally open contact connected to the 96o input 2 is closed and this contact is grounded via a switch. As a result, output 5 of optoisolator OP96 and corresponding input 1 of flip-flop ff92A are set low.

As mentioned above, the clamp switch Off-N signal is the pedal clamp number. 1 switch is activated, and both inputs 4 and 5 of the NAND gate of flip-flop ff92A become high, so the NOR gate N
A low signal appears on input 11 of O82A. At this point, the operator releases the first pedal after activating the pedal go switch and presses the pedal clamp No. It can be seen that flip-flop ff92A is not reset until the 1 switch is in the normal state and the clamp switch Off-N signal is in the low state. This condition ensures that the operator must release the first pedal before the next sewing operation.

Until the position of clamps 240, 300 is fully locked, the clamp sense signal from the normally open contact of clamp sense switch 308 is removed from ground and connected to opto-isolator OP.
The output of 95 is high at this time. When both clamps are in the proper position, the clamp detection switch grounds its normally open contact and the clamp detection signal goes low, producing a low signal at output 5 of opto-isolator OP95 and input 12 of NOR gate NO82A. Therefore, when both the clamp detection switch and the pedal go switch are activated, output 13 of NOR gate NO82A goes high, and differentiating circuit 506 consisting of capacitor C110 and resistor R104 outputs inverter I91.
A and input 1 of AND gate A66A to generate a positive pulse as an input. Inverter I91A inverts this positive pulse to a low pulse as a condogo P signal.

During initialization, output 4 of flip-flop ff90A and the corresponding crunch mode OP signal are set high by the reset N signal. Therefore, a high state is established at input 2 of AND gate A56A by the clamp mode OP signal through delay circuit 508.

Referring to FIG. 21d, the initialization of flip-flop ff21A by reset N resets its output 8 and the home position P signal to a low state. Therefore, a low state is established at input 5 of NOR gate NO82B during initialization, as shown in FIG. 21f.

As shown, a plurality of temperature sensors or switches S1, S2, S3 and S4 on the motor driven heat sink are connected to a power supply V
Connected in series to cc. Therefore, the power supply Vcc is connected to the inverter I9 via the switches S1 to S4 and the resistor R100.
Connected to 1B. However, since the normal state of the input of inverter I91B is high, the Noah gate is NO.
At 82B, input 6 goes low as an overtemperature P signal. Sensors S1-S4 (Figure 21f) are used to monitor the temperature of the power transistors supplying power to the motor coils and protect the drive circuitry in the event of an overtemperature condition;
If an overtemperature condition exists in any of these sensors, the sensor contacts open, thus pulling the power supply Vcc across resistor R1.
Since it is cut off from 00, the input of inverter I91B becomes low and the overtemperature P signal becomes high. When the input of the drive circuit DC88A is in a high state, the 21st m
As shown in the figure, the overtemperature LED signal that lights up the temperature LED lamp on the front panel goes high. This overtemperature P signal is used to protect the control system as described below.

Assuming that the temperature sensor indicates a satisfactory temperature condition, both inputs 5 and 6 of NOR gate NO82B will be low and the NOR gate NO82B will pass through delay circuit 510.
The output signal from is input 1 of AND gate A66A.
It is high along with 3. Therefore, both inputs 2 and 13 of AND gate A66A are both high, and the positive pulse of input 1 of the AND gate enters input 1 of NAND gate NA78B through this gate. NTB
The mode OP signal indicates the state of the needle thread breakage sensor 312 and is set low in the event of a thread breakage, causing the NAND gate N
Hold the A78B output high. Conversely, if the thread is not broken, the NT8 mode OP signal is high indicating proper thread condition and the positive pulse at input 1 of NAND gate NA78B is inverted through this gate. Therefore, a low pulse is formed as the start pulse N signal, and this low pulse is inverted by the inverter I91C into a positive pulse as the start pulse P signal.

A positive or high pulse appearing at input 6 of flip-flop ff90A sets the flip-flop such that output 4 is set low and output 1 is set high. Therefore, the clamp mode OP signal is set to a low state, and after a delay by delay circuit 508, this signal establishes a low state at input 2 of AND gate A66A, which then inhibits this gate. Since the clamp mode 1P signal is set high, the outputs of NOR gates NO90B and NO90C are held low, and the fabric clamp and label clamp are maintained in the locked position by the current setting of flip-flop ff90A.

The overtemperature P signal is applied to input 5 of AND gate A78C, and the clamp mode OP signal is applied to input 4 of the same gate. As above, clamp mode O
The P signal is set low by flip-flop ff90A and remains low until the end of last cut N signal later goes low. Therefore, the input of drive stage Q2 is low during the setting of flip-flop ff90A. Drive stage Q2 handles the busbar of the drive circuit which disables the motor's pre-drive circuit and final drive circuit. Switch S1~S
When an overtemperature condition is detected by 4, the overtemperature P signal is set high as described above. When the input of drive stage Q2 is set high, the Crd-N drive signal is permanently grounded, disabling the motor's pre-drive and final drive circuits. However, it is desired to finish the sewing operation before disabling the motor, and the clamp mode OP signal is switched to the flip-flop f when the end of the final cut N signal is accepted.
It will not be set high until f90A is reset. Thus, when the clamp mode OP signal is set high by flip-flop ff90A, the corresponding input of output drive stage Q2 of AND gate A78C goes high to drive the motor's pre-drive and final drive circuits. to prevent damage to the motor in overtemperature conditions. At the same time, Noah Gate NO90b,
Since all inputs of NO90C are low, and therefore inputs of electrical circuits DC89A and DC89B are high, when the operator removes his foot from the first pedal, both clamps are released by the change in state of flip-flop ff90A.

As shown in Figure 21g, reset N during initialization.
The signal resets flip-flop ff39A, so the flip-flop's output 10 is reset high and the program mode 1P exit signal is reset low. Establishing a high state at the input 10 of the NAND gate NA54A by passing the high signal at the output 10 of the flip-flop ff39A through the delay circuit 512;
As mentioned above, the start pulse N signal is initially high, and therefore the address clear P signal is initially low after initialization. However, after that, the low pulse of the start pulse N signal causes a positive or high pulse to be formed at the output of the gate NA54A as the address clear P signal. Of course, the start pulse N signal instantaneously returns to the high state.

The start pulse P signal appearing on flip-flop ff39A is a positive pulse, and does not change the state of this flip-flop at this time. Therefore, a high pulse is formed as the address clear P signal, and then the NAND gate NA
Both inputs of 54A go high and the address clear P signal is held low.

As shown in FIG. 21a, the positive pulse of the address clear P signal resets flip-flop ff130A so that the extended terminal is reset to a high state. Also,
To clear the address registers or counters AR1, AR2 to zero, the address clear P signal is inverted by inverter I131A so that a low pulse appears at the clear inputs of these counters. As mentioned above, the address clear P signal then goes low.

The start pulse N signal is also used to start the homing operation. As shown in FIG. 21h, since the program mode 1P end signal is set low, the final cut N end signal and input 4 of NAND gate NA32A are high. At first, start pulse N
The signals are high, so the homing set P signal from gate NA32A is initially low, but the homing set N inverse signal is initially high. However, after that, the low pulse of the start pulse N signal forms a positive or high pulse as the homing set P signal, and a low pulse is formed as the homing set N signal via the inverter I19A. When the start pulse N signal returns to high, the homing set P signal and set N signal return to the low and high states, respectively.

As shown in FIG. 21c, the homing set N low pulse triggers the single shot circuit SS22A, which times out after a delay longer than the time required to complete the homing mode unless a failure occurs. When the single shot circuit times out, its Q bar output goes from low to high and differentiator circuit 514 generates a positive pulse that is input to NOR gate NO9A. A low pulse is formed at the output of this gate as the homing clear N signal, which is used to initialize the homing circuit. Therefore, if an accident occurs during the homing mode and the mode is not completed, the homing clear N signal will stop the homing mode to prevent possible damage to the sewing machine or control system.

The low pulse homing set N signal is used to initiate the basic homing mode as follows. Second
As shown in FIG. 1d, the homing set N signal sets flip-flop ff21A, causing its output base home P to be high and base home N to be low. The basic home N signal is inverted by inverter I19B, and when this inverted signal goes from low to high due to flip-flop ff21A being set by the homing set N signal, differentiator circuit 516 generates a positive pulse. This positive pulse is converted into a Pri home direction set N (Pri home DirSet-) by an inverter I19A.
N) Inverted as the low pulse of the signal.

As shown in FIG. 21e, the low pulse signal of plyhome direction set N
100B input, so these gates connect D type flip-flops ff99A and ff99.
A high pulse signal is output to B respectively. These flip-flops ff99A and ff99B are used to determine the X and Y coordinate directions, as will be described in detail below.

As shown in FIG. 21f, the positive signal of the basic home P is supplied to input 5 of NOR gate NO82B, so that a delayed low state is obtained at input 13 of AND gate A66A. As mentioned above, AND gate A66A
When any of the inputs goes low, the Start Pulse N signal returns to High and the Start Pulse P signal returns to Low. However, a delay circuit is connected to each high input of AND gate A66A. The attenuation of the positive pulse at input 1 of gate A66A is long enough, and the attenuation of circuits 508 and 510 is long enough that gate A66A
input does not immediately return low, and the start pulse N signal remains low for a selected period of time, even though it is referred to as a pulse.

Since this selected time is sufficiently long, the start pulse P
The homing set P formed in response to the low pulse of
The signal remains high while the basic home N signal is set low by flip-flop ff21A of FIG. 21d. Therefore, the homing set P signal is high and the basic home N signal is low for some time between when the start pulse N returns to the high state and when the homing set P returns to the low state.

Therefore, as shown in FIG. 21g, the homing set P input to the NOR gate NO43A during this time is
When the signal is high, the low signal simultaneously input to the OR gate causes the input 9 of the NAND gate NA55A to
is forced into a low state. In this way, since the input 11 of NOR gate NO44A is high, it becomes a low state pulse as the start run N signal. At this time, the auxiliary home running P signal is low, and therefore, when the homing set P signal returns to the low state, input 9 of gate O43B becomes high, input 9 of gate NA55A becomes high, and input 11 of gate NO44A becomes high.
becomes low, and the start run N signal returns to the high state. It is easily determined that the remaining inputs of gate NA55A are high and the other inputs of gate NO44A are low at this time.

As shown in Figure 21d, during initialization the reset N
The signals are X and Y flip-flop ff21B, respectively.
ff32B is reset, the X travel N signal and the Y travel N signal are in the high state, and the X travel P signal and the Y travel P signal are in the low state. When a low pulse is formed as the start run N signal, this pulse is repeated by inverter I19C, so that a high pulse appears at input 2 of NOR gate NO20A and input 5 of NOR gate NO20B. At this time, the X travel set P signal and the Y travel set P signal are low, so gates NO20A and NO20
Low pulses are output from B to flip-flops ff21B and ff32B to set these flip-flops, so that the X running N signal and the Y running N signal are low, and the X running P signal and the Y running P signal are high.

As shown in FIG. 21i, during initialization, the reset N low signal is inverted by inverter I24F,
The resulting high signal is applied to the X and Y pulse suppression flip-flops ff3A, ff3B, ff4A, ff4B.
, ff15A, ff15B, ff27A and ff27B
is fed to each Noah gate input. Each of the above flip-flops is therefore reset by a positive signal so that the various corresponding signal outputs, X decode 4 pulses N, Yc pulse inhibit N, Yb pulse inhibit N
, Xa pulse inhibit N, and Ya pulse inhibit N are set high.

At this time, the signals from the differentiating circuits 518 and 520 are transferred to the inverters 150B and 150D and the NOR gates NO14A and NO1.
4B, NO14C, NO14D, NO26A, NO26
Flip-flop ff3A, ff3B, ff4A, ff4B, ff15A via B, NO26C, NO26D
, ff15B, ff27A, and ff27B determine that the other inputs of the X and Y suppression flip-flops are low.

As previously discussed in connection with FIGS. 21e and 21c, the LS shift N signal is initialized to a high state and the shaped wave signal LSOs-N is at a relatively fast rate of 850 cycles/second. As shown in Figure 21j, the LSO
s-N is inverted by inverter I67A, and this inverted signal is differentiated by differentiation circuit 522. Therefore,
The circuit 522 generates a series of pulses using the inverted signal from the inverter I67A at the tip of the rectangular pulse. The high pulses thus generated are inverted by inverter I67B to form a low pulse train. Since the X running N signal and the Y running N signal are set low by the X and Y flip-flops, the low pulse train from inverter I67B is output to NOR gates NO80A and NO104A.
is inverted by the gate into a narrow positive pulse train consisting of the X count pulse P signal and the Y count pulse signal.

Therefore, the count pulse P signal of X and Y is the square wave signal L
Synchronize with the end of SOs-N. It is a series of narrow positive pulses at a relatively fast rate of 850 cycles/sec.

The formation of the X combo N and Y combo N signals used to drive the X and Y step motors will be discussed in detail below when the operation of the sewing machine under program control is described; The generation of the signal will only be briefly mentioned here. As shown in Figure 21k, the pulse train of X count pulses P is fed to pin 2 of the single shot circuit, SS28A, and is also fed as the negative input of NAND gate NA5A, and the pulse train of negative Y counts P to the single shot circuit, SS28A. It is supplied to pin 10 of SS40A and the negative input of NAND gate NA29A.

The X running P signal is inverted twice by inverters I17A and I17B. When the X running P signal goes from low to high, the corresponding signal output from inverter I17B is differentiated by differentiating circuit 524 to generate a positive pulse and set flip-flop ff16A to have its output 1 low. Therefore, single shot circuit SS28A
Pin 1 of is set low by a flip-flop to enable a single shot circuit. Single shot circuit SS28A is then triggered by the first positive pulse of the X count pulse P signal on its pin 2, and its Q output immediately goes high. The Q bar output of single shot circuit SS28B remains high until single shot circuit SS28A times out and the same positive pulse of the signal of X count pulse P passes through NAND gate NA5A and is inverted by this gate to output NAND gate NA31A. A low pulse is formed at the inft 10 of the instrument. This low pulse at the input of gate NA31A is the X pulse N of the X count pulse P signal.
o. It is called 1.

As mentioned earlier, both the Xa pulse inhibit N and LS shift N pulses are initialized to a high state, and the input from NAND gate NA5B to pin 1 of single shot circuit SS6A is low and this single shot circuit enable. Single shot circuit SS6A is therefore triggered at pin 2 by this circuit. In this way, the Q bar output of single shot circuit SS6A is set low, and when the single shot circuit times out, its Q bar output is set low.
The bar output goes from low to high, and the differentiator circuit 52
6 generates a positive pulse. Single shot circuit SS6
The delay time of A and the corresponding time of generation of the pulse by circuit 526 are the pulse no. of X count pulse P. It is selected at a predetermined time after 1. The pulse generated by differentiator circuit 526 is inverted by inverter I56A to form a low pulse at input 11 of NAND gate NA31A, which is referred to as the Xa pulse.

The single shot circuit SS2 that triggered this single shot circuit before the single shot circuit SS6A timed out.
8A times out so that its Q output low signal triggers the single shot circuit SS23 at pin 9. Single shot circuit S triggered in this way
The Q output of single shot circuit SS28B is set high and delayed slightly by delay circuit 228, but the Q output of single shot circuit SS28B is set high and delayed slightly by delay circuit 228.
f16A, this flip-flop forms a high signal at its output 1 and outputs the single shot circuit SS.
Pin 1 of 28A is now inhibited from further triggering of this single shot circuit by the X count pulse P signal. - side, triggered single shot circuit SS2
The Q bar output of 0B goes low and inhibits pulses from the X count pulse P signal from passing through NAND gate NA5A until the timeout of single shot circuit SS28B. A delay circuit connected to the single shot circuit SS28B ensures that pulse Xa is generated during this period when the second and third pulses of the X count pulse P signal are inhibited.

Then, when single shot circuit SS28B times out and its Q bar output goes high, subsequent pulses from X count pulse P are applied to NAND gate NA5.
A is supplied as a low pulse to the input 10 of the NAND gate NA31A, which is inverted by this gate. Therefore, inputs 10,1 of gate NA31A
The pulse formed at 1 is the X count pulse of the P signal.
Pulse No. 1, the pulse Xa that occurs between the second and third prohibited pulses, and the fourth pulse and subsequent pulses.

The basic home P high signal is inverted by inverter I7A, and its output passes through delay circuit 530, which is again inverted by inverter I7B to form the homing mode OP high signal, which is a single shot signal. Supplied to pin 9 of circuit SS6B. The homing mode OP high signal thus inhibits this single shot circuit and its Q bar output remains high as long as the basic home P signal is high. Therefore, the signal from differentiator circuit 532 to input 13 of NAND gate NA5C remains low, and the output of gate NA5C, which is supplied to input 9 of NAND gate NA31A, remains high during this time, inhibiting the formation of the Xb pulse.

As mentioned before, input 10 of gate NA31A
. Each positive pulse on input 2 of this single shot circuit triggers this single shot circuit. A single-shot circuit SS68A regenerates each positive pulse and forms a wide corresponding train of regenerated low pulses at its Q-bar output, which is used to direct the motion of the X step motor - a train of regenerated low pulses. An X combo N signal is formed.

Since the basic home N signal was set low, the output of AND gate A5D appearing at pin 10 of single shot circuit SS68B is low, thus inhibiting this single shot circuit. Therefore, the signal from differentiator circuit 534 to input 3 of OR gate O82C is low while the basic HOME N signal is low, thus preventing the formation of an Xc pulse at the pin of single shot circuit SS68A.

In this way, the low pulse train X combo N for the X step motor during the basic homing mode is formed. This signal is the regeneration X pulse number of the X count pulse P signal.
1 and its fourth and subsequent pulses. Y
The Y combo N signals for controlling the step motor are very similar in formation, so we will only briefly describe them.

As mentioned above, the Y count pulse P signal is supplied to pin 10 of the single shot circuit SS40A and the NAND gate NA29A, and the high signal of the Y run P is supplied to the inverter I17C.
and I17D, and the inverter I17
The signal change from D is differentiated by a differentiator circuit 536 to generate a pulse, which sets flip-flop ff16B so that its output 13 goes low, and a single shot circuit receives the first pulse of the Y count pulse P. S.S.
Enable pin 9 of 40A. The Q output of triggered single shot circuit SS40A triggers single shot circuit SS30A for the purpose of generating a YA pulse.

The pulse of the Y count pulse P signal that triggers the single shot circuit SS40A passes through the NAND gate NA29A and is inverted to the input 5 of the NAND gate NA31B.
Pulse No. It appears as a low pulse called 1.

As mentioned above in connection with the X circuit section, single shot circuit SS40B is triggered on pin 1 when SS40A times out. The Q output of the single shot circuit SS40B triggered in this way is sent to the delay circuit 5.
3B, resets flip-flop ff16B and inhibits pin 9 of single shot circuit SS40A.

The Q-bar output of triggered single-shot circuit SS40B inhibits NAND gate NA29A during the second and third pulses of the Y-count pulse signal, preventing pulses from passing through this gate at this time, but not during the fourth and third pulses. It allows subsequent pulses to pass through this gate and inverts the pulses when the single shot circuit SS40B times out as described above.

When the triggered single shot circuit SS30A times out and its Q bar output goes high,
Differentiator circuit 540 generates a YES pulse, and this high pulse is inverted by inverter I56B and appears at input 4 of NAND gate NA21B as a low pulse, referred to as the YA pulse. Therefore, the low pulse formed at inputs 4 and 5 of gate NA31B is inverted and passes through this gate to input 9 of OR gate O82D.

The positive pulse passes through this OR gate to the single shot circuit SS.
67A, where the pulses are formed as a train of low pulses corresponding to the Q bar output of this single shot circuit as a regenerated Y combo N signal for controlling the Y step motor.

The single shot circuit SS30A that forms the Ya pulse is enabled by the high state of the LS shift signal supplied to the input of the NAND gate NA29B and the Ya pulse inhibit N signal, so a low signal is applied to pin 9 of the single shot circuit SS30A. Form. However, the formation of Yb and Yc pulses is prohibited at this time as mentioned earlier. Basic home N
Since the low signal is supplied to input 10 of AND gate A29C, a low input is generated at pin 2 of single shot circuit SS69B. In response, the Q-bar output of single-shot circuit SS69B remains high;
Differentiator circuit 542 is prevented from forming a YC pulse that would enter the pin of single shot circuit SS69SA through OR gate O82D.

As previously stated, the homing mode OP signal is set high by the basic home P high signal. The homing mode OP signal is applied to pin 1 of single shot circuit SS30B to inhibit this single shot circuit. Therefore, the Q bar output of single shot circuit SS30B remains high, and differentiator circuit 542 outputs NAND gate NA31.
The formation of a pulse for NAND gate NA29D that would pass as a low Yb pulse to B input 3 is prevented.

Therefore, X combo N and Y combo N during homing mode
The pulse trains for the signals are based primarily on the X count pulse P and Y count pulse P signals, respectively, except for the modification of the pulse train by the Xa and Ya pulses. Pulse train X combo N and Y combo N are as follows:
The shaft and step motor are each fed separately.

As shown in Figure 21c, the X-homing sensor signal from the homing sensor on the X-axis edge is provided to a Schmidt trigger circuit ST98A. This Schmitt trigger circuit sharpens the edges of the sensor signal, inverts the signal, and then transfers the signal to a D-type flip-flop.
appears at the D input of and the input 2 of exclusive-OR gate EO101A. Flip-flop ff99A operates as follows. CLK of this flip-flop
When the input goes high, its Q output is C
Continuously set equal to the signal on its D input while the LK input remains high. When the CLK4 input returns low, further changes in the Q output are prevented until the CLK input returns high again.

Therefore, when the CLK input goes low, the flip-flop's Q output is set equal to the final value of its D input when the CLK input goes low.

Conversely, the Q-bar output of a flip-flop is CLK.
Set equal to the last inverted D input value when input goes low.

As mentioned earlier, during initialization of the basic homing mode, the PLY HOME DIRECTION SET N signal is formed as a low pulse, resulting in flip-flop ff99A.
A positive pulse is formed at the CLK input of . Therefore,
The PLY HOME DIRECTION SET N signal returns to a high state and the flip-flop Q output is set to the final value of the D input indicating the current position in the X direction as sensed by the X homing sensor. Therefore, for example, when receiving a low pulse of ply home direction set N,
If the homing sensor signal is low, the Schmitt trigger circuit ST98A to flip-flop ff99A
The inverting output applied to the D input of the flip-flop is high, so the flip-flop's Q output is set high and the Q bar output is set low.

The output between flip-flop Q and Q-bar is CL
It remains in this state until another positive pulse is accepted at the K input.

X from Q output of flip-flop ff99A
The home direction P signal is used to identify the direction in which the X step motor must be driven to move the workpiece holder to the home position in the X direction. The X home/direction P signal is input 4 of the AND gate A133B.
and the basic home P signal is fed to input 3 of this gate. Since the basic home P signal is high during this time, the X home/direction P signal is the NOAH gate NO134C.
is guided by input 6. The low signal of base home N is provided to input 2 of AND gate A 133A such that input 5 of NOR gate NO 134C is also low. Therefore, the signal at input 6 of NOR gate NO134C is inverted as an X direction signal. If the X Home Direction P signal is high, the X Direction signal is low;
Conversely, if the X Home Direction P signal is low, the X Direction signal is high. The polarity of the X direction signal dictates the signal from the X homing sensor when the basic homing mode is initialized, thus driving the X step motor along the X axis to the home position during this basic homing mode. It is clear that an X step motor can be used to control the proper direction.

As shown, the Q bar output of flip-flop ff99A is provided to input 1 of exclusive-or gate EO101A. As previously mentioned, the output from the Schmitt trigger circuit ST98A is provided to input 2 of the game. When the outputs of Q and Q-bar are set by the flip-flop CLK input, the inverted Q-bar output of this flip-flop is the inverse of input 2 of exclusive-or gate EO 101A. Therefore, once these outputs of the flip-flop are set, the exclusive-or gate EO
The two inputs of 101A are each set to opposite polarity. This exclusive or gate EO101A is
As long as the two inputs are of opposite polarity, it will have a high output, but if the two inputs are of the same polarity, the output of this gate will be low.

Therefore, the input of the exclusive-OR gate reverses polarity when the output of the Schmitt trigger circuit ST98A crosses the X-axis sensed by the X-homing sensor when the clamp is being driven toward the home position. However, upon reversal of the polarity described above, both inputs of the exclusive-OR gate become equivalent. At this point, the exclusive-or gate EO101Ano output goes low. Basic home N signal is Noah Gate NO71A
Since one input from the exclusive OR gate is low and the other input from the exclusive OR gate is low at this time, the output of NOR gate NO 71A goes from low to high and the differentiator circuit 544 generates a positive pulse.

As stated earlier, during initialization, the LS shift N signal of flip-flop ff45A is set high by the reset N signal. Output 6 of flip-flop ff45A is low since both its inputs 4 and 5 are high.

The high signal at input 5 of this flip-flop is caused by the low signal from differentiator circuit 546 which is inverted by inverter I46A. flip flop ff45
Since the low output from inverter I46A is inverted to a high state by inverter I46B, NOR gate NO71B input 5 and NAND gate NA60A input 2 are both high. The high signal at input 5 of NOR gate NO71B prevents flip-flop ff71C from being set by a positive pulse from differentiator circuit 544. However, this differentiating circuit 544 is connected to input 1 of NAND gate NA60A, and input 2 of this NAND gate is connected to input 1 of NAND gate NA60A.
is high at this time, resulting in a low pulse appearing at input 10 of the NAND gate NA73A, so the positive pulse is inverted by the NAND gate NA60A. - On the other hand, NAND gate NA73A inverts this low pulse and presents a positive pulse at input 1 of AND gate A132A. The high signal of basic home P is supplied to input 2 of AND gate A132A, so NOR gate NO134A
A positive pulse appears on input 1 of . The low signal of elementary home N is applied to input 4 of AND gate A 132B, so the other input 2 of NOR gate NO 134A is low. Therefore, NOR gate 134A inverts its input 1 positive pulse to form a low pulse as the X-stop-N signal.

As shown in FIG. 21d, the X-stop N signal is applied to the X-running flip-flop ff21B, and the low pulse of the X-stop N causes this flip-flop to output its output signal
Reset so that travel N is high and X travel P is low. As shown in FIG. 21j, the output of the X running N high signal NOR gate NO80A is set low. Therefore, the X-count pulse P signal used to form the pulse train as the X-combo N signal for the purpose of controlling the X-axis step motor goes low, stopping the X-axis step motor. The motor is driven in the basic home mode at a relatively high speed of 850 cycles/second so that the workholder moves quickly past the home position of the basic home mode before it stops.

The operation of the control system for controlling the workpiece holder in the Y direction is very similar to the connection in the X direction. Therefore, as shown in FIG. 21e, from the Y direction, the flip-flop ff from the Schmitt trigger circuit ST98 is
Generated on the D input to 98B. The low pulse of the fly home direction set N is passed through the NAND gate NA100B as a high pulse to the flip-flop ff99.
The flip-flop f is supplied to the CLK input of B and during initialization depending on the last state of the D input.
Establish the Q and Q-bar outputs of f99B. The Q output of this flip-flop, called Y-home direction P, is fed to the input 8 of the AND gate A133D, and since the input 7 of this gate is connected to the basic home P of the high signal, the NOR gate NO 134D is fed as the Y-direction signal. The signal from the Y home direction is inverted. The other AND gate A133C is connected to the basic home N of the low signal and therefore the NOR gate NO13
4D input 7 is also low at this time. The Y-direction signal controls the direction in which the Y-axis step motor moves the workpiece holder in the Y-direction, in the same way as described above in connection with the X-direction signal used to control the direction of the X-axis step motor. used for.

If the output from the Schmitt trigger circuit ST98B changes state when the homing sensor detects a crossing along the X axis of the workpiece holder, the inputs of the exclusive OR gate EO101B will be the same and the NOR gate N
A low state is established at input 3 of O86A. Since the basic home N signal is low, the output of the NAND gate NO86A goes from low to high, and the differential circuit 548 generates a positive pulse at the input 2 of the NAND gate NA37B. Since input 1 of NAND gate NA73B connected to the output of inverter I46B is high, a low pulse is formed at input 4 of NAND gate NA73C.

This gate inverts the pulse and AND gate A132D
A positive pulse is formed at input 8 of . Since the other input 7 of this gate is connected to the basic home P of the high signal, the positive pulse is inverted by the NOR gate NO 134B as a low pulse for the Y Stop N signal. Input 6 of AND gate A 132C is connected to the base N of the low signal, and the other input 3 of NOR gate NO 134B is low at this time.

As shown in FIG. 21d, the Y-stop-N low pulse is applied to the Y-run flip-flop ff32B to reset the flip-flop so that its output signal Y-run P is low and Y-run N is high. As shown in FIG. 21j, the Y run N high signal supplied to NOR gate NO 104A stops the Y-axis step motor, thereby forming a low state in the Y count pulse P signal.

Of course, the Y-axis step motor is
Based on the respective crossing times in the axis and Y axis
The Y-axis step motor must be stopped at the same time as before or after the axis step motor.

When a direction change is instructed by the X and Y homing sensor signals and the flip-flops for X travel and Y travel are reset and the movement of the clamp in the X and Y directions is interrupted,
As shown in Figure 21d, both inputs of NOR gate NO20C are reset low. When the second input of gate NO20C goes low, the output of this gate goes high and differentiator circuit 550 generates a positive pulse, which is inverted to a low pulse by inverter I19D, and this low pulse is output to the NOR gate. NO
Appears on input 12 of 20D.

Since the basic home N signal is low, gate NO20D inverts the pulse at its output as a positive pulse for the mode pulse P signal, which is used to select the auxiliary and sub-auxiliary homing modes.

As shown in FIG. 21c, the signal of mode pulse P is connected to input 12 of NAND gate NA73D and NAND gate N
It is supplied to input 9 of A45B. As shown, the output of inverter I46B, which is high, is connected to input 13 of NAND gate Na73D, and the output of inverter I46C, which is low, is connected to input 10 of NAND gate NA45B.

Since input 10 of gate NA45B is low at this time, the output of this gate connected to pin 9 of single shot circuit SS33A is high, and this single shot circuit is not triggered at this time.

However, input 15 of NAND gate NA73D is high, so the high pulse for the mode pulse P signal is inverted through this gate. The corresponding low pulse from the output of gate 73D is connected to single shot circuit SS33.
appears on pin 1 of B and triggers this single shot circuit. This single shot circuit times out and its Q.
When the bar output goes high, a positive pulse is generated by the differentiator circuit 546. This pulse is inverter I4
6A as a low pulse, setting flip-flop ff45A such that its output signal LS shift N is low and output 6 is high.

The high signal at output 6 of this flip-flop is delayed by delay circuit 552 and then output to inverter I4.
It is toggled low by 6B. Inverter I46
The low output of B is inverted by inverter I46C, and since the output from this inverter is high, differentiator circuit 554 generates a positive pulse, which triggers single shot circuit SS59A at pin 2.

The positive pulse generated by differentiator circuit 554 is inverted by inverter I46D, and the corresponding low pulse from this inverter appears as the auxiliary set pulse N signal at the inputs of NAND gates NA100A and NA100B. The corresponding positive pulses formed at the outputs of these NAND gates are the flip-flops ff99A, f
Start f99B with its CLK input to obtain new X and Y position data for the Q and Q bar outputs of these flip-flops as described above.

An RC circuit connected to single shot circuit SS59A is configured to cause this triggered single shot circuit to undergo a 10 millisecond delay before timing out. This delay circuit allows positioning of the X and Y step motors and ensures that position information is clocked into flip-flops ff99A and ff98B. When single shot circuit SS59A times out, its Q bar output goes high and differentiator circuit 556 generates a positive pulse as the auxiliary home run P signal. This signal initiates the auxiliary home mode during which the X and Y axes step motors follow the intersections that occur along the X and Y axes of the workpiece holder during the basic home mode. Therefore, since the Q outputs of flip-flops ff99A and ff99B have different polarities from those in the fundamental mode, when they are driven in the fundamental mode, they are driven in opposite directions.

As shown in FIG. 21g, when the auxiliary home run P signal is supplied to the NOR gate NO43A, a low pulse is formed at the input 9 of the OR gate O43B. Basic home N
Since the signal is low, a low pulse appears at input 9 of NAND gate NA55A, and the NOR gate NO44A
A positive pulse is formed at the input 9 of the motor, and a low pulse is formed as the start running N signal.

As shown in FIG. 21d, the start running N low pulse is applied to the running flip-flops ff21B and ff3 of X and Y.
2B and travel N of X and Y as described above.
The output of low X and Y running P becomes high. As shown in Figure 21c, the LS shift N signal is low at this time, so the LSOsc-N signal is a relatively slow rate square wave signal of 425 cycles/second. As described above,
The slow clock signal is used during the auxiliary and sub-assist modes to ultimately position the work holder at its home position.

As shown in Figure 21j, the X run N and Y run N signals are set low, except that the pulse train formed at this time is at a relatively slow rate of 425 cycles or pulses per second. As mentioned above, the pulse train of X and Y count pulses P is again formed from the LSOsc-N signal. As stated earlier in connection with Figure 21k, X and Y
A regenerated low pulse train of the X and Y combo N for the step motor control is again formed from the signals of the X and Y count pulses P. However, since the LS Shift N signal is low at this time, the outputs from NAND gates NA5B and NA29B to single shot circuits SS6A and SS30A are high, thus inhibiting double and single shot circuits. Therefore, during the homing mode of the auxiliary and sub-auxiliary, Xa and Ya
pulses are not formed and are inhibited by the LS shift N signal.

As before, the X and Y running P signals trigger these single shot circuits, which trigger the second and third pulses of the X and Y count pulses P signal at NAND gates NA5A and NA29A, respectively. prohibited. Therefore, by the single shot circuits SS68A and SS69A,
The pulse train that is regenerated and formed as a combo N signal of is prohibited. The Xb, Xc, Yb, Yc pulses are inhibited during the auxiliary homing mode in the same way as they are achieved during the basic home mode.

Referring to FIG. 21e, when the direction indication of the Schmitt trigger circuit ST98A for the X direction is changed by the indication of intersection in the 544
A positive pulse is generated by It can be seen that the basic home N signal is maintained low at this time. Inverter I14
Since the output from B is low at this time, the output of NAND gate NA60A connected to input 10 of NAND gate NA73A is high, and gate N
This pulse does not work on A60A.

However, the positive pulse from the differentiating circuit 544 causes the inverter I4 to
6D, and a low pulse is formed at input 6 of NOR gate NO71B. Inverter I40B
Input 5 of gate NO71B from the output of
Since is low, the low pulse formed at the input 6 of this gate is inverted by this gate, and the positive pulse thus formed is sent to the flip-flop ff71.
Set C so that its output 13 goes low.

The output QD of the 4-bit counter CT58 is normally low. A high signal from output 13 of flip-flop ff71C clears the 4-bit counter to zero, keeping output QD in the clear state low. When the output 13 of the flip-flop ff71C becomes low, the hold is released by the counter CT58. At this time, the input of this counter provided as the homing LSObsc-P signal is used to count the counter. As mentioned in connection with FIG. 21c, since the LS shift N signal is low at this time, the homing LSOsc-P signal is a relatively slow square wave of 425 cycles/sec. Counter CT58
is counted by four pulses of the homing LSOsc-P signal at a slow rate, the output QD of this counter goes from low to high and differentiator circuit 558 generates a positive pulse.

The positive pulse from circuit 558 is inverted by inverter I46F and the portion of the pulse that exceeds the threshold is clipped, thereby forming a narrow low pulse at input 9 of NAND gate NA73A.

The positive edge of this narrow pulse is differentiated by the differentiating circuit 560, generating a positive pulse and flipping the flip-flop ff.
71C so that its output is high. Therefore, the hold flip-flop ff71C again clears the counter CT58 and outputs this counter until the flip-flop is set again.
Hold in the clear state where D is low. Since input 10 of NAND gate NA71A is high, the narrow low pulse at input 9 is inverted by this gate to a positive pulse, which is output to AND gate A132.
It enters input 1 of Noah Gate No. 134A through A. At this time, the fundamental home P signal applied to the other input of AND gate A 132A is also found to be high. This positive pulse is inverted to the low pulse for the X stop N signal to the NOR gate NO134A. As mentioned earlier in connection with FIG.
A high signal and an X travel P low signal are generated. As discussed in connection with FIG. 21j, the high state of X-travel N produces a low value of the X-count pulse P signal, and movement of the clamp in the X direction is stopped.

Movement in the X direction is detected by the X homing sensor until four clock pulses after a change or crossing of the workpiece holder as achieved by the counter CT58 described in connection with FIG. 21e. Since it does not end, the sensor passes the position where the direction change is instructed and the clamp is set to 4.
The stage is moved in the X direction. This is because the X-count pulse P and homing LSOsc-P signals are both synchronized at a slow rate of 425 pulses/second. Therefore, the final position of the clamp in the X direction is precisely determined by exactly four counts or steps past the intersection position determined by the X homing sensor at a relatively slow speed. Accordingly, the clamp is positioned to prevent directional ambiguity caused by the sensor if it is necessary to move the clamp in the X direction during the secondary homing mode.

It will be clear from the following description that after the combination of auxiliary and sub-auxiliary homing modes, the clamp is always in the same position for a given adjustment of the X and Y homing sensors.

The operation of the control system when terminating the movement of the crank in the Y direction is the same as described above in connection with the X direction. Second
As shown in Figure 1e, differentiator circuit 548 generates a positive pulse when a change in direction is indicated by Y home sensor and Schmitt trigger circuit ST98 such that both inputs of exclusivity OR gate EO101B are the same. . At this time, since the output of inverter I46B is low, the output of NAND gate NA75B and the input 4 of NAND gate NA73C are high. circuit 54
The positive pulse generated by NOR gate NO86B is inverted by inverter I83A and outputs to input 11 of NOR gate NO86B.
appears as a low pulse. Since input 12 of gate NO86B from inverter I46B is low, the low pulse at input 11 is inverted by this gate to a positive pulse, which is applied to flip-flop f.
Set f86G. As a result, the low state of output 4 of this flip-flop is the 4-bit counter CT.
87 is released and the homing LSOsc-P signal causes the counter to count up to 4, at which time the output QD of the counter goes high. In response, differentiator circuit 562 generates a positive pulse that is inverted and clipped by inverter I83B to form a narrow low pulse at input 5 of NAND gate NA73. The positive edge of this low pulse is differentiated by a differentiating circuit 564, which forms a positive pulse, which causes flip-flop f
Resetting f86C, its output and 4 go high, holding and clearing counter CT87. The narrow low pulse at input 5 of gate NA73C is inverted by this gate and then passes through AND gate A132D to input 4 of NOR gate NO 134B.

This gate NO134B inverts this pulse again as a low pulse of the Y stop N signal. As previously discussed in connection with FIG. 21d, the Y-Stop N low pulse resets the Y-Run flip-flop ff132B, resetting the Y-Run P signal low and the Y-Run N signal high. As stated in connection with FIG. 21j, the high state of the Y run N signal appearing at NOR gate NO 104A clears the Y count pulse P signal and stops the clamp from moving in the Y direction.

Therefore, the movement of the clamp in the sub-auxiliary homing mode is stopped in both directions. As stated earlier, it is irrelevant whether the clamp stops first in the X or Y direction.

As mentioned above, during the auxiliary homing mode, positioning of the clamp along the X or Y axis is not complete until the position is approached from the auxiliary mode particular direction. If the clamp moves from an incorrect position relative to a given axis during the auxiliary mode, a sub-auxiliary mode is entered for that axis or coordinate during which the clamp moves in a particular direction to its final home position. Therefore, if the clamp moves along both the X and Y coordinate axes during auxiliary homing mode in a particular direction, this secondary auxiliary mode will not be entered for either axis, and the clamp will be auxiliary. Correct home position during mode. Therefore, in this case the clamp is moved by the four-step motor beyond the position where the sensor indicates the correct change of direction relative to both reference axes. If the clamp moves in an unspecified direction along any axis, it enters the secondary assist mode for that axis.

During the auxiliary homing mode, if the clamp moves in an unspecified direction along both coordinate axes, it enters the auxiliary auxiliary homing mode on both axes and moves the clamp in a specific direction along both axes to the final home position. Moving.

The conversion from auxiliary homing mode to sub-auxiliary homing mode is described below. As shown in FIG. 21d, when both step motors are stopped in the auxiliary homing mode and the X and Y traveling flip-flops ff21Bff32B are reset by the X-stop N and Y-stop N signals, these flip-flops are A low signal is formed at both inputs of the NOR gate NO20C. As mentioned earlier, when both inputs of this gate go low, a positive pulse is generated as the mode pulse P signal.

Next, referring to FIG. 21c, since the output of inverter I46B is low at this time, the output of Nant gate NA73D supplied to single shot circuit SS33B is high, thus inhibiting the single shot circuit. This prevents the mode pulse P signal from triggering this single shot circuit. However, the output of inverter I46C is high at this time and the positive pulse of mode pulse P is inverted by NAND gate NA45B so that the low pulse formed at the output of this gate triggers single shot circuit SS33A at pin 9. A single shot circuit triggered in this way is then subject to a 10 millisecond delay. As mentioned earlier, this 10 millisecond delay allows the step motor to remain stationary because if the step motor is driven in the opposite direction while still undergoing relatively large vibrations, it will be driven again. This is because the robot moves in an inappropriate direction. Single shot circuit SS
When 33A times out and its Q bar output goes high, differentiator circuit 566 generates a positive pulse. This positive pulse appears at input 9 of AND gate A11A, and this pulse also appears at input 9 of inverter I108B.
Finally, it was reversed and input 2 of Noah Gate No. 98
A low pulse is formed.

At this time, it is clear that input 10 of AND gate A11A and input 3 of NOR gate NO98 are low. This is because the reset N signal causes both flip-flops ff60B and ff85A to be reset during Yesterday, resulting in a high signal at the input of NAND gate NA60C. Therefore, Nand Gate N
The output of A60C is low and the gate A11A
Input 10 of gate NO 9B and input 3 of gate NO 9B are both low. In response, the high pulse from the differentiating circuit 566 is applied to the AND gate A by the low input 10.
It is blocked by 11A. However, the low pulse at input 2 of NOR gate NO9B is inverted and passes through this gate. The resulting positive pulse is input 1 of NAND gate NA85B and input 4 of NAND gate NA85C.
and appears at pin 10 of single shot circuit SS59B.

The Q-bar output of flip-flop ff99A is supplied to the input 2 of NAND gate NA85B via delay circuit 568, and the Q-bar output of flip-flop ff99B is supplied to the input of NAND gate NA85C via delay circuit 570. As mentioned above, the Q-bar outputs of both flip-flops are set at the beginning of the auxiliary homing mode and the
and Y provide a reference for the direction in which the step motors are driven. Flip-flops ff99A and ff99B are in auxiliary homing mode and are not reset. When the Q bar output of flip-flop ff99A is high, the positive pulse at input 1 of NAND gate NA85B is inverted to a low pulse through this gate. ,
This pulse sets flip-flop ff60B and
Initializes the start of the axis sub-auxiliary homing mode.

Conversely, when the Q-bar output of flip-flop ff99A is low, the positive pulse is prevented from passing through gate NA85B, and the output of this gate remains high, thus preventing the X-axis secondary homing mode. Prevent initialization.

Similarly, if the Q bar output of flip-flop ff99B is high, the positive pulse at input 4 of NAND gate NA85C will be inverted through this gate, and the corresponding low pulse will set flip-flop ff85A to Initialize homing mode.

Conversely, if the Q-bar output of flip-flop ff99B is low, the positive pulse will pass through NAND gate NA85.
Since it is blocked by C, initialization of the Y-axis sub-auxiliary homing mode of flip-flop ff85A is prevented.

Therefore, the low Q bar output of flip-flop ff99A indicates that the clamp is approaching the home position from the correct direction. In this way the clamp is no longer
There is no need to move in the direction, and there is no need to enter the Y-axis sub-auxiliary mode. Instead, flip-flop ff99A
If the Q-bar output of is high, this indicates that it is necessary to move the clamp further along the X-axis to obtain the correct home position in the X-axis direction, and then Enter the mode. Similarly, in the Y-axis, the low Q bar output of flip-flop ff99B indicates that the clamp is driven in the correct direction during assist mode and not in sub-assist homing mode. Alternatively, if the Q-bar output of flip-flop ff99B is high, the clamp will not be moved in the correct direction during the auxiliary mode and will enter the Y-axis secondary auxiliary mode.

First, for convenience of explanation, flip-flops ff99A, f
Assume that the Q-bar output of the f99B is low indicating that the clamp is in the correct home position and not in sub-assist homing mode on either axis. Neither flip-flop ff60B nor ff85A is set.

Therefore, the output 1 of flip-flop ff60B
1 and output 8 of flip-flop ff85A remain in the initialized high state, and inputs 4 and 5 of NAND gate NA60C and AND gate A1
Both inputs 3 and 4 of 00C are high.

Single shot circuit SS59B triggered at pin 10 by a positive pulse from NOR gate NO9B receives a 6 microsecond delay before timing out to flip-flop ff60B when entering sub-auxiliary mode for one or more axes. Allow sufficient time for ff85A to set. When the Q bar output of the single shot circuit SS59B times out and goes high, the differentiator circuit 5
72 generates a positive pulse which passes through the ant gate A100C as a positive pulse by the high state of its inputs 3 and 4. This positive pulse is NOAH gate NO9
It is inverted by C and low as the end homing N signal.
form a pulse. The use of the termination homing N signal at the end of the homing mode is discussed in detail below.

Low pulse from NOR gate NO9C is inverter I1
0C, and the corresponding positive pulse is inverted by NOR gate NO9A as a low pulse of the homing clear N signal, which is used to initialize the next homing mode system. Therefore,
The low pulse signal of the homing clip 7N is sent to the flip-flops ff60B (Fig. 21c), ff85A (Fig. 21c), ff45A (Fig. 21e), and ff21A (Fig. 21d).
(Figure). As shown in FIG. 21d, the homing clear N signal causes the flip-flop ff21A to
When the basic home P output signal is reset, the output signal of the basic home P becomes low and the basic home N output signal becomes high.

As shown in FIG. 21c, flip-flop ff45A
Once reset, the LS Shift N signal goes high, causing the control system to operate again at the fast clock speed of 850 cycles/second, producing a low signal at the input of inverter I46B.

The remaining flip-flops in the homing circuit have already been reset. Continuity of the control system after homing mode is based on the termination homing N signal, as described below.

Now let us assume that the auxiliary homing clamp is not properly positioned along the X-axis and that a secondary auxiliary homing mode is required on the X-axis.

In this state, the Q-bar output of flip-flop ff99A is high, as described above in connection with FIG. 21e, and the positive pulse at input 1 of NAND gate NA85B is inverted by this gate, causing a corresponding The low pulse output is a flip-flop f
Set f60B. Furthermore, the low pulse signal of the auxiliary-auxiliary auxiliary set pulse N is supplied to the input 10 of the NAND gate NA101A, so the flip-flop ff9
Generate a positive pulse on the 9A CLK input. Therefore, position information from the X homing sensor signal is now established at the flip-flop's Q and Q bar outputs, as previously discussed.

It can be seen that the circuit parts of the X part and the Y part of the sub-auxiliary homing mode operate independently of each other. Therefore, if the Y-axis auxiliary homing mode is not entered, position information is not established in flip-flop ff99B.

When flip-flop ff60B is set, input 5 of NAND gate NA60C and AND gate A10
A low state is established at input 3 at 0C. Although single shot circuit SS59B is still triggered by a positive pulse at pin 10, the low state of input 3 of ant gate A100C prevents the positive pulse generated by differentiator circuit 572 from passing through this gate. Ru. After a 6 microsecond delay, single shot circuit SS59B times out and flip-flop ff60B (or flip-flop ff85A) sets and gate NA
Allow sufficient time for 60C and A100C to be adjusted. In this way, the low pulse signals for end homing N and homing clear N are not received at this time.

When flip-flop ff60B is set and its output 8 goes from low to high, differentiator circuit 574 generates a positive pulse as the X running set P signal. Referring to FIG. 21d, the X-running set P positive signal is inverted by NOR gate NO20A, and the resulting low pulse sets the X-running flip-flop ff21B. Referring to Figure 21j, the X running N low signal initiates the X count pulse P pulse train, which is formed from the LSOsc-N signal as previously described. At this time, the LS shift N signal remains low, and the LSOsc-N shaped wave signal and hence the X count pulse P
The pulse train is also at a low rate of 425 cycles/sec. In connection with FIG. 21k, the high signal of the X travel P and the pulse train of the X count pulse P form an X combo N low pulse train that drives the X step motor. As in auxiliary homing mode, at this time L
Since the S-shift N signal is low, the Xa pulse is inhibited.

Referring to FIG. 21c, the X-homing sensor detects the intersection of the workpiece holder along the Then a positive pulse occurs again. Since input 5 of NOR gate NO71B remains low, the positive pulse is inverted twice by inverter 146D and gate NO71B, and the resulting high pulse sets flip-flop ff71C. The resulting low output 13 on this flip-flop releases the hold on counter CT58, which is now still at a slow rate of 425 cycles/sec. The homing LSOsc-P signal starts counting up to 4 as triggered on the CLK input. When the counter counts to 4 and its QD output goes high, flip-flop ff71C is reset by a positive pulse from differentiator circuit 560, and as mentioned earlier, the low pulse of the X stop N signal is applied to gate NO.
It appears from 134A. The X-stop N signal resets flip-flop ff218 as described above in connection with FIG. 21d, so the X-run N signal goes high. Second
As mentioned in relation to Figure 1j, the X traveling N high signal is
Set the count pulse P signal low, thus stopping the X step motor. In response, the clamp moves 4 steps or 4 pulses in the direction of the x-coordinate axis past the position where the X-homing sensor indicates a change in direction, reaches the correct home position in the X-axis assisted homing mode, and moves from the correct direction.

Referring again to FIG. 21d, when the X travel flip-flop ff21B is reset by the X stop N signal,
This flip-flop establishes a low state at input 9 of NOR gate NO20C. The operation of the circuit in response to this signal will be discussed after the Y sub-auxiliary homing mode is explained.

The operation of the Y sub-auxiliary homing mode is the same as described in connection with the X-sub auxiliary homing mode.

Referring to FIG. 21e, if the Q bar output of flip-flop ff99B is high, which is set at the beginning of the auxiliary homing mode and indicates that the Y-axis auxiliary auxiliary homing mode should be entered, then the A low pulse from the output of NA85C sets flip-flop ff85A.

The low pulse of the Y-axis sub-auxiliary set pulse N signal is inverted by NAND gate NA100B and is used to clock Y position data into flip-flop ff99B as described above. set flip-flop f
Output 8 of f85A goes low, so input 4 of NAND gate NA60C and AND gate A100C
A low signal is generated at both input 4 and input 4. The low state of input 4 of AND gate A100C is the low state of input 4 of AND gate A100C.
This prevents the passage of positive pulses generated by 72. Therefore, when one or both of the X and Y sub-auxiliary homing modes is entered, the homing mode does not end at this time because the positive pulse from the differentiating circuit 572 does not pass through the AND gate A100C.

When the output 11 of the set flip-flop ff85A goes high, the differentiating circuit 576 generates a positive pulse as the Y running set P signal.

Referring to FIG. 21d, the positive pulse of Y-running set P is inverted by NOR gate NO20B, and the corresponding low pulse sets Y-running flip-flop ff32B. Therefore, the Y-Run-N output of this flip-flop is set low, and the Y-Run-N low signal causes the LSOsc--, which is at a low rate of 425 cycles/sec, to be set low, as discussed above in connection with Figure 21j. A pulse train of Y count pulses P is formed from the N signal. Referring to FIG. 21k, the Y combo N drive the Y step motor by the Y travel P high signal and the Y count pulse P pulse train.
A low pulse train is formed. As mentioned above, the LS shift N signal was low at this time, so Ya papal was inhibited.

Returning to FIG. 21e, when the Y homing sensor signal indicates a change in direction, the exclusive OR gate EO1
The signal at input 12 of 01B changes state and differentiator circuit 548 generates a positive signal so that the positive pulse appearing at input 5 of flip-flop ff86C sets this flip-flop and releases the hold of counter CT87. It should be noted at this point that input 12 of NOR gate NO86B is low at this time. When counter CT87 counts up to 4 and its QD output goes YES, flip-flop ff86C is reset by a pulse generated by circuit 564, and as mentioned earlier, a low pulse is applied to the output of NOR gate NO134B as a Y-stop-N signal. appear. Second
As described in connection with FIG. 1d, at this time, the Y-stop N signal resets the Y-run flip-flop ff32B, so the output signal of the Y-run N becomes high.

As stated in connection with FIG. 21j, the Y count pulse P signal is forced low by the Y run N high signal,
Stop the movement of the Y step motor.

In this way, the clamps move 4 pulses or 4 steps beyond their position when the Y-homing sensor indicates a change of state, and these clamps move to the desired home along the Y-axis during the Y-auxiliary homing mode. position and the clamp is then moved from the correct direction.

At this time, the appropriate direction of movement of the X and Y step motors is:
As shown in FIG. 21e, it can be seen that the basic homing mode, auxiliary homing mode, and sub-auxiliary homing mode are all determined by the X-direction and Y-direction signals. As stated earlier, the X and Y direction signals are determined by the X and Y home, command, and P signals from flip-flops ff99A and ff99B, respectively. Therefore, regardless of the specific homing mode involved, the Q outputs of these flip-flops are
is set in the proper condition to obtain proper control of the step motor and movement of the clamp in the desired direction.

Returning again to FIG. 21d, the Y traveling flip-flop ff
When 32B is reset to sub-assist homing mode, the Y-travel P signal is reset low. Therefore, input B of NOR gate NO20C is low when the Y direction movement during this sub-auxiliary homing mode is completed. In this way, when both X and Y sub-auxiliary homing modes are entered, both X and Y flip-flops ff21B
and ff32B are reset by the X stop N and Y stop N signals, respectively, the output of the NOR gate NO20C goes high. If only the X-auxiliary homing mode is entered, the X-travel flip-flop ff32B
is not set by the Y travel set P signal and input 8 of NOR gate NO20C remains low during the X sub-auxiliary homing mode. Therefore, in this case, when the X running flip-flop ff21B is reset by the X stop N signal, the output of the NOR gate NO20C becomes high. Similarly, if only the Y sub-auxiliary homing mode is entered, the X travel flip-flop ff2
1B is not set by the X travel set P signal and input 9 of NOR gate NO 20C remains low throughout the Y secondary auxiliary homing mode. Therefore, when the Y running flip-flop ff32B is reset by the Y stop N signal, the output of the gate NO20C becomes high at this time. Accordingly, the output of gate NO20C is only set high until completion of all secondary homing modes, whether X, Y, or X and Y.

At this time, the differentiating circuit 550 generates a positive pulse, and the positive pulse appears as a mode pulse P signal at the output of the NOR gate NO20D. Therefore, the positive pulse of the mode pulse P is generated regardless of whether one or both of the sub-auxiliary homing modes is entered.

Furthermore, referring to FIG. 21c, the mode pulse P
The signal is applied to input 12 of NAND gate NA73D and input 9 of NAND gate NA45B. Since input 13 of gate NA75D is low, single shot circuit SS33B is inhibited as described in connection with the auxiliary homing mode. However, Nand Gate NA
Inverter I connected to input 10 of 45B
Since the output of 46C is high, the positive pulse of mode pulse P passes through gate NA45B and is inverted to trigger single shot circuit SS35A at its pin 9. As before, this single shot circuit SS33A
is subject to a 10 millisecond delay, and when this single shot circuit times out, differentiator circuit 566 generates a positive pulse. Flip-flop ff60B or ff85A -
Either or both of inputs 4 or 5 of NAND gate NA 60C are low at this time since either or both are set during the start of the secondary homing mode. Therefore, the output of gate NO60C and input 3 of NOR gate NO9B are high, and the low pulse appearing at input 2 of NOR gate NO9B is prevented from passing through this gate by the high signal at input 3 of this gate.

However, since input 10 of AND gate A11A is also high as determined by the output of gate NA60C, the positive pulse generated by circuit 566 passes through this gate to input 6 of NOR gate NO9C.
reach. This positive pulse is inverted and passes through gate NO9C, so that a low pulse appears as the end homing N signal. The low pulse at the output of gate NO9C is also inverted by inverter I10C, and the corresponding positive pulse from this inverter is inverted by NOR gate NO9A as the low pulse of the homing clear N signal, which is used for homing in preparation for the next homing operation. Used to reset the flip-flop of the circuit.

Thus, at this point the homing mode is completed regardless of whether one or more sub-auxiliary homing modes have been entered.

Referring to FIG. 21d, flip-flop ff
Regardless of the state of the basic home P signal from 21A, when the pulse generated by differentiator circuit 550 decays, input 3 of OR gate O8C goes high, so input 1 of NAND gate NA11B is now high. Therefore, the low pulse of termination homing N is inverted and passes through NAND gate NA11B as a positive pulse, which triggers pin 10 of single shot circuit SS22B.

This single shot circuit SS22B is subject to a 5 millisecond delay and the differentiator circuit 578 generates a positive pulse. Since the NTB mode OP signal is high when there is no thread breakage instruction from the thread breakage sensor as described above, the NAND gate NA11C inverts the positive pulse. Before entering the homing mode, the clamp mode OP signal is set low, so the low pulse appearing at input 11 of NOR gate NO 34B is inverted by this gate and enters input 1 of NOR gate NO 135A as a high pulse. Since the auxiliary start P signal is normally low, the NOR gate N
The positive pulse at input 1 of O135A is inverted by this gate and again by inverter I31B, so that the positive pulse at input 6 of flip-flop ff34A is inverted by this gate and again by inverter I31B.
A positive pulse appears at to set this flip-flop. The output of the flip-flop's store cycle enable P is set high while the output of the flip-flop's enable N is set low to initiate the first store cycle under program control.

Under program control, the needles reciprocate at either fast or slow speeds. At high speed, the sewing machine is driven by a quick drive at a speed of about 3000 revolutions per minute so that the needle reciprocates at the same speed.

Therefore, the basic timing cycle for a fast speed sewing machine is 20 milliseconds/cycle, at which speed the needle enters the fabric -times every 20 milliseconds. At slow speed, the machine is driven at about 200 revolutions per minute so that the timing cycle is then about 300 milliseconds and the needle enters the fabric once every 500 milliseconds.

A schematic diagram of the timing cycle at a fast rate of 20 milliseconds is shown in FIG. At time T1 the needle is in the lowered position within the fabric and at time T2 the memorization cycle begins. Δ
This occurs during a storage cycle during which information is read from and decoded from the PROM at a time represented by T1. memory cycle (
The time required by ΔT1) is approximately 3/10 of 1 millisecond.
, and the storage cycle ends at time T3. Time T4
represents the time at which a positive pulse appears as the needle drop pulse P signal in response to the optical sensor of unit 62 indicating that energization of the motor is to begin. When receiving the needle removal pulse P pulse, the step motor starts moving for a time ΔT2. At a later time T51/2 the needle does not actually exit the fabric, but due to the delay time associated with the inertia of the motor and workpiece holder, energization of the motor begins at time T4. Therefore, the clamp driven by the step motor does not actually begin to move until a time T6, which is after time T5 when the needle exits the fabric. The time interval ΔT2 represents the final delay time at low speed of the sewing machine to prevent the clamp from moving at low speed before the needle exits the fabric.

Alternatively, slow commands may be programmed to cause the clamps to engage as little or not as desired.

The time ΔT3 represents the time required to actually move the clamp for the maximum allowable movement programmed in memory. The hands are in the raised position at time T1. The maximum movement of the clamp is therefore limited at high speeds due to the shortening of ΔT3 so that the clamping movement is approximately completed at T8 before the needle re-enters the fabric at time T9. The time elapsed for a time of ΔT4 is a 5 millisecond delay time after movement of the clamp before the next memory cycle begins at time T1. At this time, one cycle of the sewing machine is completed, and if the control system is in the sewing mode, the needle will reciprocate once during this period. During each timing cycle, information is read from the PROM and decoded to cause the clamp to move as specified during this cycle. The PHOM program causes this sequence of cycles during the sewing operation so that the clamp moves in a series of steps as described below.

During a memory cycle, the control system reads information from the PROM memory and uses the decoded data to operate the sewing machine. Referring to FIG. 26, each PROM has 256
8-bit words, each word is 1, 2, 3,...255, 2
56. Each bit of each word is b1, b2...,
b7, b8, bit b1 is the lower bit,
Bit b8 is the upper bit. All of the 8-bit words are divided into two banks A and B, with the low order bits b1, b2, b3, b4 of each of the 256 words being in bank A and the high order bits b5, b6, b7, b8 being in bank B.
It is in. Thus, Bank A consists of 256 lower 4-bit words and Bank B consists of 256 4-bit words of higher order bits. Each 8-bit word or corresponding address of the memory is stored on the left side of the diagram. 2 in memory
Since it contains 6 words, the address of the first 8-bit word is the binary digit 00000000, and the address of the 256th 8-bit word is 00000000.
The binary digits of the Bitword address are 11111111. The memory cycles used for each word are also illustrated and described below.

Referring to FIG. 21a, the sewing machine operator selects various program modes via the four-way program selection switch as described above in connection with FIG.

In selection A, all programs are in PROM sewing machine A,
It is itself made up of separate programs. Similarly, if the operator selects the B setting of the switch, all programs will be used in bank B. If remote setting A/B is selected, the operator switches the sewing machines and obtains separate programs for sewing machines A and 8 by activating the foot pedal switch. If the program selection switch extension is set, the control system will first utilize the program portion located in machine A and then automatically switch to the remaining program portion located in bank B.

Referring to FIG. 26, the memory layout of the prom is illustrated when the program selection switch is set to A, B or remote A/B selection. In this diagram, the complete program should be in two banks and one or both.

Therefore, if bank A is selected by the operator, the complete program should be stored in bank A, and the data required for this program must be less than the program capacity in this bank. Similarly, if sewing machine 8 is selected by the operator, a separate program is created for sewing machine B.
This program must be less than the capacity of this bank; however, it is desirable to store separate programs in memory to maximize the use of the PROM, if possible. Therefore, the operator can select a desired program for operating the sewing machine by setting the program selection switch. Also, when selecting remote A/B of the program selection switch, each bank should have a program, and after completing the program of one bank, the operator can switch to the other bank by pressing the foot pedal. Select a program. In this way, after completing the programming of the one sewing machine, the operator depresses the foot pedal and the programming of the other sewing machine is started. Once the second sewing machine has been programmed, the operator again starts programming the first bank by depressing the foot pedal or continues working with the same program as desired.

Therefore, both machines have separate programs, and either program may or may not contain the entire 256 4-bit words of the machine. sewing machine 1
During each memory cycle of a sequence, three 4-bit words are used from each bank that stored the sequence. Thus, when programming of bank A begins, the control system skips memory address 00000000 during the first memory cycle and uses the first 4-bit word at address 00000001 in the second word. Start the program. The control system first reads and decodes the Y data from bank A in the low bit portion of the second word. After decoding the Y data, read the 4 bits of the X data in the third word of bank A corresponding to address 00000010. After decoding the X data, the control system goes to address 00.
The 4-bit control or command is read from the low order 4 bits in machine A in the fourth word corresponding to 000011, and then the control system decodes this information for the purpose of machine single-sequencing.

In this way, at this time during the first memory cycle PR
The complete 12 bits of information are read from the OM and no more information is read from the PROM until the next memory cycle, which is about 20 milliseconds later when the machine is running at high speed. During the second memory cycle, the control system reads the Y data from the 5th word of sewing machine A, the X data from the 6th word of bank A, and the control word 7 of bank A when the address register carries up. , this information is decoded during reading.

Therefore, during each subsequent memory cycle, it continues to read three 4-bit words from machine A until the control system has been programmed. Assuming that the program occupies all of the memory of sewing machine A, the last memory cycle is number 85 as shown, and during this memory cycle the control system starts from the 254th word of sewing machine A with the Y data and bank A. Then, the control word from the 256th word of sewing machine A corresponding to address 11111111 is read. At this time, since the program in question is all contained in sewing machine A, this program must be completed, and therefore the control word of the 256th word must be the end of the program command. of course,
If you do not need to use the entire memory of the sewing machine,
The program may end at some memory cycle before the fifth memory cycle.

The same operation occurs when reading a program from bank B.

During the first memory cycle, the 4-bit data contained in the second to fourth words of control system bank B are read in sequence, and the first word is skipped over at address 00000000. In this way, the control system connects the Y data from the second word of bank B, which corresponds to address 00000001, and address 0
0000010, the corresponding X in the third word of bank B
Bank B corresponding to data and address 00000011
Read the fourth word, the control word. During the second memory cycle, three 4-bit words are read from machine B's words 5-7. The reading sequence continues until the program is completed, and if the program occupies the entire sewing machine B, 254~
The last three 4-bit words are read starting from word 256.

FIG. 27 shows the state of the program memory when the program selection switch is set to the extension mode. This mode of selection switch is used when the program is too large to be contained within one bank of PROM. During the first memory cycle, the control system is at address 00
Obtain the first 4-bit word containing Y data from the second word of bank A corresponding to 000001. Furthermore, bank A 3
, continue reading the next two 4-bit words after the fourth word. During the second memory cycle, the program reads three 4-bit words from bank A, words 5-7. The control system reads three 4-bit words in sequence during each memory cycle,
Finally, during memory cycle No. 85, 25
Information from the 4th to 256th words is obtained, and at this time P
Reading information from the ROM is automatically switched to bank B. During the 86th memory cycle, the program first reads the Y data contained in word 1 of bank B, which corresponds to address 00000000. In this way, sewing machine B in the extended mode will not jump to address 00000000. As shown, the second and third 4-bit words in memory cycle 86 are obtained from the second and third words of bank B, respectively. The control system continues to read information from bank B during each memory cycle until the program is complete. If the program occupies all of the memory in bank A plus bank B, the last memory cycle is 170 and comes from the 255th word in bank B, which corresponds to address 11111110. In extension mode, the 25th address of bank B corresponding to address 11111111
Not used for the 6th word. Since the number 256 is not divisible by 3, there is always one 4-bit word in each bank that is never used.

As shown in FIG. 28, the Y data word consists of 4 bits, regardless of the bank in which it is contained, and is used as position information for the clamp movement. As mentioned above, in sewing machine A, lower bits b1, b2, b3, and b4 include 4 bits,
- side bank B contains four Y data bits in high-order bits b5, b6, b7, and b8. A typical word is shown to be a binary digit, consisting of a decimal number three. With this information in the Y data word, the control system directs the step motor to move the clamp three steps in the Y direction.

Similarly, referring to Figure 29, the X data word is stored as the four least significant bits in bank A and
It consists of 4 bits included as the 4 upper bits. In this particular example, the X data information, when encoded in binary form, equals five steps in the X direction.

The type of 4-bit control word for both X and Y position information is shown in FIG. If this control word is stored in bank A, it will be located in the lower bits b1, b2, b3, b4, and if it is stored in bank B, it will be located in the higher bits b5, b6,
Included in b7 and b8. Its type is the same whether the word is in bank A or B. The lower bit of the 4-bit word indicates the desired direction of motion in the Y direction. bit b
If 1 or b5 is a binary 1, this indicates that the clamp should move in the +Y direction relative to the needle.

Therefore, the clamp moves in the +Y direction by the amount of momentum indicated by the corresponding Y data word. If binary bit b1 or b5 is 0, this means that the clamp is the momentum contained in the Y data word -
Indicates that it should move in the Y direction.

Direction information for X-direction movement is specified in the second lower bit b2 or b6 of the 4-bit control word. If the bit is a binary 1, movement in the +X direction is indicated; if the bit is a binary 0, the clamp moves in the -X direction. Therefore, the clamp will move in the particular direction indicated by this bit, and the magnitude of the direction is indicated in the X-Deck word.

The two high order bits of the control word indicate the particular sewing mode to be received in response to this memory cycle. If the mode sign or instruction bit is binary digit 00, then stop
Enter sewing mode. In this mode, the sewing needle stops reciprocating and the clamp moves without sewing. The cloth in this mode is not sewn, but the direction and magnitude of the movement in the X and Y directions are as described above.
specified by the data word. If the mode codes of the two high order bits have a binary value of 01, the sewing machine is commanded to the sewing mode. In this state, the sewing machine operates at high speed. If the two high order bits have the number 10, the low speed sewing mode is entered and the sewing machine is run at low speed. During sewing mode and low speed sewing mode, the X and Y direction information and the X and Y data words are used as clamp position information. This low-speed sewing mode is normally entered near the end of a program or before the stop sewing mode, and is used to operate the sewing machine at a low speed just before the needle stops reciprocating.

Finally, if the mode code is binary 11, it enters end-of-program mode, which commands the sewing machine to stop reciprocating the needle, and enters homing mode, which positions the clamp at the proper home position relative to the needle. It becomes automatic. The end-of-program command or mode occurs only once within a program and is the last command used in the program to end a sewing operation.

By programming a sequence of control words and associated X and Y data words, a program for the operation of the sewing machine is obtained. For example, the mode code of the first control word is a stop sewing command to move the kunpu from the home position to a position with an interval at which the sewing operation starts. Instead of that,
The mode code of the first control word is distributed in the magnitude indicated by the X and Y data words corresponding to the directions indicated by the X and Y directions in the same control word during the first timing cycle of the sewing machine. It may be a sewing command that sews at high speed. Preferably, a continuous sequence of control words is used that commands the sewing mode to stitch continuously at high speed while moving in the direction and magnitude specified by the associated data. At some point, in order to sew the corner of the label onto the fabric, the clamp may be moved to align the different strands of the label with the needle, while at other intervals the sewing movement will start again from the first sewing position, for example. It is desirable to move to an open position. In this case, a low speed sewing command is used to operate the sewing machine at low speed. The stop stitch mode is then entered by using the appropriate information in the mode code bit of the control word, at which time the thread is automatically cut and the clamp is set according to the direction and magnitude information associated with the particular stop stitch command. be moved. Of course, a continuous sequence of stop stitch commands may be used to move the clamp continuously without stitching. When the clamp is positioned as desired during the stop sewing mode, the sewing mode is re-entered and the sewing machine is operated continuously. Finally, when it is desired to finish a sewing pattern, the machine enters a slow sewing mode for a few commands to slow down the machine before entering the end-of-program mode. When the end-of-program mode is commanded, the needle stops reciprocating, the thread is automatically cut, and the clamp is returned to its home position by the control system. At this time, the program and sewing operation are completed.

The program control system sews a first pattern consisting of a sequence of commands and steps to move the clamp to a second spaced position on the fabric without sewing, and then sews a second pattern consisting of a sequence of sewing steps. U gives instructions to the sewing machine to sew the pattern and then exit the program. If desired, multiple spaced stitch patterns may be sewn after moving the clamp without stitching between sewing sequences to form a multiple spaced stitch pattern.

The control system operates as follows during the first and subsequent memory cycles. When flip-flop ff34A shown in FIG. 21d is set and the memory cycle enable P signal goes high, differentiating circuit 58 shown in FIG.
0 generates a positive pulse. This pulse is inverter I2
4E, I24F, flip-flops ff3A, ff3B, ff4A, ff4B, ff15
The inputs of A, ff15B, ff27A, and ff27B are reset by this positive pulse. Therefore,
These flip-flops are later initialized at the beginning of a memory cycle to decode the X and Y position information.

As shown in FIG. 21C, when the memory cycle enable N signal goes low in response to the setting of memory cycle flip-flop ff34A of FIG. It is inverted and passed through this gate as a clock pulse signal. Thus, the first pulse after memory cycle enable P goes low passes through gate NO38A.

Although the nature of the clock pulse signal has been described above, the clock signal can be better understood by referring to the signal waveform of FIG. As shown, the clock pulse signal consists of a train of narrow pulses, the leading edge of each pulse corresponding to the trailing edge of the high speed clock output from the high speed oscillator. A pulse train of clock pulses is thus formed with a high speed oscillator clock speed corresponding to a rate of 8500 pulses/second.

As shown in Figure 21j, the clock pulse signal is applied to pin 10 of a single shot circuit SS48B, with each pulse triggering the single shot circuit. Since the pulse of the clock pulse signal is relatively narrow, a single shot circuit SS48B is used.
regenerates the pulses, resulting in a corresponding address clock P pulse train of wide pulses at the Q output of this single shot circuit, as shown in FIGS. 21j and 31.

As shown in FIG. 21j, the address clock P signal is connected to a strobe counter C.
Provided to T65's CLK input. This counter CT65 is a 4-bit counter, but only the two lower bits are used. That CLR on this counter
The input is cleared to the 0 state by the reset N signal during initialization of the control system. This counter is also triggered on the trailing edge of each pulse of the address clock P signal, with its output 14 representing the lower order bit and its output 13 representing the next higher order bit.

Therefore, the trailing edge of the first pulse received from the address clock P signal registers the two lower bits of this counter by one count such that output 14 of this counter is high and output 13 is low. the binary number 01
increases to This particular output is used to decode the Y data as seen below.

Since the strobe counter CT65 has already been cleared to 0 by the reset N signal, the outputs 14 and 13 of this counter are initially low before the counter increments. Therefore, after initialization, input 4 of NAND gate NA51A, input 1 of NAND gate NA51B, and inputs 10 and 11 of NAND gate NA51C are low, and before the counter increases, the outputs of NAND gates NA51A, NA51B, and NA51C are high.

The counter first increments its count and its output is 1
4 is high and output 16 is low, the high input 14 of this counter is inverted by inverter I50E to input 3 of NAND gate NA51A.
, 4 are both low and their outputs remain high. However, for the NAND gate NA51B, the low output 13 of the counter is the inverter I50F.
Input 2 of this gate is set high. Since the current input 14 of the counter is connected to the input 1 of this gate, the gate N
Input 1 of A51B is also high, and input 16 of this gate is ready for use. counter CT
Low output 15 of 65 is NAND gate NA51C
Since it is connected to input 11 of
The output of C remains high. As shown,
The Q-bar output of single shot circuit SS63A connects all three gates NA51A, NA51B, NA51C.
is supplied as an input to As stated below,
This single shot circuit Q bar output is counter C
Since T65 is set low until it increments the count, the single shot circuit has all three gates NA51A,
NA51B and NA51C are inhibited and the outputs of these gates are high until the single shot circuit times out and its Q bar output goes high.

As shown, a pulse train of clock pulses is applied to pin 10 of a single shot circuit SS63A, which is triggered by each pulse. As shown in FIG. 61, the Q bar output of the triggered single shot circuit SS63A goes low at the leading edge of the pulse of the address clock P signal, and the delay time corresponding to this single shot circuit is low at the leading edge of the pulse of the address clock P signal. It is longer than the pulses of the clock P pulse train. In this manner, the single shot circuit times out after the trailing edge of the address clock P signal pulse, at which time counter CT65 increments.

In this way, the counter CT65 detects the gate NA51A before the single shot circuit SS63A times out.
, NA51B, and NA51C, and its Q bar output returns to high.

When single shot circuit SS63A times out, it establishes a high state at input 5 of gate NA51A, input 13 of gate NA51B, and input 9 of gate NA51C.

As stated earlier, when counter CT65 initially increments, the outputs of gates NA51A, NA51C are held high by the output of the counter. However, when single shot circuit SS63A times out, all inputs of NAND gate NA51B are high, and the output of this gate changes from high to low. Therefore, the Y-slope N signal changes from a high to a low state, and as shown in Figure 21i, this signal is inverted by the inverter I50C so that the output of this inverter now goes from low to high. . In response, differentiator circuit 520 generates a positive pulse at the output of inverter I50D. The use of this pulse to decode the Y information is detailed below.

Referring to FIGS. 21j and 31, at the next pulse in the pulse train of clock pulses, the single shot circuit S
S63A is re-triggered and the next re-generated pulse of the address clock P signal is formed, counter CT65
increases again at the trailing edge of the address clock P pulse. Therefore, this counter will then have two bits of the order changed to a binary 10, its output 14 will be low and its output 13 will be high. Gate N
Since input 1 of A51B and input 10 of gate NA51C are both low, the outputs of these two gates are held high at this time by output 14 of counter CT65. However, since output 14 of counter CT65 is inverted by inverter I50E, a high state is established at input 3 of NAND gate NA51A. In addition, counter CT6
Since output 13 of 5 is high, gate NA5
1A input 4 is also high. Single shot circuit SS
When 63A times out again and its Qbar output goes high, input 5 of gate NA51A
A high state is established. Therefore, the X Strope N output of gate NA51A now goes from high to low, and as shown in Figure 21i, the X Strope N signal is
Inverted by inverter I51A, its output goes from low to high when single shot circuit SS63A times out. In response, differentiator circuit 518 generates a positive pulse that appears at the input of inverter I508. The use of this pulse to decode the X-data information is discussed in detail below.

Referring to FIGS. 21j and 31, at the third pulse of the clock pulse, the single shot circuit SS63A
is triggered, an address clock P pulse is formed, and counter CT65 increments on the trailing edge of the address clock P pulse.

Counter CT65, which has been incremented in this way, has a binary number of 11, and both outputs 14 and 13 are set to high. The output of counter CT65 is inverted by inverter I50E, input 3 of gate NA51A is low and this gate is inhibited. Similarly, high output 13 of counter CT65
is inverted by inverter I50F, input 2 of NAND gate NA51B is low, and this gate is also inhibited and its output is high.

However, the high outputs 14 and 13 of the counter are connected to the inputs 10 and 11 of the NAND gate NA51C, thus conditioning this gate.

When single shot circuit SS63A times out, all three inputs of gate NA51C are high, changing the state of the output of this gate from high to low, and the low signal triggers pin 1 of single shot circuit SS63B.

As shown, the Q-bar output of single shot circuit SS63B is inverted by inverter I52A, and when the single shot circuit is triggered, the EMC-P signal is set high so that the memory cycle complete. The EMC-P signal is inverted by inverter I52B and the low output of this inverter appears at the CLR input of counter CT65 to clear the counter to 0 for use during the following memory cycle. As shown in Figure 21d, EM
C-P high signal is memory cycle flip-flop f
Resetting f34A, the memory cycle enable P output is reset low and the enable N output is reset high. As discussed below, EMC-P signals are used throughout the circuit. Referring to Figure 21j, the EMC-P signal returns to its normal low state when it times out shortly after triggering the single shot circuit.

Thus, we have previously described how three consecutive pulses of a clock pulse signal are used to sequence a circuit through a memory cycle. In this regard,
Since the pulses of the clock pulse train occur at the trailing edges of the pulses of the fast clock signal from the high speed oscillator, the Y-strope N, be done.

Chapter 21a explains how to obtain information from commercially available PROM memory.
Write in relation to figures. A predetermined memory word address or PROM inputs A0, A1 are input to the internal gates of the PROM.
...When appearing in A6, A7, the 8 bits of this memory word are output signals D0, D1, ...D6, of the PROM.
Appears as D7. The address has 8 bits because there are 256 8-bit words in the PROM and the 8-bit address forms 256 binary numbers to address each 8-bit word in the PROM. When addressing the PROM storage, the lower 4 bits of the addressed word in bank A appear as output signals D0, D1, D2 and D3, and the higher 4 bits of the word in bank B appear as output signals D4.
, D5, D6, D7. In this way,
Output D0 represents the least significant bit of the word and output D7 represents the most significant bit.

As mentioned earlier, the high pulse of the address clear P signal formed before entering homing mode is used to clear both address registers AR1 and AR2 to zero. Two registers AR1 and AR2 are required 8
It is a 4-bit counter followed to obtain a bit address, register AR1 containing the lower 4 bits of the address and register AR2 containing the higher 4 bits of the address.

Recall that each pulse of the address clock P pulse train is formed by each pulse of the clock pulse train as shown in FIG.

Referring again to Figure 21a, the address clock P signal is applied to the CLK input of an address register AR1 containing the low order four bits of the address, and the address register AR1 is clocked at the trailing edge of each pulse of the address clock P pulse train. Increase the count. Address register AR1 will be filled with the binary number 1111 once enough numbers have been counted to fill it.
By this register, address register AR2
A carry signal is generated on pins 7 and 10 of . This carry signal enables register AR2, which increments with the next pulse received at its CLK input from the address clock P signal. This same pulse increases the count in the lower register AR1, which returns to the zero state and has a binary value of 0000. At this time, the carry signal from register AR1 becomes low and register AR1
remains low until filled again. In this way, the higher register increments once for every 16 counts in the lower register AR1, and the address clock P signal increases by 256.
Increment the counts in these registers through a range of binary numbers. The outputs of registers AR1, AR2 are used as signals for the current address at inputs A0, A1 . . . A6, A7 of the prom. Thus, as the address register counts, the 8-bit word of the PROM corresponding to the address is formed at the output of the PROM.

Therefore, during the first memory cycle of a program, when the first pulse from the address clock P signal is received at the CLK input of address register AR1, this address register has one in its low order bit and one in its three high order bits. Increase the count by one count so that the focus remains at zero. Also, address register AR2
All 4 bits of address register AR2 remain at 0 at this time since they are already cleared to 0 and are not incremented by the first pulse. Therefore, the PROM input is set to address 0000000 by these registers.
A binary 1 is formed at input A0 of the PROM, and the register thus commands the PROM to present the 8-bit word corresponding to this address at the output of the PROM. It can be seen that during the first memory cycle, address 000000000 is not used.

The address register AR is set by the address clock P signal.
When the 1 counts again, the address 00000010 is formed at the output of this register, and the prom selects the corresponding 8-bit word in memory and forms the word at its output. When register AR1 increments for the third and final time during the first memory cycle, the PROM again forms an output signal based on the register's output signal. Thus, for each memory cycle, the address register increments three times, producing three separate outputs from the PROM. In this manner, the address registers increment in sequence to obtain the information in memory at the output of the PROM, forming three output words for each memory cycle.

The four selected bits of each 8-bit word of the output of the PROM become inverted information as signals A data N, B data N, C data N, and D data N as described below. First, assuming that the program selection switch is set to terminal A, PROM outputs D0, D1, D2
, D3. When terminal A is opened, the resistor R1 is
A high state is established at the input of inverter I131C via 35. This high signal is the inverter I31C
, I31D, and the AND gate A13
A high signal is formed at input 2 of 6A, input 6 of AND gate A136C, input 2 of AND gate A137A, and input 6 of AND gate A137C. This high signal causes these gates to
The data from the three low order bits are shown below as NOR gates NO138A, NO138B, NO138
C, put it in a state where it passes through NO138D.

The low output from the inverter I131C is the input 4 of the AND gate A136B, and the AND gate A13.
It is supplied to input B of 6D, input 4 of AND gate A137B, and input 8 of AND gate A137D. Input 2 of Noah Gate No. 138A, Input 4 of Noah Gate No. 138B, Noah Gate No. 1
Input 6 of 38C and input 8 of NOR gate NO 138D are low at this time.

PROM output D0 is AND gate A136A
is connected to input 1 of the AND GATE A13
Since input 2 of 6A is high, output D
0 is high, input 1 of NOR gate NO 138A is also high, and NOR gate NO 138A is set to A by the low signal of input 2 of NOR gate NO 138A.
A high signal is inverted to a low state as a data N signal. Conversely, if PROM output D0 is low, input 1 of NOR gate NO 138A is also low, and the NOR gate inverts this signal to a high state as the A data signal. In this way, output D0 from the PROM is inverted as the A data N signal, output D1 of the ROM is connected to input 5 of the AND gate A136C, and the binary state of output D1 is inverted as the B data N signal by the NOR gate NO138B. It is clear that it is reversed as Similarly, PROM output D2 is connected to input 1 of AND gate A137A, thus producing an inverted signal of C data N. Finally, PROM output D3 is AND gate A137C.
This output of the PROM is inverted as the D data N signal.

The four higher outputs of PROM in bank B D4, D
5, D6, and D7 are AND gates A136B and A, respectively.
136D, A137B, and A137D.

Since the other inputs of these gates are low, the state of the bank B PROM output is A data N, B data N, and C data at the current set of program select switches.
This does not affect the formation of data N and D data N signals. When the program selection switch is thus set to bank A, the four lower bits appearing at the PROM output are inverted, forming the A data N, B data N, C data N, and D data N signals. .

When the address registers are counted and the corresponding 8-bit words of the memory appear in sequence at the output of the PROM, only the four least significant bits are used to form the data N signal.

When the program selection switch moves to the B terminal to select bank B, the terminal B and contact of this switch are grounded, so it is inverted twice by the inverters I131C and I131D, and the AND gates A136A and A136
One of the inputs of C, A137A, and A137C goes low. Therefore, input 1 of NOR gate NO 138A, input 3 of NOR gate NO 138B, input 5 of NOR gate NO 138C, and input 5 of NOR gate NO 138C.
Input 7 of 138D is low, and the PROM's four low order outputs D0, D1, D2, D3, which are connected to the other inputs of the AND gate in question, influence forming the data N signal. Never.

However, since the output of inverter I131C is high at this time, input 4 of AND gate A136B, input 8 of AND gate A136D, input 4 of AND gate A137B, and input of AND gate A13
All inputs 8 of 7D are high at this time. PRO
M's four upper output signals D4, D5, D6, D
7 is connected to the other input of these AND gates, so the NOR gates NO138A, NO138B,
NO138C and NO138D invert the PROM output as A data N, B data N, C data N and D data N signals.

The PROM inverted output D4 corresponds to the A data N signal, the PROM inverted output D5 corresponds to the B data N signal, the PROM inverted output D6 corresponds to the C data N signal, and the PROM inverted output D7 corresponds to the D data N signal. Corresponds to the N signal. Thus, when the program select switch is selected to read from PROM bank B, the four upper PROM outputs are inverted and formed as the data N signal. Address register AR1, A
R2 corresponds to the data N signal when sequenced through the PROM through the 8-bit word of memory. The sequence is P
It is formed from the high order bits of the ROM. Therefore, data N
Whether the signal is formed from the four lower or higher bits of the PROM depends on setting the program select switch to read from bank A or B of the PROM.

Referring to FIG. 18, lamps 467, 469 are provided on the front panel of the cabinet to indicate the current bank of PROMs from which the control system obtains information. If the program select switch contacts are set to terminal A to read information from PROM bank A, then inverter I130D
The input of this inverter is high, the output of this inverter is low, and since lamp 467 is lit by the power supply Vcc connected to this lamp through resistor R135B, this control system reads from bank A of the PROM. Instruct that there is. Similarly, inverter I1
The output of 30C is high and lamp 469 is not lit. When the program select switch is set to the B terminal, the output of inverter I131C is high and therefore the output of inverter I130C is low. Lamp 469 is turned on by power supply Vcc connected to this lamp via resistor R135C. Since the output of inverter I130D is high, lamp 467 is not lit at this time.

As previously mentioned, the program selection switch is set in extended mode so that the control system first reads data from bank A of the PROM and automatically switches to bank B for obtaining the remainder of the program.

The address clear P signal is sent to the flip-flop ff130.
It is used to reset this flip-flop before the control system enters homing mode so that output 1 of A and the extension terminal of the program select switch are reset to a high state. Therefore, when the contact of the program selection switch is set to the extension terminal, the inverter I13
The C input is high and the four low order outputs of PROM bank A are interpreted as data N signals, as described above in connection with setting the program select switch to terminal A. However, the address register increases its count through various states and finally becomes full.
When both registers AR1, AR2 contain all binary ones and the last word from bank A is formed at the output of the PROM, the carry output 1 of register AR2
5 is high.

Inverter I130B inverts the execute signal from register AR2 and forms a low signal at its output. When both registers change to a binary number of all zeros upon receiving the next pulse from the address clock P signal, the carry output 15 of register AR2 goes low and the inverter I
The corresponding output of 130B will be high. Therefore, differentiator circuit 582 generates a positive pulse that sets flip-flop ff130A to a low state at its output 1 and extension terminals, thereby reducing the PROM output bit used to form the data N signal. to the four high-order bits of bank B.

Therefore, at this time, the data N signal corresponds to inverted information obtained from address 00000000 of bank B of the PROM. PRO for the address register to increase the count from now on
Later information is obtained from bank B of M. lamp 467,
469 is the PR used during program extension mode.
It is clear that it indicates the current bank of OM.

As previously mentioned, the operator selects the program bank to be used by using the third foot pedal, setting the program selection switch to the remote A/B selection terminal. Each press of the third foot pedal activates a remote program selection switch that alternately grounds its normally closed (NC) and normally open (NO) terminals. When the NO terminal is removed from ground, output 5 of opto-isolator OP139 goes high. Therefore, the input of inverter I131C, which is connected to the output of opto-isolator OP139 via the contacts of the program select switch, is now high and the lower output from PROM bank A is used to form the data N signal. After programming bank A is complete, the operator presses the pedal to activate the remote program selection switch and ground the NO contact.

In this case, output 5 of optoisolator OP139 is low, so the input of inverter I131C is low, selecting information from bank B of the PROM. After the bank B program is completed, the operator presses the pedal again to select a separate program for bank A. Alternatively, the operator may use programs from the same bank many times if desired without switching to other banks.

At this time, lamps 467, 469 indicate the program bank currently in use, avoiding confusion that may arise regarding banks when the foot pedal is used.

Recall in connection with FIGS. 21j and 31 that the first pulse from the train of clock pulses during a memory cycle forms a Y-slope signal. However, this signal is not generated until single-shock circuit SS63A times out, and sometimes the address clock P signal is output to address register AR1 of FIG. 21a.
, sometimes after increasing the count of AR2. Therefore, the A data N, B data N, C data N, and D data N signals are formed from the Y data word to newly set these address registers before receiving the Y strobe N low signal. Similarly, when the second pulse of the clock pulse signal is received for use with the X data, the address register has already been incremented by the address clock P signal and before receiving the low signal of the A data N signal is formed from the data. Finally, upon receipt of the third pulse of the clock pulse signal, the address register is already incremented and the EMC-P high signal is formed before triggering the single shot circuit SS63B of FIG. 21j. Therefore, a control word is formed as a data N signal before receiving this EMC-P high signal.

As shown in FIG. 21j, A data N, B data N, C
Data N, D Data N signals are supplied to both X and Y preset counters CT61 and CT62. These counters CT61 and CT62 are used as 4-bit out counters and are cleared by the reset N signal during initialization.

Both counters operate such that the information of the Data N signal enters the counters when a low state appears on pin 9 of these counters at the time of the rising edge of pin 2 of these counters.

As previously stated, the Y strobe N signal goes low after the PROM's Y data word is formed as the data N signal in response to the first pulse of the clock pulse signal. Therefore, the signal at pin 9 of Y counter CT62 is low at this time. In this way, the data N signal is transmitted to the Y counter CT62 when a rising edge is obtained on pin 2 of this counter.
filled with.

The Y strobe N signal is also provided to the input of inverter I67C. When the Y strobe N signal goes low,
The output of inverter I67C goes high and differentiator circuit 584 generates a positive pulse at input 5 of NOR gate NO104C. This positive pulse is NOAH gate NO1
04C and inverter I67E to form a narrow positive pulse at input 9 of NOR gate NO104D. This gate NO104D inverts this pulse again into a narrow low pulse which appears at pin 2 of counter CT62. At the rising edge of the low pulse of pin 2, A data N, B data N, C
Data N, D The data N signal is strobed by the counter CT62 for later use. A
Recall that the Data N signal is a low order bit and the D Data N signal is a high order bit, and that the Data N signal is in inverted form. Therefore, the counter CT62 is used to increase the count of this inverted data toward a binary number of all ones.

As you can see below, the data contained in the Y counter is Y
Indicates the number of steps the step motor should be driven,
A Y counter is used to count these steps. A Y Combo N pulse train is formed to drive the Y step motor, and the pulse train includes the appropriate number of pulses by which the step motor is to be moved. However, this pulse train is modified to obtain better control of the step motor, and the way this pulse train varies is based on the number of pulses or steps that the motor is driven.

If four or more pulses of the Y Combo N signal are used during a given timing cycle of the sewing machine, the initial pulse is removed from the pulse train and automatically added to the end of this pulse train without using the Y counter. Therefore, in this case, the data of the counter should be modified to take into account the missed pulse, and since the data of this counter is in inverted form, the counter is incremented by one count and the Y combo with this counter is Maintain the correspondence between the counted portions of the N pulse train.

As long as the signal at pin 9 of the Y-counter CT62 remains low, the counter will not increase in number, although the data N signal will fill the counter with information as described above. However, once the signal on pin 9 of this counter goes high, the counter increments by one on the rising edge of the signal on pin 2. A high state does not occur in the counter 9 until the Y strobe N signal goes high, and this Y- Y strobe N signal going high means that the single shot circuit SS63A during the memory cycle
Occurs when is triggered for the second time.

At this time, the Q bar output of the single shot circuit is low and the Y strobe N signal returns high.

As seen below, the X data word is decoded to form a modified pulse train to the Y step motor. If this decoded data indicates that four or more pulses should be issued to the Y step motor, the Y Decode 4 Plus N signal is set low. If less than four pulses of the pulse train are formed for the motor, the Y-decode 4 plus N signal remains high, in which case NOR gate NO 104B of FIG. 21j is inhibited and a low signal appears at its output; Counter CT62 does not increase the count. However, if the Y step motor is stepped with four or more pulses and the Y decode 4 plus N signal is set low, the Y counter CT62 will increment by one count as described below.

Referring to Figures 21j and 32, the Y Decode 4 Plus N signal is set low at approximately the same time as T1, which is when the Y Strobe N signal goes low. This Y-STROBE N low signal is applied to the input of an inverter I67D, which inverts this signal to a positive signal at its output, which remains HIGH until the Y-STROBE N signal returns to high at time T3. be.

The inverted signal from the output of inverter I67D is delayed by delay circuit 586, and this delayed signal is
Noah Gate NO (shown as NO104B(2) in Figure 2)
Appears on input 2 of 104B.

As shown, this delayed signal goes high at time T2;
Returns to low at time T4. Between times T1 and T2, both inputs of NOR gate NO 104B are low, and the output of this gate is high until time T2, when T
At 2, this output returns to low because at this time the delayed signal at input 2 of gate NO 104B goes high. Noah Gate No. 104 at time T4
The delayed signal at input 2 of B goes low again, so two low signals are generated at the input of this gate. Therefore, the output of gate NO 104B goes high again at time T4. In this manner, differentiator circuit 588 generates positive pulses at both times T1 and T4 when the output of gate NO 104B is high. These positive pulses are inverted by NOR gate NO104C, inverter I67E, and NOR gate NO104D, and at times T1 and T4
A narrow low pulse is formed at pin 2 of the Y counter CT62. When a low pulse is formed on pin 2 of this counter at time T1, the Y strobe N signal is still low and, as stated earlier, pin 9 of counter CT62
The low signal only puts information into this counter. However, when a second low pulse appears at pin 2 of counter CT62 at time T4, the Y strobe N signal has already returned to the high state at pin 9 of this counter. Therefore, this second low pulse is at pin 2 of this counter.
Increments the information already entered in the Y counter by one count in response to the rising edge of the pulse.

The operation of this counter when inputting A data N, B data N, C data N, and D data N signals to the X counter CT61 in response to the X strobe N signal is to input information from the data N signal to the Y counter CT62. It's very similar to what I said in connection with. The information thus entered is also incremented by one count in response to the low state of the X decode 4 plus N signal in the same manner as described in connection with Y counter CT62.

When the X strobe N signal goes low, the X data word has already been formed as a data N signal. The X strobe N signal is inverted by inverter I52E, and when the output of this inverter goes high, differentiator circuit 590 generates a positive pulse, creating a narrow low pulse at the output of NOR gate NO80C. X counter C
Since the pin 9 input of T61 is low, the positive edge of this low pulse causes information from the Data N signal to be placed into this counter. Also, this information is A
It is an inverted form with low order bits corresponding to the data N signal. If the decoded X data instructs the X step motor to move more than 4 pulses, then
The plus N signal remains high during the memory cycle, inhibiting gate NO80B, and X counter CT61 does not increment.

However, if the X step motor is driven with four or more pulses, the X decoder 4 plus N signal will be low. Therefore, X decode 4 plus N signal and NOR gate N
The delay signal formed by delay circuit 592 of input 2 of O80B forms two narrow low pulses at the output of NOR gate NO80C and pin 2 of X counter CT61. The first low pulse occurs while the X STROBE N signal is low, so this counter does not increment at this time. However, after the X strobe N signal went high, i.e. the single shot circuit SS63A was again triggered by the third pulse of the clock pulse signal and entered the counter CT61 as described in connection with the Y counter CT62. A second low pulse is generated when the information increases by one count. Therefore, the X counter data is modified according to changes in the pulse train to the X step motor.

The third pulse train of clock pulses during a memory cycle.
When receiving the EMC-P high signal in response to the pulse of , the control word has already been formed as an A data N, B data N, C data N, D data N signal. As shown in Figure 21j, the data N signal is applied to a register R47 consisting of four D type flip-flops. The EMC-P signal is applied to register R47, and when this signal goes high, the A Data N, B Data N, C Data N, and D Data N signals are decoded by the register at its output as described below. .

Looking back, when the Y strobe N signal later goes low in response to the first pulse of the clock pulse signal,
Information from the bit Y data word is entered into Y counter CT62. When the X strobe N signal later goes low upon receiving the next pulse of this clock pulse signal, information from the X data word is placed into the X counter CT61. In either case, the information placed in the X and Y counters is incremented by one when either or both of the X Decode 4 Plus N or Y Decode 4 Plus N signals go low.

Finally, after receiving the third pulse of the train of clock pulses during the memory cycle, the information from the control word is
for the purpose of setting the direction of the step motor of
It is also decoded by register R47 to indicate the particular mode or instruction it contains.

The A Data N, B Data N, C Data N, and D Data N signals are also decoded for use in controlling the pulse trains issued to the X and Y step motors. Although the specific nature of the pulse train is based on the number of pulses involved, it is generally desirable to start and stop both the X and Y step motors at slow speeds to prevent unwanted vibrations of the motors. . Both the X and Y information from the X and Y data words are decoded for use in performing this pulse smoothing as follows.

Since the X and Y data words each contain 4 bits, there are 16 possible binary numbers for each data word, as shown in FIG. X
If it is desired to output one pulse to the stepper motor, the PROM encoded X data word has a binary value of 0001, as shown. Similarly, Y
If it is desired to output 15 pulses to the step motor, the Y data word is 1111 binary. The corresponding inversion of the X or Y data formed as the A data N, B data N, C data N, D data N signals is also shown in the drawing. As shown, the data N signals of the above example of 1 pulse and 15 pulses are each 1110,000
It represents the inverted binary number of 0 and is the complement of 1. The inverted data N signal is decoded to form a signal that is used to form a pulse train to the stepper motor, as described below.

As shown in FIG. 21i, A data N, B data N, C
Data N, D The current state of the data N signal is AND gate A
49B, Noah Gate NO39B, Nand Gate NA66
Logic is taken at the inputs of B, NA66C and inverters I64B and I64C. As can be seen from Figure 33,
If the X data or Y data contains four or more pulses, one or both of the corresponding signals of C data N and D data N are low or 0. Conversely, if the number of pulses encoded in the data word is less than four, both the C data N and D data N signals are high or one.

When a Y data word is encoded to drive the Y step motor with four or more pulses, the corresponding data N
The signal is decoded as follows.

Since one or both of the C Data N or D Data N signals are low, the output of AND gate A49B is also low. Therefore, input 9 of Noah Gate NO14A
And input 5 of Noah gate NO14D is low.

The output of AND gate A49B is AND gate A
Since it is also supplied to input 4 of 49C, the Noah gate N
Input 9 of O39C is also low. Gate A49B
The low output of is also formed at input 5 of NAND gate NA66B and input 11 of NAND gate NA66C, so the outputs of both NAND gates are high. Input 11 of Noah gate NO26C and input 9 of Noah gate NO26D are gate NA6.
Since both inputs of 6C's output NA49A are high, its output is low.

In this way, since NOR gate NO39C has two low inputs, input 11 of NOR gate NO14B and input 5 of NOR gate NO26A become high. The low output from NAND gate NA49A is inverted by inverter I64A such that input 2 of NOR gate NO14C and input 3 of NOR gate NO26B are both high. Therefore,
Among the Noah gates on chips 594 and 596, gate N
Only O14A and NO14D have low input from the signal.

As mentioned earlier, after the formation of the data N signal for the Y data word, the Y strobe N signal goes low, so the differentiating circuit 520
One pulse is generated by .

This positive pulse is inverted by inverter I50D, so that input 12 of gate NO14B and gate NO
A low pulse is generated at input 6 of gate 14D, input 2 of gate NO 26B, and input 8 of gate NO 26D. The other input of these gates is formed before the Y STROBE N signal goes low and before the pulse is generated by circuit 520. Since input 11 of gate NO 14B, input 3 of gate NO 26B, and input 9 of gate NO 26D are all high, the outputs of these gates will remain low even if a low pulse is accepted at the other input.

However, since input 5 of NOR gate NO14D is low, when a low pulse enters input 6 of this gate, a positive pulse is formed at its output which sets flip-flop ff4B, thus setting the Y decode 4 plus N signal low. do. As previously discussed in connection with Figure 21j, this state of the Y Decode 4 Plus N signal causes the Y counter to increment by one count when the Y Strobe N signal returns high.

Thus, receiving the Y Strobe N signal during the first portion of the memory cycle in response to the first clock pulse being accepted causes the Y Decode 4 Plus N signal to be set low. The remaining outputs of the flip-flops on chips 598, 600, 602, and 604 are high at this time because they are reset by the memory cycle enable P signal at the start of the memory cycle and the - The gates on chips 594 and 596 that are strobed such that the input is in the low state and the other input has a low pulse are connected to gate NO1.
This is because it was 4D.

The X data word is formed as the data N signal after being pulsed by differentiator circuit 518 during the second phase of the memory cycle. If the X data word is programmed to drive the X step motor with more than four pulses, the corresponding data N signal is decoded as follows. After the data N signals are formed, these signals are decoded as signals for the gates on chips 594 and 596 in the same manner as described above. In this way, input 9 of gate NO14A and input 5 of gate NO14D are in a low state, and input 11 of negative gate NO14B is in a low state.
, input 2 of gate NO14C, gate NO26A
Input 5 of gate NO26B, input 3 of gate NO26C, input 11 of gate NO26C, and input 9 of gate NO26D are in the low state.

When the X STROBE N signal goes low, differentiator circuit 518 generates a positive pulse that is inverted by inverter I50B. Therefore, a low pulse appears at input 8 of gate NO14A, input 3 of gate NO14C, input 6 of gate NO26A, and input 12 of gate NO26C. Since input 9 of gate NO14A is low, a positive pulse is formed at the output of this gate, which sets flip-flop ff3A such that its output signal Xdecode4 plus N is set low. The outputs of the remaining gates of chips 594, 596 remain low at this time, and the other flip-flops on chips 598, 600, 602, 604 are connected to the X strobe N in this case where the X data word contains four or more pulses. It is never set in response to a signal. As previously stated in connection with FIG. 21j, this low signal X decode 4 plus N causes the X counter CT61 to increase by one count.

In retrospect, the Y Decode 4 Plus N signal is set low in response to four or more pulses programmed into the Y data word, and similarly the four or more pulses in the X data word are decoded. If so, the X decode 4 plus N signal goes low. It should be noted that for convenience, the states of the four or more pulses of both data words are listed together.

However, if either or both of these data words contain a count less than 4, the settings of the Y decode A plus N and X decode 4 plus N signals are mutually independent and dependent on the respective data word.

As stated above in connection with FIG. 33, if an X or Y data word is encoded with counts or pulses less than 4,
C data N and D formed in response to X and Y data words
Both signals with data N are 1 or high. As shown in FIG. 21i, since the C data N and D data N signals are high, the output of AND gate A49B is also high, and input 9 of NOR gate NO14A and input 5 of NOR gate NO14D are both high. Therefore, when receiving low signals Y strobe N and X strobe N, the outputs of gates NO14A and NO14D remain low, and flip-flops ff3A and ff4B
is not set, Y decode 4 plus N, Xf
The code 4 plus N signal remains high. In this way, if the Y data word is less than 4, the Y Decode A Plus N signal will never be set low. Therefore,
If the corresponding X and Y data words are greater than or equal to four counts, or even equal, the Y Decode 4 Plus N and X Decode 4 Plus N signals are set low. At this time, the possible states of the C data N and D data N signals have already been described, and both signals are in the high state for the duration described below, for counts less than four of the data words.

Also, in this case, since the output of AND gate A49B is high, input 4 of AND gate A49C is high.
, input 5 of NAND gate NA66B, and input 11 of NAND gate NA66C are high.

Next, assume that a zero count is encoded into an X or Y data word. As shown in FIG. 33, the A data N or B data N signals formed from this data word are both high. Referring to Figure 21i, Noah Gate No. 39
B's input is high, so AND gate A49
Input 5 of C is low, Noah gate NO39C
Input 9 is also low. Since the input of inverter I64B from the B data N signal is high, the inverted signal at input 4 of NAND gate NA66B is low and the output of this gate is high. Similarly,
The input of inverter I64C is high and the output of this inverter, which appears at input 9 of NAND gate NA66C, is low, so the output of this gate is high. It can be seen that input 11 of NOR gate NO26C and input 9 of NOR gate NO26D are both high. Also, since both inputs of NAND gate NA49A are high, the output of this gate is low. Since both inputs of NOR gate NO39C are low, the signals at input 11 of NOR gate NO14B and input 5 of NOR gate NO26A are both high. Since the low signal from gate NA49A is inverted by inverter I64A, input 2 of NOR gate NO14C and input 3 of NOR gate NO26B go high. As mentioned before, input 9 of Noah Gate NO14A and Noah Gate NO1
4D input 5 is also high. In this way, when the corresponding X or Y data word has a zero count, chip 5
All Noah gates on 94,596 have high innovations.

When the corresponding Y Strobe N or
None of the flip-flops on 04 are set. Since these flip-flops are already reset during the initialization of the memory cycle by the memory cycle enable P signal, the corresponding r of these flip-flops is
None of the outputs are set low. Thus, if the Y data word is 0, then the Ya pulse inhibit N, Yc pulse inhibit N, Y from these flip-flops.
The b pulse inhibit N and Y decode 4 pulse N signals remain high. Similarly, if the X data word represents a 0 pulse, the Xa Pulse Inhibit N, Xb Pulse Inhibit N, Xc Pulse Inhibit N, and X Decode 4 Plus N signals all remain high.

The next situation is when the X or Y data word has one count such that the formed A data N signal is low and the B data N signal is high, as shown in FIG. This is the case. In this case, since input 2 of NOR gate NO39B is high, a low signal is generated at input 5 of AND gate A49C. Therefore, Noah Gate NO39C
Input 9 is also low. Since the input of inverter I64B is high, input 4 of NAND gate NA66B is low and the output of this gate is high. The low input of inverter I64C is inverted to a high state at input 9 of NAND gate NA66C. Input 10 of NAND gate NA66C is B data.
This is also high since the TA N signal is provided. Input 11 of NAND gate NA66C is AND gate A49
Since it is connected to the high input of B, it is also high, which is caused by the high states of the C data N and D data N signals. All inputs of NAND gate NA66C are high, so its output is low. Thus, input 11 of NOR gate NO26C is low and input 9 of NOR gate NO26D is also low. Since input 13 of NAND gate NA49A is low, its output is high. Since input 8 of Noah Gate NO39C is high, its output is low, so input 11 of Noah Gate NO14B and Noah Gate NO
A low signal is produced at input 5 of 26A. High output from NAND gate NA49A is inverter I
64A, a low signal is produced at input 2 of NOR gate NO14C and input 3 of NOR gate NO26B.

Therefore, all the above inputs of the Noah gates on chips 594, 596 are low, except that gate NO1
4A input 9 and gate NO 14D input 5
It's high. If the gates in this state on chips 594 and 596 indicate a Y data word when receiving the low signal of Y strobe N, flip-flops ff27B and ff1
5B and ff3B are set. In this way, YA
Pulse prohibition N, YB pulse prohibition N, and YC pulse prohibition N
signal is set low. If the gates in this state on chips 594 and 596 receive the X strobe N low signal and represent N data words, flip-flop ff27A
, ff15A, and ff4A are set. Therefore, at this time, the XA pulse inhibit N, XB pulse inhibit N, and XC pulse N signals are set low.

In this way, when a Y data word has one count,
Flip-flop f with Y decode 4 plus N signals
All Y-pulse inhibit flip-flops are set except f4B. Similarly, all X pulse inhibit flip-flops are set except flip-flop ff3A which has an X decode 4 plus N output signal when the X data word represents one count. The states of the inhibit signals from these flip-flops corresponding to one pulse of an X or Y data word are shown in the right-hand portion of FIG.

Now assume that either the X data or the Y data word contains two counts. As shown in FIG. 33, in this case the corresponding A data N signal is high and the B data N signal is low. Since input 3 of NOR gate NO39B is high, input 5 of AND gate A49C is low, and input 9 of NOR gate NO39C is also low.

Since the input of inverter I64B is low, input 4 of NAND gate NA66E is high. Also, input 3 of NAND gate NA66B is A data N.
It is high because the signal is supplied.

As stated earlier, input 5 of NAND gate NA66B is also high because it is connected to the output of AND gate A49B, which has inputs supplied with high signals of C data N and D data N. Therefore,
The output of NAND gate NA66B appearing at input 12 of NAND gate NA49A is low. Thus, the output of gate NA49A is high and the output of NOR gate NO39C is low.

Therefore, input 11 of NOR gate NO14B and input 5 of NOR gate NO26A are both low. The high signal from NAND gate NA49A is sent to inverter I64.
Since it is inverted by A, input 2 of NOR gate NO14C and input 3 of NOR gate NO26B become low. Nand Gate NA66C input 10
Since is low, the output of this gate is high, and input 11 of NOR gate NO26C and input 9 of NOR gate NO26D are both high. Corresponding to the Y data word, when the Y strobe N signal goes low, flip-flops ff15B and ff3B are set. In this way, as shown in FIG. 33,
The YB Pulse Inhibit N and YC Pulse Inhibit N signals are set low. For X data words, when the X strobe N signal goes low, flip-flops ff4A, ff15
A is set. In this way, at this time, only the XB pulse inhibit N and XC pulse inhibit N signals are set to low as shown in FIG. The remaining outputs of the flip-flops reset at the start of the memory cycle by the memory cycle enable P signal remain high.

Finally, we will discuss the case where the data word of X or Y includes 3 counts. As shown in FIG. 33, the resulting signals A data N and B data N are both low or 0. Referring to Figure 21i, NAND gate NA66B
Since both input 3 of the NAND gate NA66C and input 10 of the NAND gate NA66C are low, a high signal is generated at the output of both of these gates. In this way, input 11 of NOR gate NO26C and input 9 of NOR gate NO26D are both high. Nand Gate NA49
Both inputs of A are high, so its output is low. This low signal is inverted by inverter I64A, and both input 2 of NOR gate NO14C and input 3 of NOR gate NO26B become high. Also, at this time, input 8 of NOR gate NO39C is low, so its output is high. As mentioned above, the input of AND gate A49B is supplied with the C data N and D data N high signals, so its output is high. Thus, the output of ant gate A49C is high, resulting in a low signal at the output of NOR gate NO39C. Therefore, input 11 of NOR gate NO14B and input 5 of NOR gate NO26A are both low.

In the case of a Y data word, when the Y strobe N signal goes low, only flip-flop ff3B is set, so Y
The C-pulse prohibition N signal becomes low. Similarly, when the gates on chips 594 and 596 are adjusted for the X data word and then the Y strobe N signal goes low, only flip-flop ff15A is set, causing the XC pulse inhibit N signal to go low. As I said before,
All flip-flops are reset by the memory cycle enable P signal at the start of a memory cycle; the other outputs of the X or Y pulse-inhibited flip-flops remain high.

In this respect, X
and Y pulse inhibit flip-flop states. As mentioned before, the prohibited flip-flop ff3A, ff
4A, ff4B, ff15A, ff15B, ff27A
, ff27B, is determined from the data word by reference to the inhibit signals listed in FIG.

During the third phase of the memory cycle, the control word from the PROM in response to the third pulse of the train of clock pulses is
Let us recall that the inverted signals are formed as A data N, B data N, C data N, and D data N. 30th
Referring to the figure, this control word is formed as a data N signal as follows. A data N signal in low state is +Y
The low order bit specifying the direction of the Y step motor is inverted so that the high signal indicates the -Y direction. Similarly, if the B Data N signal is high, it specifies the -X direction of the X step motor, and the low state of B Data N indicates the +X direction of this step motor. The two high order bits for the mode code are inverted as the C data N and D data N signals. In this way, if both the C data N and D data N signals are high, the stop sewing mode is commanded. If the C Data N signal is low and the D Data N signal is high, the sewing mode is programmed into the control word. C data N signal is high and D
If the Data N signal is low, the slow sewing mode is commanded, and if both Data N signals are low, the program end mode is selected.

As previously discussed in connection with FIG. 21j, the data N signal is decoded by circuit R47 in response to the leading edge of the EMC-P high signal. If the stop sewing mode is commanded by a control word, as represented by the inverted signals of C data N and D data N, the following state is formed at the output of register R47. That is, output 14 is low and output 16 is high, output 1 is low and output 15 is high. Thus, input 1 of NAND gate NA35A and input 4 of NAND gate NA35B are both low, and the outputs of both gates are high. Therefore, input 12 of Noah Gate NO36A and Noah Gate N
Both inputs B of O36B are high. Also, since input 12 of NAND gate NA35D is low and its output is high, a high signal is generated at input 3 of NAND gate NO36D. But Nand Gate N
Since inputs 9 and 10 of A35C are both high, input 6 of NOR gate NO36C becomes low.

As previously stated, the normal state of the EMC-P signal is low so that the output of inverter I52C is high. Therefore, the outputs of the four NOR gates on chip 606 are normally low. However, E.M.C.
When the -P signal goes high and the output of inverter I52C goes low, input 11 of NOR gate NO36A, input 9 of NOR gate NO36B, input 5 of NOR gate NO36C, and input of NOR gate NO36D are output.
A low signal is formed at input 2. EMC-P
When the signal goes high, the data N signal is decoded by register R47, and the NOR gate on chip 606 is set to EMC-- before the single-shot circuit SS63B times out.
The P signal is modulated by the EMC-P pulse before returning low. In the case described here, Noah Gate N
O36C input 6 is set low and EM
Before the C-P signal returns to the low state, NOR gate NO36
Since input 6 of C is in the low state and the signal of input 5 is still low, a positive pulse is formed at the output of this gate as the stop stitch P signal. Chip 606
Since one of the inputs of the remaining gates above is high, its outputs, sewing P, program end P, and low speed sewing P, remain low. The stop stitch P pulse is used to set the control system in the stop stitch mode, as will be seen below.

Next, it is assumed that the C data N and D data N signals indicate that a low speed sewing command for the sewing machine is programmed into the control word. As a result, the state of the output of register R47 when set by the leading edge of high pulse EMC-P is as follows. That is, output 14 is high, output 16 is high, output 1 is low, and output 15 is low. In this way, input 5 of NAND gate NA35B, NAND gate NA35
Since input 10 of C and inputs 12 and 13 of NAND gate NA35D are all low, the output signals from these gates are high. Noah Gate No.
It is found that input 8 of No. 36B, input 6 of Noa gate No. 36C, and input 3 of Noa gate No. 36D are all high, and these gates are prohibited and their output signals program end P, stop sewing P, and low speed sewing P become low. . However, Nand Gate NA35A
Since both inputs are high, Noah Gate NO36A
A low signal is generated at the input 12 of the EMC-P signal, which generates a positive pulse for the stitch P signal before the EMC-P signal goes low.

This sewing P pulse causes the sewing mode of the control system and the sewing machine to be established as described below.

Next, the C data N and D data N signals represent low speed commands,
Therefore, the output state of register R47 is as follows: outputs 14 and 16 are low and output 1 is low.
, 15 are high.

In this way, inputs 1 and 2 of NAND gate NA35A are both low, input 4 of NAND gate NA35B is low, and input of NAND gate NA35C is low.
Since the input 9 of the gate is low, the output signals of these three gates are high.

Therefore, input 12 of Noah Gate No. 36A, input 8 of Noah Gate No. 36B, and input of Noah Gate No. 36.
Since the inputs 6 of C are all high, the signals for sewing P, program end P, and stop sewing P become low. However, since both inputs of NAND gate NA35D are high, a low signal is generated at input 3 of NAND gate NO36D, and a high pulse of the low-speed sewing P signal is generated, and at this time, the control system enters low-speed sewing mode as detailed below. .

Finally, assume that the C data N and D data N signals represent a control word program termination instruction. The result register R
The output status of 47 is as follows. That is, output 14,1 is high and output 16,1 is high.
15 is low. You can do it like this, Nand Gate NA
35A input 2 is low and NAND gate NA
Since inputs 9 and 10 of NAND gate NA35D are low and input 13 of NAND gate NA35D is also low, the output signals of these three gates are high. Therefore, since input 12 of Noah gate NO36A, input 6 of Noah gate NO36C, and input 3 of Noah gate NO36D are all high, sewing P, stop sewing P,
The low speed sewing P signal becomes low. However, since the input of NAND gate NA35B is high, a low signal is generated at input 8 of NAND gate NO36B, and positive pulse information for the program end P signal is generated. In response, the control system enters a program termination mode as seen below.

The A data N and B data N signals are also decoded by register R47 in response to the EMC-P pulse to determine the XPROM direction P used to control the direction of the X and Y step motors.
and a YPROM direction P signal is formed.

As shown in Figure 21e, the X prom direction P signal is applied to input 1 of AND gate A 133A. The other input 2 of this gate is supplied with the basic home N signal which is now high. Thus, if the X-prom direction P signal is high, input 5 of NOR gate No. 134C is also high, and if the X-prom direction P signal is low, input 5 of gate No. 134C is low.

Input 3 of AND gate A133B is supplied with the basic home P signal, which is low at this time. In this way, Noah Gate No. 134C inputs X to its input 5.
The signal is inverted as the X direction signal used to control the direction of the step motor.

The YPROM direction P signal is very similar in use.

As shown, this signal is fed to input 5 of AND gate A133C, and the other inputs are fed to basic home N.
A high signal is provided. Since input 7 of AND gate A133D is supplied with the basic home p low signal, a low signal is generated at input 8 of NOR gate NO 134D. Therefore, the YPROM direction P signal is the NOR gate NO13.
4D to form the Y direction signal used to control the direction of the Y step motor.

As previously mentioned, register R47 comprises any suitable device for decoding the D data N signal, such as four D type flip-flops of the type described in connection with FIG. 21e. As shown in FIG. 21n, the output of this flip-flop is such that when the EMC-P signal goes high, the C input of each flip-flop represents the corresponding D input.
Supply EMC-P signal to LK input. The first flip-flop ff120A has its D input supplied with the C data N signal. Its Q output is used as output 14 of register R47, and its Q bar output is used as output 15 of register R47. The second flip-flop ff120B has a D input to which the D data N signal is applied, its Q output is used as output 1 of register R47, and its Q bar output is used as output 16 of this register. In other words, the flip-flops ff120A and ff120B are EMC-P.
When the signal goes high, it is used to decode the C data N and D data N signals as described above.

Similarly, the A data N and B data N signals are supplied to the D inputs of flip-flops ff120C and ff120D, respectively, and their Q outputs and Q bar outputs are used to control the directional relationship of the X and Y direction signals and the control for the step motor. YPRO based on the corresponding direction information of the word
It is used as the M direction P signal and the XPROM direction P signal.

The most common mode code used as a control word during operation of a sewing machine is a sewing command for high-speed operation of the sewing machine, so the corresponding sewing mode is written first. Let us recall that in response to this command, a positive pulse is generated as the sewing P signal. As shown in FIG. 21g, the X strobe N signal is inverted by inverter I41A, and this inverted signal is applied to input 6 of flip-flop ff57A.

Since the XSTROBEN signal is normally high, the flip-flop's inverse signal is low. When the XSTROBE N signal momentarily goes low before decoding the control word, the inverted high signal resets the flip-flop so that its output stitch 1P is low and stitch OP is high. Thereafter, the sewing P pulse passes through the OR gate O43C and enters the input 2 of the flip-flop ff57A, thereby setting this flip-flop. As mentioned before, orgate O
When the low speed sewing P signal of the other input of 43C is present, it is low. The output of flip-flop ff57A is set as follows: the stitch 1P signal is set high and the stitch OP signal is set low.

Referring to Figure 21e, Noah Gate NO44D
If any of the inputs of is high, the output of this gate is low. As mentioned before, NT
The normal state of the B-mode OP signal is high, so input 2 of AND gate A70D is normally low;
Input 4 of Nando Date No. 70C is also normally low. Therefore, the auxiliary start P signal at the output of AND gate 70D is normally low. The normally normal state of the Cond-Go P signal is high, and as long as both inputs of the NOR gate are low, the auxiliary start P signal and input 4 of NAND gate NA70C are high.

Assuming normal conditions, input 4 of AND gate NA70C is low, so input 9 of NAND gate NA70B is high. When the sewing P positive pulse is received, this pulse is inverted by the inverter I83D, and a low pulse is formed at the input 10 of the NAND gate NA70B. Therefore, a high pulse is formed at the output of the NAND gate NA70B, so that the flip-flop ff
Set input 2 of 84A and its output 1
is set low and its output 4 is set high, thus providing a high state of the sewing mode P signal indicating that the control system is in sewing mode.

The sewing flip-flop ff84A is reset by the reset signal during initialization, its output 1 is set to high, and the sewing mode P signal is set to low. When the sewing flip-flop is set, its input 6 is low, which is determined as follows. Low speed sewing P supplied to input of Noah gate NO44C
Since both the signal and the program end P signal are low, input 13 of NAND gate NA70A goes high.

Referring to Figure 21h, the NTB mode OP signal is normally high and goes low only in the event of a thread break as measured by the thread break sensor. Therefore, the NTB mode P signal at the output of inverter I19E is normally low. When the thread breakage sensor detects thread breakage and the NTB mode OP signal becomes low, the NTB mode P signal becomes high. At this time, the differentiator circuit 610 of FIG. 21e generates a positive pulse as the NTB mode pulse N signal at the input of the inverter I83C, so a low pulse is generated at the input 12 of the NAND gate, and therefore a YES pulse is generated at the input 6 of the flip-flop ff84A. Reset the flip-flop. If there is no thread breakage, inverter I8
Since the state of the signal at the input of 3C is low, the input 12 of the NAND gate NA70A becomes high.

Therefore, the output of gate NA70A and the input 6 to flip-flop ff84A are normally low.

After sewing flip-flop ff84A is set in response to sewing P pulse, input 12 is input to OR gate O84B.
A low signal is established. As mentioned earlier, the clamp mode OP signal is set low before entering homing mode, so input 1 of drive circuit DC72A is
is low. As shown in Figure 21m, if the normal-repair selection switch is set to its normal terminal, the normal-repair selection signal and input 2 of drive circuit DC72A
are low, and if this switch is set to the repair terminal, these signals are high. Therefore, if the switch is set to the normal side during normal operation of the sewing machine,
Both inputs of drive circuit D1C72A are low.

Output 3 of drive circuit DC72A is related to the output of this circuit as follows. If either input is high, the output of the drive circuit is also high, causing the sewing machine to operate at low speed. vice versa,
If both inputs of drive circuit DC72A are low, then
The output of this drive circuit is also low, thus causing the sewing machine to run at high speed. Therefore, during normal operation of the sewing machine, when receiving a sewing P pulse, both inputs to drive circuit DC72 are low and its output is low, resulting in the following conditions. The tri-attack activation relay is closed, energizing the main brake/clutch solenoid of the quick-release device. Recall, with reference to FIG. 17, that when the solenoid is energized, it forces disc A30 against the clutch surface of flywheel 422 so that the sewing machine is driven at high speed. When flip-flop ff84A is set to lock mode, the normal-repair selection switch is set to the normal terminal and the clamp mode OP signal remains high, and the brake/clutch solenoid is disabled until this flip-flop is reset. The needle remains energized and moves back and forth at high speed as long as it receives sewing commands from Prom.

Since the sewing flip-flop is reset by reset N before receiving the first pulse of the sewing P signal during initialization, input 1 of the drive circuit DD72A is high, and the main brake/clutch solenoid of the quick device is deenergized. Monkey. Therefore, at this time, the disk A30 comes into pressure contact with the main braking surface 434 of the worm wheel 432. This condition is maintained even if the normal-repair selection switch is set to the repair side terminal or receives a pulse from the slow stitch P signal or the program end P signal, as will be seen below.

A high state of either the NTB mode P or clamp mode OP signal produces the same result. In either case, at least one input of drive circuit DC72A is in a high state.

Whether the quick drive disk 446 is pressed against the auxiliary clutch surface 448 or the auxiliary brake surface 450 is based on the sewing machine speed and the state of the output signal from the drive circuit DC88B of FIG. 21g. If the quick device detects that the sewing machine is running at low speed, the synchronization unit 62
, then the auxiliary brake is engaged unless proper conditions are established at the output of the drive circuit DC88C.

Satisfying this condition will be described later. At this point the 21st
The main brake/clutch solenoid in figure e is the drive circuit DC.
Suffice it to say that when this solenoid is energized by solenoid 72A, the machine runs at high speed, ie, during the sewing mode, and when this solenoid is deenergized, the machine runs at low speed or stops.

As shown in FIG. 21g, when the sewing P positive pulse sets flip-flop ff39B and its output 1 goes low, input 4 of AND gate A42A goes low and input 8 of flip-flop ff57B goes low; Time is not set. In addition, the sewing P pulse is inverted and passes through the NOR gate NO53A, and the low pulse generated at this time is the low-speed sewing flip-flop ff if the previous command has caused the low-speed sewing mode.
Reset 54C. The flip-flop is reset so that its output 3 is high and its output 6 is low. Therefore, input 8 of OR gate O53C is high, and input 1 of drive circuit DC88 is also high.

The drive circuit DC88B operates as follows. If both inputs of this drive circuit are high, its output signal, the high/low speed sewing command, is high, and if either input is low, this signal is also low. Referring to FIG. 17, the quick device normally operates so that disc 446 presses against auxiliary braking surface 448.

If the quick device uses one signal from the synchronization unit 62 to determine low speed operation of the sewing machine, the quick device automatically initiates the cutting sequence and moves the disc 446 to the auxiliary braking surface unless disturbed. 450 to stop the sewing machine. While the high/low speed sewing command signal is low, the quick device is inhibited from undergoing cut and stop sequences even if the minon is operating at low speed.

If the high/low speed stitch command is high, the quick device will be forced to perform a cut and stop sequence, but will not undergo this sequence unless the quick device has specified from unit 62 that the machine is running at low speed.

If the energization-repair selection switch is at the repair terminal, the main brake clutch solenoid is deenergized and disc 430 is pressed against main brake surface 434, as seen in connection with FIGS. 17, 21c, and 21m. Ru. Figures 21g and 2
Referring to Figure 1m, at this time the normal-repair select signal is high along with input 1 of NAND gate NA42B. When the front panel press switch is closed, the press signal is high and the input 2 of the drive circuit DC88B is
is low because both inputs of NAND gate NA42B are high. Therefore, during repair mode, the high/low speed stitch command signal is low and the quick device is prevented from initiating a cut and stop sequence. Therefore, regardless of commands from the program control word, when the push switch is closed during the repair mode, the sewing machine is under program control but runs at a low speed. This is done because the disc 430 of the quick-release device (FIG. 17) presses against the primary brake surface 434, which prevents the disc 446 from disengaging from the auxiliary clutch surface 448.

If a thread breakage occurs when the high/low speed sewing command signal is high during the sewing mode, the following sequence occurs. Figure 21h and 2
As previously discussed in connection with Figure 1e, flip-flop ff84A is reset in response to the high to low transition of the NTB mode OP signal. At this time, drive circuit D
C72A deenergizes the main brake clutch solenoid and the quick drive disc 430 presses against the braking surface 434 of the worm wheel 432. Therefore, the sewing machine slows down to low speed. When the quick device determines from the synchronization unit 62 that the sewing machine is running at low speed, the quick device starts a cutting sequence and stops the sewing machine because the high/low speed sewing command signal is high, and is not prevented from receiving this sequence. .

In sewing mode, if the normal-repair selection switch is set to the normal side, the normal-repair selection signal is low. Therefore, input 1 of NAND gate NA42B is low along with input 9 of OR gate O53C. In this manner, the output signal from NAND gate NA42B is high, and both inputs of drive circuit DC88B are high, so the high/low speed sewing command signal becomes high. In this manner, if a thread break is detected by the thread break sensor, a cut and stop sequence of the quick release device is initiated during the sewing mode.

As shown in FIG. 21g, flip-flop ff57A
is set as a result of the sewing mode intermediate stitch P pulse,
Input 9 of NOR gate NO44B is set low by a flip-flop. Also, NTB mode P
Since the signal is normally low, input 5 of NAND gate NA55C is high. However, if thread breakage has already been detected by the thread breakage sensor and the NTB mode P signal goes high, input 5 of NAND gate NA55C remains low and the control system does not drive the step mode in this hour stitch mode. is prevented. Nand Gate NA
The Clamp Mode 1P signal at Input 3 of the 55C should be high. However, if the clamp mode 1P signal is low, this condition prevents starting the step motor in the sewing mode. At this time, the NAND gate is in such a state that its inputs 3 and 5 are high signals.

As previously stated, when the optical sensor in unit 62 indicates that the clamp can be moved at time T4 (FIG. 25) of the timing cycle, a positive pulse is formed as the needle drop pulse P signal. At this time, NAND gate NA55C 3
Since all inputs are high, a low pulse is formed at input 10 of NAND gate NA55A. - On the other hand, this NAND gate NA55A inverts this pulse and passes it, so a positive pulse is formed at the input 11 of the NAND gate NO44A. Gate NO44A inverts the pulse again to form a low pulse as the start run N signal, which starts driving the X and Y step motors as described below.

For needle removal, it is determined that the start run N signal is in a high state before receiving the pulse P pulse. At this time, since the basic home N signal is high, the input 9 of the gate NA55A becomes high. When flip-flop ff57A is set by the sewing P pulse, NAND gate NA5
Since a low state is established at input 1 of 5B, a high signal is generated at input 11 of OR gate O43D, and a high signal is generated at input 11 of NAND gate NA55A.

Therefore, all three inputs of NAND gate NA55A are high until receiving the needle drop pulse P pulse, and input 11 of NAND gate NO44A is low until this time. Also, since flip-flop ff39B was reset by the sewing P pulse, AND gate A4
Input 13 of 2A is low, thus producing a low signal at input 12 of NOR gate NO44A. In this way, since both inputs of the NOR gate NO44A are low, the start run N signal remains high until the needle dropout pulse P is received.

The drive of the step motor during sewing mode is described below. Referring to FIG. 21d, when a start run N low pulse is received, this pulse is inverted by inverter I19C to form a positive pulse at input 2 of NOR gate NO 20A and input 5 of NOR gate NO 20B. Therefore, a low pulse is formed at the outputs of NOR gates NO20A and NO20B, so the X and Y flip-flops ff21B and ff32B are set, respectively, and the running N outputs of X and Y are set to low, and the running P outputs of X and Y are set to low. Set high.

The operation of the control system when forming a pulse train for the step motor and moving the flange is the same as described in connection with the homing mode. Referring to Figure 21j, when the X and Y running N signals go low, the X count pulse P and Y count pulse P signals are again formed from the LSOsc-N signal as described above. . Recall that the X and Y count pulse P signals are positive pulse trains. With reference to FIG. 21e, when flip-flop ff45A is reset by the homing clear N signal, L
Recall also that the SShiftN signal is set high. Therefore, the LS shift N high signal, as described in connection with FIG. 21c, creates a relatively fast LS transmitted N signal. The pulse train of X and Y count pulses P is therefore formed at a relatively high rate of 850 pulses/sec.

The relative timing between the pulses of the X and Y count pulse P signals and the pulse train supplied to the step motor is described in connection with FIG. X and Y count pulse P
The pulse train is shown as a clock in the drawing, and the pulses of these signals occur at 1.16 millisecond intervals. The remaining lines show the relative timing of the pulses delivered to the stepper motor based on the number of pulses or counts encoded after the X or Y data. In the case of one or more coded pulses, clock pulse NO1 is used for the step motor each time the timing is the same.

Of course, if no pulse is encoded into an X or Y data word, no pulse will be output to the corresponding stepper motor. If the control word instructs the corresponding step motor to generate two pulses, then the time of the first pulse applied to the step motor corresponds to clock pulse NO1, or this clock pulse NO2 2 milliseconds after this first pulse, pulse A is added to the pulse train for the step motor, and pulse A is added between inhibited clock pulses NO2 and NO3.
occurs. If three pulses are to be formed for the X or Y step motor, clock pulse NO1
is used or clock pulses NO2 and NO3 are inhibited. As shown, pulse A is applied 2.0 milliseconds after the first pulse applied to the step motor;
Pulse B is added 1.8 milliseconds after pulse NO3 and 2.12 milliseconds after pulse A. If four or more pulses are formed for the X or Y step motor, clock pulse NO1 is used as the first pulse for the step motor and clock pulses NO2 and NO3 are inhibited again. Pulse A is applied 20 milliseconds after providing the first pulse to the step motor, and then 1.
At 48 milliseconds clock pulse NO4 is used for the step motor. Assuming that N pulses are programmed into the control word, clock pulse NO5 and subsequent pulses, including clock pulse NO(N-1), are used to form the motor pulse train. However, the clock pulse NO,(N) is prohibited, and the clock pulse NO,(N
-1) Pulse B is formed 1.8 ms later. Finally, 2.2 milliseconds after pulse B, pulse C is added to the motor pulse train.

Therefore, the basic clock speed of 1.16 ms is modified for each case of two or more pulses supplied to the step motor, especially at the beginning and end of the pulse train supplied to the step motor. .

The frequency is decreased at the beginning and end of the pulse train to gradually accelerate and decelerate the stepper motor to improve its operation under open loop control.

The formation of the X and Y combo N pulse train for the X and Y step motor is discussed below with reference to Figure 21k. The first condition is when the number of pulses output to the X or Y step motor is one pulse as determined by the corresponding X or Y data word. As stated in connection with Figures 21i and 33, in the one-pulse state of the Y control word, the Y decode 4 plus N signal is set high, and the YA pulse inhibit N, YB pulse inhibit N, and YC pulse The inhibit signal is set low during memory cycles. Similarly, for one count of the X control word, the X Decode 4 Pulse N signal is set high and the XA Pulse Inhibit N, XB Pulse Inhibit N and XC Pulse Inhibit N are set low. The X and Y signals that control the proper direction of the X and Y step motors are already formed.

Referring to FIGS. 21k and 35, in connection with the homing mode, the X-travel flip-flop is set and when the X-travel P signal goes high, the differentiator circuit 524
generates a positive pulse that sets flip-flop ff16A, causing pin 1 of single shot circuit SS28A to go low. When the first pulse (pulse NO1) of the becomes high.

The relative timing of these signals is shown in FIG.

When single shot circuit SS23A times out and its Q output goes low, single shot circuit SS23A times out and its Q output goes low.
28B is triggered on pin 9. Therefore, the Q output of single shot circuit SS28B becomes high at this time,
The delayed high signal at input 5 of flip-flop ff16A resets this flip-flop so that a high signal is generated at pin 1 of single shot circuit SS28A, inhibiting the single shot circuit. As can be seen from Figure 35,
The Q bar output of the single shot circuit SS28B is high at pulse No. 1 of the X count pulse P.

Therefore, pulse No. 1 is inverted by NAND gate NA5A and is formed as a low pulse at input 10 of NAND gate NA31A. Since the XA Pulse Inhibit N signal is low, a high state is established on pin 1 of single shot circuit SS6A to prevent this circuit from being triggered. Therefore, the Q bar output of this single shot circuit remains high, and the input 11 of NAND gate NA31A is also high. Furthermore, since the XB pulse inhibit N signal is low, input 9 of NAND gate NA31A is also high. In this way, Nand Gate NA31
The output of A is a positive pulse at pulse No. 1n of the X count pulse P signal, and this pulse passes through the OR gate O82C to pin 2 of the single shot circuit SS68A.
trigger. This pulse is generated by the single shot circuit SS68.
One wide low pulse is formed at the Q bar output of the single shot circuit as the X combo N signal which is restarted by A and drives the X step motor one pulse. This low signal of XC pulse prohibition N is the single shot circuit SS6.
8B is inhibited from forming XC pulses.

As shown in FIG. 2ij, the pulse train of the X count pulse P is inverted by the NOR gate NO80C, and this inverted pulse train is formed at pin 2 of the X counter CT61. Each pulse in the pulse train increments the counter by one. The information entered into the X counter from the data N information corresponds to 1 count or 1 pulse, and the inverted binary number of the counter is 11
It is 10.

When the X counter counts once in response to the first pulse of the X count pulse P pulse train, the counter counts to a full count value of 1111, at which time the counter signal X carry P goes from low to high. As shown in FIG. 21e, the X carry-P signal is connected to AND gate A13.
2B input 3. The other input of this AND gate is supplied with the basic home N signal which is now high. Basic home P low signal is AND gate A
Since it is supplied to Impunto 2 of 132A, Noah Gate N
Input 1 of O134A is low. Therefore, the X carry P high signal is
Inverted as the low state of the Stop N signal. As shown in FIG. 21d, the X stop N signal causes the X travel flip-flop f
Reset f21B, its X-travel N output is high and its X-travel P output is low. 21st
As shown in figure j, the X running N low signal inhibits the formation of any further pulses of the X count pulse P pulse train, which signal only contains one pulse in the case in question. Also, the counter CT61 increments the count by one time in response to this single pulse, and the X
Combo N signal is pulse N of X count pulse P pulse train
It contains only one low reoccurring pulse at o1.

Assuming that one pulse is encoded in a Y data word, the operation of the control system operating the Y step motor is the same as described above. The pulse train of Y count pulse P is 21jth
As mentioned in connection with the figure, it starts when the Y travel N signal goes low. Referring to Figure 21k, Y
When the running P signal goes high, flip-flop ff16
B is triggered and arranges the single shot circuit SS40A,
This single shot circuit is triggered by pulse No. 1 of the Y count pulse P signal. At this time, since the Q bar output of the single shot circuit SS40B is high, this pulse No. 1 is inverted by the NAND gate NA29A. YA pulse inhibit N signal is low, so single shot circuit SS30A is inhibited and NAND gate NA31B
input 4 remains high. YA pulse prohibitedN
Since the signal is low, input 3 of NAND gate NA31B is also high. Therefore, Nand Gate NA31B
One low pulse at the input 5 of the circuit is inverted by this gate, and after passing through the first gate O82D, a positive pulse is formed at the input 10 of the single shot circuit SS69A. The small single shot circuit regenerates this pulse s, Y
Form one broad low pulse at its Q bar output as a Y combo N signal that drives the step motor one pulse. This YC pulse inhibit N low signal inhibits single shot circuit SS69B from forming a YC pulse.

As shown in FIG. 21j, the pulse train of the Y count pulse P is inverted by the NOR gate NO104D, and the inverted pulse train is formed at pin 2 of the Y counter CT62. When the Y counter increases by one in response to pulse No. 1 of the CT count pulse P signal, the carry P signal becomes high. Referring to FIG. 21c, ant gate A1
Since the basic home N high signal is supplied to the input 6 of the AND gate A132C, the input 7 of the AND gate A132D is
is low, so the Y Carry P signal fed to input 5 of gate A132C is connected to NOR gate NO134B.
to form a low state in the Y-stop-N signal. Referring to FIG. 21d, the Y Stop N Low signal resets the Y Run flip-flop ff32B so that its Y Run P output is low and its Y Run N output is high. Referring to Figure 21j, the Y run high signal inhibits the Y count pulse P signal. In this way, only one low signal is output to the Y step motor and the Y counter CT62 only increments once.

The states of the two counts or pulses encoded in the X or Y data words are then as follows. Referring to FIG. 33, in this case, for the X data word, the XA inhibit N signal and the X decoder 4 plus N signal are set high, and the XB
The Inhibit N signal and the XC Inhibit N signal are set low. Y
The inhibit flip-flop is set in the same manner as corresponding to the Y data word. As before, when the X and Y run flip-flops are set, the X run N and Y run N outputs are set low and the X count pulse P
and a pulse train of Y count pulses P is started. 21st
Referring to Figures K and 33, when the X running P signal goes high, flip-flop ff16A is set and the signal at pin 1 of single shot circuit SS28A goes low,
The single shot circuit is triggered by pulse No. 1 of the pulse train of X counter pulses P, and at this time the Q output of this single shot circuit goes high. Since the single shot circuit SS28B is not triggered until the single shot circuit SS28A times out, the Q bar output of the single shot circuit SS28B is high at pulse No. 1. Therefore, pulse No. 1 of the X count pulse P signal
is inverted by NAND gate NA5A, forming a low pulse at input 10 of NAND gate NA31A. When single shot circuit SS28A times out and its Q output goes low, single shot circuit SS28A times out and its Q output goes low.
21B is triggered. At this time, the single shot circuit SS
The Q output of 28B goes high and the delayed output signal resets flip-flop ff16A.

The reset flip-flop resets the single shot circuit SS before receiving pulse No. 2 of the X count pulse P signal.
28A to prevent this single shot circuit from triggering again. Also, when single shot circuit SS28B is triggered, its Q bar output goes low. As shown in FIG. 36, the Q bar output of the single shot circuit SS28B is low during pulse No. 2 of the X count pulse P signal.The reason is that this single shot circuit does not time out until after receiving this pulse. This is because it will not happen. Therefore, during this time, the single shot circuit SS28
The signal supplied from B to NAND gate NA5A is low and prevents pulse No. 2 from passing through this NAND gate.

Since the XA inhibit N and LS shift N signals are high,
Single shot circuit SS6A is enabled by a low signal on its input 1. When single shot circuit SS28A is triggered and its Q output goes high, single shot circuit SS6A is triggered and its Q bar output goes low on pulse No. 1 of the X count pulse P signal. The delay in single shot circuit SS6A is such that it times out 2 milliseconds after being triggered, at which time its Q bar output goes high. At this time, the differentiating circuit 526 generates a positive pulse, which is inverted by the inverter I56A to form a low pulse at the input 11 of the NAND gate NA31A. Since the XB pulse inhibit N signal is low, a high signal is formed at input 9 of NAND gate NA31A. In this way, as shown in FIG. 36, the signal formed at the output 8 of the gate N31A is the positive pulse at pulse No. 1 of the X count pulse P signal and the XA after 2 milliseconds of timeout of the single shot circuit SS6A. It consists of a positive pulse. These pulses are regenerated by single shot circuit SS68A and formed into a corresponding pulse train of wide low pulses as the X combo N signal for X step motor control.

At this time, since the XC pulse inhibit N signal is low, the formation of the XC pulse by the single shot circuit SS68B is inhibited. Therefore, as shown in FIG. 36, the first pulse supplied to the X step motor occurs at pulse No. 1 of the X count pulse P signal, and the second pulse occurs between the pulses of the X count pulse P signal. The signal is formed after 2 milliseconds to decrease the frequency.

Referring to FIG. 21j, each pulse of the X-count pulse P signal causes the X-counter CT61 to count one count, and on the second count the inverted data of the counter is increased to the full count value.

It should be noted that the counting of the X counter is synchronized to the formation of the motor pulse train of the X combo by the X count pulse P signal. When the counter increments twice, an X-carry P high signal is generated and the X-carry flip-flop shown in FIG. 21d is reset. On the other hand, the counting of the X counter CT61 is stopped, the pulse train of the X count P is prohibited, and therefore the X direction movement of the X step motor and the clamp is terminated.

The operation of the control system when driving the Y step motor when the Y control word is 2 counts is very similar to that described in connection with the X step motor. Referring to FIG. 21k, pulse No. 1 of the Y count pulse P signal is inverted by the NAND gate NA29A, and this pulse is
When the Y count pulse is pulse No. 1 of the P signal, it is used to form the first regenerating low pulse of the Y combo N signal.

After the Y running P signal becomes high, the single shot circuit SS4
Since 0A is triggered by pulse No. 1, single shot circuit SS30A is triggered because the LS shift N and YA pulse inhibit N signals are high at this time. Single shot circuit SS 2ms after trigger
When the 30A Q bar output times out,
Differentiator circuit 540 generates a positive pulse which is inverted and formed as a low pulse at input 4 of Nant gate NA31B. In this way, 2 milliseconds after pulse No. 1 of the Y count pulse P signal, the single shot circuit SS69A is triggered to form the second low pulse of the Y combo N signal for controlling the Y step motor. 21st
Referring to Figure J, since the Y counter CT62 is counted twice by the inverted signal of the Y count pulse P, a Y carry P high signal is obtained in response to the second pulse. At this time, a low state is obtained on the Y-Stop-N signal, which resets the Y-Run flip-flop. On the other hand, since the pulse train of the Y count pulse P is inhibited, any more pulses for the Y step motor are formed, and the Y counter CT62 is prevented from counting any more.

Next, the three count states of the X or Y control word are described below. In this case, as described in connection with FIG. 33, the XC or YC pulse inhibit N signal is low and -
The corresponding signals of XA or YA Pulse Inhibit N, XB or YB Pulse Inhibit N and X or Y Decode 4 Plus N are high. As before, when the X and Y run flip-flops are set and the X run N and Y run N signals go low, the pulse train of the X count pulse P and the Y count pulse P starts. As shown in FIGS. 21k and 37, when receiving pulse No. 1 of the X count pulse P signal, the Q bar output of the single shot circuit SS28B is high, and this pulse No.
A and formed as a low pulse at input 10 of NAND gate NA31A. The X-running P signal sets flip-flop ff16A, so the single shot circuit SS28A is triggered by pulse No. 1 of the X-count pulse P signal. As before, single shot circuit SS28B is triggered by the Q output of this single shot circuit SS28A when SS28A times out, and single shot circuit SS28B
The delayed Q output of is then single shot circuit SS2
Prevents 8A from being triggered further. As shown in FIG. 37, since the single shot circuit SS28B does not time out until after receiving pulse No. 3 of the X count pulse P signal, the Q bar output of this single shot circuit is between pulses No. 2 and No. 3 of this pulse train. It is low. In this way, single shot circuit SS28B prevents pulses No. 2 and No. 3 from entering NAND gate NA31A through NAND gate NA5A.

As before, single shot circuit SS6A is triggered by the Q output of single shot circuit SS28A when receiving pulse No. 1 of the X count pulse P signal, but this is due to the combination of XA pulse inhibit N and LS shift N. Both signals are high at this time to connect this single shot circuit to its input 1.
This is because it becomes possible when it becomes a low signal. Also, single shot circuit SS6A times out 2 milliseconds after its trigger, and differentiator circuit 526 generates a positive pulse, which is inverted by inverter I56A and X
Two milliseconds after pulse No. 1 of the count pulse P signal, a low pulse is generated at the input 11 of the NAND gate NA31A. As shown in FIGS. 34 and 37, the X formed in the input 11 of the NAND gate NA31A
The A pulse occurs between pulses No. 2 and No. 3 of the prohibited X count pulse P pulse train. Referring to FIG. 21j, as stated earlier, each inverted pulse of the X count pulse signal counts the X counter CT61, and this counter
When the count is increased by 3 by 3, a high state of the X Carry P signal is obtained. On the other hand, since the X-traveling flip-flop is reset as described above, the pulse train of N count pulses P is inhibited.

In connection with FIG. 21d, the X-traveling flip-flop ff2
Recall that when 1B is reset, the X-travel N signal goes from low to high. As shown in FIG. 21k, when the
2 generates a positive pulse at the pin of single shot circuit SS6B. The basic home P signal is low at this time and therefore the homing mode OP signal is also low at pin 9 of single shot circuit SS6B, enabling this single shot circuit. Therefore, a pulse at pin 10 of single shot circuit SS61B will trigger this single shot circuit and its Q bar output will go low on pulse number 3 of the X count pulse P pulse train. This single shot circuit is 1.8 after pulse No.
It is used to form an Xb pulse that occurs 2.12 milliseconds after the XA pulse in milliseconds. Therefore, the single shot circuit SS6B times out 1.8 milliseconds after pulse No. 3 of the X count pulse P pulse train. When single shot circuit SS6B times out and its Q bar output goes high, differentiator circuit 532 outputs NAND gate N.
Generate a positive pulse at input 13 of A5C. At this time, since the Xb pulse inhibit N signal is high, the generated pulse is inverted and formed as a low pulse at the input 9 of the NAND gate NA31A.

Therefore, a positive pulse is formed at the output of the NAND gate NA31A as follows. The first pulse is formed at pulse No. 1 of the X count pulse P signal, the second Xa pulse is formed 2 ms later, and the third Xb pulse is formed 2.12 ms after the value of the Xa pulse. Ru.

As mentioned above, the pulse N of the pulse train of the X count pulse P
o2 and No.3 are prohibited. In this manner, single shot circuit SS68A regenerates these three pulses to form a corresponding low pulse train of regenerated pulses as the X-combo N signal for X-step motor control.

The formation of the Y step motor pulse train when the Y data word is 3 counts is very similar to that described in connection with the X circuit. Referring to FIG. 21k, pulse No. 1 of the Y count pulse P signal is inverted by NAND gate NA29A and used to form the first low pulse of the Y combo N signal at pulse No. 1 of the Y count pulse P signal. I can do it. If the Y running P signal is already high, flip-flop ff16B is set and single shot circuit SS40A is triggered by pulse No.1.

Since the Ya pulse inhibit N and LS shift N signals are both high, the single shot circuit SS30A operates as the single shot circuit SS40 at pulse No. 1 of the Y count pulse P signal.
Triggered by A. Single shot circuit SS30A
times out 2 milliseconds after the trigger, so that the pulse generated by the differentiator circuit 540 causes the regeneration of the Y combo N signal low Ya 2 milliseconds after the first pulse.
A pulse is formed. Referring to FIG. 21j, when the Y count pulse P signal is pulse No. 3, the Y counter C
Since T62 is counted for 3 counts, the Y carry P signal goes high and the Y carry flip-flop is reset. Referring to FIG. 21d, when the Y running flip-flop ff32B is reset, the Y running N signal goes from low to high. As shown in FIG. 21k, the Y running N signal is inverted twice by inverters I7E and I7F, and when the Y running N signal and the output of inverter I7F go high, the differentiating circuit 514 inverts the single shot circuit S.
Generate a positive pulse on pin 2 of S30B. As mentioned before, the homing mode OP signal is low at this time,
A pulse on pin 2 of single shot circuit SS30B triggers this single shot circuit. This single shot circuit is 1.8 ms after pulse No. 3 and 2.12 ms after the formation of Ya pulse.
Set to timeout in milliseconds.

When the single shot circuit times out and its Q bar output goes high, differentiator circuit 542 generates a positive pulse at input 5 of NAND gate NA29D. Since the Yb pulse inhibit N signal is high, this pulse is inverted by the gate NA29D and the NAND gate NA3
It is formed as a low pulse at input 3 of 1B. This pulse triggers the single shot circuit SS69A
2.12 milliseconds after receiving the pulse is used to form the regenerating Yb pulse of the Y Combo N pulse train.

When there are three counts of X or Y data words, the corresponding signals of Xc Pulse Inhibit N and Yc Pulse Inhibit N are both low. Therefore, the corresponding input of pin 10 of single shot circuit SS68B or input 2 of single shot circuit SS69B is low, and the corresponding single shot circuit is
or prohibited due to this state of the data word of Y. Therefore, no Xc or Yc pulse is formed for the corresponding state of 3 counts of X or Y data words, and
Or the corresponding pulse train of Y combo N is completed with an Xb or Yb pulse.

The states of the four or more pulses of the X or Y data word are described below. In this case, as shown in Figure 33,
Decoding X or Y 4 plus the corresponding signal of N is low, while inhibiting the pulse of Xa or Ya N, Xb or Yb
The corresponding signals of Pulse Inhibit N and Xc or Yc Pulse Inhibit N are high regardless of the count of data words greater than three. For convenience, a specific example of 6 counts encoded in the X and Y data words will be mentioned.

As before, the X and Y running flip-flops are set and the pulse train of X count pulse P and Y count pulse P starts when the nail pull pulse P is pulsed. Referring to FIGS. 21k and 38, the Q bar output of single shot circuit SS28B is high when receiving pulse No. 1 of the X count pulse P signal. Therefore,
This pulse No. 1 is inverted by the NAND gate NA5A and is formed as a low pulse at the input 10 of the NAND gate NA31A, so that a high pulse is formed at the output of the gate NA31A. A regenerating low pulse is formed. As mentioned earlier, when the X running P signal goes high, flip-flop ff16A is set, and at this time the single shot circuit SS28A is triggered by pulse No. 1 of the X count pulse P signal. X
The single shot circuit SS28A times out before receiving pulse No. 2 of the count pulse P signal, and the single shot circuit SS28B is triggered at this time. In this way, the Q output of single shot circuit SS28B goes high before receiving pulse No. 2 of the X count pulse P signal, and flip-flop ff16A is reset to inhibit single shot circuit SS28A before receiving pulse No. 2 of the X count pulse P signal. Pulse number of pulse train of X count pulse P
Between No. 3 and No. 4, the single shot circuit SS28B times out, and at this time the Q bar output of the single shot circuit SS28B returns to high. Therefore, Nand Gate NA
5A is pulse No. 2 and No. 3 of the X count pulse P signal
During this time, input 10 of NAND gate NA31A remains high.

Since the Xa pulse inhibit N and LS shift N signals are both high, the signal at pin 1 of the single shot circuit SS6A is low, and this single shot circuit inhibits the Q of the single shot circuit SS28A at pulse No. 1 of the X count pulse P. Triggered by output. As mentioned earlier, the single shot circuit SS remains active until 2 milliseconds after receiving pulse No. 1.
6A does not time out. Single shot circuit SS6
When A times out, its Q bar output goes high and differentiator circuit 526 generates a positive pulse, which is inverted by pulse-side inverter I56A and formed as a low Xa pulse at input 11 of NAND gate NA31A. . In this way, Nand Gate NA31
The Xa pulse of input 11 of A is the X count pulse P
X count pulse P 2 milliseconds after signal pulse No.1
This occurs between inhibition pulses No. 2 and No. 3 of the pulse train.

As can be seen, the single shot circuit SS28B times out between pulses No. 3 and No. 4 of the pulse train of X count pulses P. Therefore, the Q bar output of this single shot circuit becomes high at this time, and pulse No. 4 of the X count pulse P signal and subsequent pulses are inverted to form a low pulse at the input 10 of the NAND gate NA31A. In the particular embodiment at hand, pulses No. 4 and No. 5 of the pulse train of X-currant pulses P are NAND gates N
It is formed as a low pulse at input 10 of A31A.

As can be seen below, the X count pulse P pulse train is inhibited before receiving pulse number 6.

Referring to Figure 21j, if four or more pulses are encoded in the X data word and the X Decode 4 plus N signal is low, the . Therefore, in this case, in order to obtain the X carry P high signal,
One less pulse (for example, 5) than the number of pulses from the count pulse P signal is required. In the particular embodiment in question, if the count of the X data word is 6, then the inverted data placed into the X counter CT61 is initially -6 but incremented by one to become a count of -5.

In this manner, the X-counter CT61 counts to a full register state of all binary ones in response to five pulses of the X-count pulse P signal, rather than the normally expected six counts. Therefore, when the X counter CT61 increases by 5 counts in response to pulse No. 5 of the pulse train of the X count pulse P, the high state of the X carry P signal is obtained, so the X stop N is activated as described above in connection with FIG. The signal goes low and resets the X travel flip-flop ff21B. At this time, the X running N signal from flip-flop ff21B becomes high. As shown in Figure 21f, this signal inhibits the formation of any further pulses of the X count pulse P pulse train and does not receive pulse No. 6 of this pulse train. In this way, the second
Referring to Figure 1k, the last pulse of the pulse train of X count pulses P inverted by NAND gate NA5A is pulse No. 5, and NAND gate NA31A
The last low pulse formed at input 10 corresponds to pulse No. 5 of the X count pulse P pulse train.

However, whether the X traveling flip-flop or the X count pulse P
When the X running N signal becomes high after being reset by the X stop N signal at pulse No. 5 of the pulse train, the differentiating circuit 51
2 generates a positive pulse at pin 10 of single shot circuit SS6B. At this time, since the basic home P signal is low, the signal at pin 9 of single shot circuit SS6B is also low. Therefore, single shot circuit SS6B is triggered by a positive pulse on pin 10 at pulse No. 5 of the X count pulse P signal. This single shot circuit SS6B times out 1.8 milliseconds after triggering, after it would have received pulse No. 6 of the X count pulse P pulse train if it had not been inhibited. When the Q bar output of single shot circuit SS6B goes high, differentiator circuit 532 outputs NAND gate N.
Generate a positive pulse at input 13 of A5C. Since the Xb pulse prohibition N signal is high, the NAND gate NA is activated 1.8 milliseconds after pulse No. 5 of the X count pulse P signal.
A low Xb pulse corresponding to input 9 of 31A is formed.

Therefore, the following positive pulse is formed at output 8 of NAND gate NA31A. That is, the first pulse corresponding to pulse No. 1 of the X count pulse P pulse train, part 2
Xa pulse 2 after milliseconds, that is, while pulses No. 2 and No. 3 of the X count pulse P pulse pulse train are inhibited.
, X count pulse P pulse train pulse No. 4 and No. 5
, and finally the Xb pulse 1.8 milliseconds after pulse No. 5 of the X count pulse P pulse train. All these pulses are formed as positive pulses at input 2 of the single shot circuit SS68A and trigger this single shot circuit.

The single shot circuit regenerates the pulses and turns them into broad low pulses as the X combo N signal for controlling the X step motor.

As mentioned above, when single shot circuit SS61B times out and its Q bar output goes high,
Differentiator circuit 532 generates a positive pulse, and this positive pulse is
A low Xb pulse is generated at the output of NAND gate NA5C. As shown, this low pulse is also formed at pin 9 of single shot circuit SS68B. At this time, the basic home N signal is high together with the Xc pulse inhibit N signal, so input 10 of the single shot circuit SS68B is high.
As mentioned above, a high signal appears on the output signal to enable this single shot circuit. Therefore, a low pulse on pin 9 of single shot circuit SS68B triggers the single shot circuit. This single shot circuit is adapted to undergo a trigger word delay of 2.2 milliseconds. As the single shot circuit times out and its Q bar output goes high, the differentiator circuit 534 generates an Xc positive pulse,
This pulse passes through OR gate O82C and triggers pin 2 of single shot circuit SS68A. Therefore, this pulse is modified by this single shot circuit, and the low wide Xc pulse becomes
This becomes the X combo N signal for the step motor. At this time, six pulses are transmitted to the X step motor, completing the formation of the X combo N signal.

Looking back, the X combo N pulse train for the X step motor is formed as follows. Assuming an N count is programmed into the X data word and N is greater than 3, the next timing will form a pulse for the X step motor. The first pulse is formed for the X combo N signal at pulse No. 1 of the X count pulse P signal. Pulses No. 2 and No. 3 of the X count pulse P signal are inhibited and the Xa pulse is formed 2 milliseconds after the first pulse. At this time, the pulse of the combo N signal is formed corresponding to the pulse of the X count pulse P signal and includes pulse number (N-1) of the X count pulse P signal.

The next pulse formed in the X combo N signal is pulse Xb that occurs 1.8 milliseconds after pulse No. (N-1) of the X count pulse P pulse train. Finally, the last pulse in the X Combo N pulse train is an Xc pulse formed 2.2 milliseconds after the XB pulse. In this way it can be seen how the X count pulse P pulse train is modified to form a smoothed pulse train on the step motor.

The formation of the Y-combo-N signal for Y step motor control for Y control word counts of four or more is very similar to that described above. When the Y-running flip-flop is set and its output Y-running N goes low, a Y-count pulse P pulse train is initiated. Referring to FIG. 21k, pulse No. 1 of the Y count pulse P pulse train is inverted by the NAND gate NA29A, and pulse No.
is used to form the first regenerated low pulse of the Y combo N signal accordingly. The Y running P signal is already high, and when flip-flop ff16B is set, the single shot circuit SS40A goes high as described above.
It is triggered by pulse No. 1 of the count pulse P pulse train. When single shot circuit SS40A times out and its Q output goes low, pulses No. 2 and No. 3 of the Y count pulse P pulse train are inhibited by nanodot gate NA29A. Also, as mentioned earlier, the Q output of the single shot circuit SS40B resets the flip-flop ff16B and inhibits the single shot circuit SS40A after receiving pulse No. 1 of the Y count pulse P pulse train. As mentioned above, triggered single shot circuit SS40A is activated when both the LS shift N and Ya pulse inhibit N signals are high.
Since pin 9 of is a low signal, this single shot circuit S
Used to trigger S60A. When single shot circuit SS30A times out and its Q bar output goes high, differentiator circuit 540 generates a positive pulse, which causes input 4 of NAND gate NA31B to go high.
A low Ya pulse is formed. Single shot circuit SS
A corresponding pulse is regenerated by 69A, which pulse is low wide on the Y-combo N signal while pulses No. 2 and No. 3 of the Y-count pulse P signal are inhibited 2 milliseconds after the formation of the first pulse. It is formed as a Ya pulse.

Pulse No. 4 and subsequent pulses of the Y count pulse P pulse train are used to form the regenerated low pulse of the Y combo N signal, in this case pulse No. 5, the pulse (
N-1).

As mentioned earlier in connection with FIG. 21j, 1L, the low signal of Y decode 4 plus N causes the Y counter CT62 to increase by one count during the memory cycle, so the high state of the Y carry P signal causes this counter to receive the Y count pulse. Obtained when strobed (N-1) or 5 times by the P inversion signal. At this time, the Y stop N signal becomes low and the 21st
The Y-travel flip-flop ff32B shown in the figure is reset, and its output Y-travel N is reset to high.

Referring to FIG. 21j, the Nth or sixth pulse of the Y count pulse P pulse train is inhibited as a result of the Y running N high signal. Referring again to FIG. 21k, the Nth or 6th pulse will never be a Y-combo N pulse train. However, when the Y-travel N signal of the Y-travel flip-flop goes high, differentiator circuit 514 generates a positive pulse at pin 2 of single-shot circuit SS30B.

Since the homing mode OP signal is low at this time, single shot circuit SS30B is triggered by the input 2 pulse. When this single shot circuit times out after 1.8 milliseconds, differentiator circuit 542 generates a positive pulse at input 5 of NAND gate NA29D.

Since the YB Pulse Inhibit N signal is high, a low Yb pulse is formed at input 3 of NAND gate NA31B, and thus a corresponding high pulse is formed at pin 10 of single shot circuit SS69A. This triggered single-shot circuit produces pulses N of a Y count pulse P pulse train.
Regenerate the pulse as a low wide YB pulse of the Y combo N signal at 1.8 ms after o(N-1) or 5.

The output of NAND gate NA29D is also connected to pin 1 of single shot circuit SS69B.

Since the basic Baum N and Yc pulse inhibit N signals are both high, the signal at pin 2 of single shot circuit SS69B is also high. Therefore, a low Yb pulse on pin of single shot circuit SS69B triggers this single shot circuit.

Single shot circuit SS69B times out 2.2 milliseconds after being triggered.

When the single shot circuit times out and its Q-bar output goes high, differentiator circuit 542 generates a positive pulse that passes through OR gate O82D and triggers bin 10 of single shot circuit SS69A.

Single shot circuit SS69A is for Y step motor control.
Regenerate the pulse as a wide low Yc pulse of the combo N signal.

Therefore, the Y combo N pulse train for the Y step motor is:
It is formed in the same way as described in connection with the X circuit.

For convenience, regarding the formation of a combo N pulse train of X and Y,
Although the case has been described where the counts encoded in the and Y data words are the same, it is understood that the control of the X and Y step motors is independent. Therefore, under normal conditions, the X and Y combo N for the X and Y step motors is encoded with different numbers of pulses in the X and Y data words.
The pulse trains have different types. Recalling in connection with FIG. 21d, the X and Y running flip-flops ff21B, ff
32B is simultaneously set by the start run N signal. Therefore, referring to FIG. 21j, the X and Y count pulse P pulse trains are started by the X and Y running flip-flop outputs and both start from the LS oscillation N.
Since they are formed from signals, it can be seen that they start at the same time. As long as one or more pulses are encoded into the X and Y data words, the first pulses forming the X and Y combo N pulse train occur simultaneously. But after this,
The pulse trains supplied to the N and Y step motors differ from each other depending on the number of counts encoded in the X or Y data word, respectively. Referring again to FIG. 25, the last pulse transmitted to the step motor occurs before the time T9 when the needle enters the fabric.

The last state mentioned for the X and Y data words corresponds to the count of these data words. Figures 21j and 33
Referring to the figure, the X or Y data word is inverted as the data N signal, so all data N signals are high and the X or Y counters - CT61 or CT62 are inverted when data enters these counters. Each time becomes a cup.

Referring to Figures 21d, 21e and 21j,
The corresponding X or Y Stop N signal is low due to the corresponding X or Y Carry P signal from the full counter becoming high. For example, the X Stop N signal is low because the X Carry P signal is high. When receiving the low pulse of the start run N signal, the X run N signal remains high even if a low pulse is formed at the output of the NOR gate NO20A which normally sets the X run flip-flop ff21B as shown in FIG. 21d. When the start run N signal decays, the X run P signal returns to a low state. Referring to Figure 21j, the X-Run N signal remains high, so the X-Count Pulse P signal is inhibited and remains low. Thus, referring to FIG. 21k, since no pulse is formed in the X count pulse P signal, no pulse is formed at input 10 or any other input of NAND gate NA31A. The X running P signal temporarily goes high and then returns to the low state to set flip-flop ff16A, but the X count pulse P
The absence of pulses in the signal prevents single shot circuit SS28A from being triggered. Since the remaining pulses depend on the trigger of the single shot circuit SS28A or the formation of pulses in the X count pulse P signal, no pulse is formed in the X combo N signal supplied to the X step motor, and the clamp does not move in the X direction. . The same result occurs for the Y step motor since the Y carry P signal is high before entering vertical mode. Of course, if both the X and Y data words are encoded with zero counts, the clamp will not move in the X or Y direction. Therefore, only the one of the two control words, X or Y, is normally encoded with a zero count. for example,
If the Y step motor is driven with 5 pulses and the X step motor is left at rest, a 0 count is programmed into the X control word and a 5 count is coded into the Y control word so that only the Y step motor moves. Make it.

At this time, for convenience of explanation, the control of the X and Y step motors corresponding to the X and Y control words to move the clamp relative to the needle is independent of whether it is in the program, sewing mode, stop sewing mode, or low-speed sewing mode. substantially the same. In either case, the X and Y data words are decoded to form an X and Y combo N signal for control of the X and Y step motors in accordance with the above description.

When both the X and Y running flip-flops of FIG. 21d are reset, both inputs 8 of NOR gate NA20C are reset.
, 9 are reset low. In this way, when the last of the two signals X-stop N and Y-stop N goes low, the output of NOR gate NO20C goes from low to high, and the differentiator circuit 550 generates a positive pulse at the input of inverter I19D. . Inverter I19D inverts the positive pulse and forms a low pulse at input 3 of OR gate 8C. Flip-flop ff21A is reset by the homing clear N signal, and the basic home P
Recall that the signal is low at this time. The state of input 3 of OR gate O8C is high until this input receives a low pulse, so NAND gate N
A low pulse is formed at input 1 of A11B and a high pulse is formed at its output, which triggers the single shot circuit SS22B at input 10.

Single shot circuit SS22B is subject to a 5 millisecond delay, which occurs between times T8 and T2 during T4, as described in connection with FIG. When the single shot circuit times out and its Q-bar output goes high, differentiator circuit 578 generates a positive pulse and switches to NTB mode O.
Since the P signal is normally high, this positive pulse is the gate NA
Input 11 of Noah Gate NO34B by 11C
is inverted as a low pulse. Also, the clamp mode OP signal is set low before homing mode,
This low pulse is inverted as a positive pulse to input 1 of NOR gate NO 135A. As mentioned earlier, the auxiliary start P signal is normally low and the NOR gate NO1
35A inverts the positive pulse, and inverter I131B inverts the corresponding low pulse again to flip-flop ff.
A positive pulse is formed at input 6 of 34A, which sets the memory cycle flip front. This flip-flop is pulsed E during the previous memory cycle.
Recall that it is reset by MC-P. Accordingly, the memory cycle enable P signal is again set high and the memory cycle enable N signal is set low to begin another memory cycle at time T2 of the timing cycle shown in FIG. Thus, referring to FIG. 21C, when the memory cycle enable N signal goes low, the clock pulse signal is again formed from the high speed clock signal for use during the memory cycle. Also, as described in connection with FIG. 21i, the memory cycle enable P signal causes chips 598-604 to
Reset the upper pulse inhibit flip-flop.

It can be seen how the control system is sequenced by the PROM programming in relation to the timing cycles shown in FIG. After completing the homing mode, the second
The initial 5 millisecond delay experienced by the single shot circuit SS22B of Figure 1d is for a period of .DELTA.T4. After completion of the delay, the memory cycle flip-flop f of FIG. 21d
f34A is set at time T2 to begin the first memory cycle. During a memory cycle, the Y data word is first read from the prom memory, inverted and decoded as the data N signal. The X data word is then read from the PROM, inverted and decoded as the data N signal. The control word is read from the PROM, inverted and decoded as the data N signal, and then the memory cycle ends at time T3. Furthermore, the address register is 3 times during the memory cycle.
Increase the number of times. At this time, the control system is prepared to initiate movement of the clamp by the X and Y step motors. However, this procedure is not performed until T4, when a positive pulse is generated by the nail drop sensor as the needle drop pulse P signal indicating that the timing cycle has advanced enough for the sewing machine to move the clamp. As mentioned earlier, the signal supplied to the step motor is
Due to the delay time associated with the step motor and the inertia of the clamp, the signal to the step motor is started before the needle actually breaks from the fabric. At time T5 the needle is removed from the fabric and actual movement of the clamp begins at time T6 in response to signals sent to the X and Y step motors. The clamping movement is completed at time T8, which is some time before the needle re-enters the fabric at time T9.

Then, during ΔT4, the single shot circuit SS22 of FIG. 21d
B is delayed for 5 milliseconds, after which the next memory cycle begins again at time T2.

In this way, the control system performs a programmed sequence, especially in the sewing mode.

Next, assume that a low-speed sewing command is received from one control word. As mentioned above, in order to slow down the sewing machine in preparation for a stop stitch command or a program end command, a series of low speed sewing commands are normally used before these commands. Second
As shown in FIG. 11, the low speed sewing P pulse forms a low pulse at the input 13 of the NAND gate NA70A, and the positive pulse formed at the output of this gate resets the flip-flop ff84A. Therefore, the sewing mode P signal is set low to take the control system out of sewing mode. Also, the output 1 of this flip-flop
is set high, so a high signal is formed at input 1 of drive circuit DC72A. Drive circuit DC72A
If either input is high, the output of this drive circuit is high and the main clutch brake solenoid is deenergized. Recalling in connection with FIG. 17, disc 430 is now pressed against main braking surface 434 of worm wheel 432.

As shown in FIG. 21g, the low-speed sewing P pulse is inverted by the inverter I52F to the flip-flop ff54.
Set C, its output 3 goes low and its output 6 goes high. Therefore, input 8 of OR gate O53C is low, and if the normal-repair selection switch is on the normal terminal side, the other inputs of OR gate O53C are also low, so input 1 of drive circuit DC88B is low.
The signal becomes low. If any input of the drive circuit is low, the high/low speed stitch command output signal will also be low. This state of the signal prevents the quick device from initiating a cut and stopping the sewing machine sequence even when the quick device detects from the unit 62 signal that the sewing machine is running at low speed. Therefore, the disk 4 in FIG.
46 remains pressed against the auxiliary clutch surface 448, and a sequence of slow commands is used to slow the sewing machine from high speed to low speed during the slow sewing mode.

Referring to Figure 21g, the slow stitch mode IP signal is set high by flip-flop ff54C to indicate that the control system is in the slow stitch mode. The delay signal at input 5 of AND gate A42A is also high to prepare this gate for the next stop sewing command. The flip-flop ff39B is reset by the intermediate stitch P pulse in the sewing mode so that its output 1 becomes low, and the process proceeds to the low speed sewing mode. Low speed sewing P pulse is also flip-flop ff57
A is set, its output STCH-IP is set high and its output STCH-OP is set low. Flip-flop ff57A is reset by the X strobe N signal during a memory cycle.

Referring to FIG. 21g, set flip-flop ff57 is connected to input 9 of NOR gate NO44B.
Since the output of A is low, it can be seen that a low pulse is formed for the start run N signal to begin forming the pulse train again for the X and Y step motors. Therefore, referring to FIG. 21d, the low pulse of the start run N causes the X and Y run flip-flops ff21B
, ff32B are set, and a pulse train of X and Y counter pulses P is started. As mentioned before,
Each pulse of the pulse train of X and Y counting pulses P causes the X and Y counters CT61 and CT62 to count, respectively, and as described in connection with FIG.
The X and Y combo N signal for controlling the step motor is formed from the X and Y count pulse P pulse train and the X and Y decoded control word in the same manner as described above in connection with the sewing mode.

However, at this time, the sewing needle is reciprocating at a low speed. Second
When the X and Y running flip-flops of FIG. 1d are reset after the completion of the clamping motion, differentiator circuit 550 again generates a positive pulse which triggers single shot circuit SS22B. After a 5 millisecond delay, memory cycle flip-flop ff34A is set again to begin a new memory cycle.

During normal operation of the sewing machine, the needle drop pulse P signal is used to initiate the formation of a pulse train for the step motor to move the clamp in the X and Y directions.

However, the needle does not move back and forth during the stop sewing mode, and the needle dropout pulse P pulse does not occur in this mode. Therefore,
A new reference is required during the stop stitch mode to sequence the control system through its operation.

As shown in Figure 21g, the positive pulse EMC-P formed at the end of each memory cycle is connected to the single shot circuit SS.
Trigger 18A on its pin 2.

This single shot circuit SS18A is subject to a 7 millisecond delay and when it times out its Q bar output goes high. At this time, the differentiator circuit 616 generates a positive pulse at input 2 of the NAND gate NA55B, and this positive pulse forms a low pulse as the start run N signal and starts the X and Y runs to start the pulse train supplied to the step motor. Used to set flip-flops. Assuming one or more continuous stop stitch commands are programmed into the prom, the EMC-P signal instead of the needle drop pulse P signal after the first timing cycle will execute the sequence every timing cycle as described below. Used for taking.

The timing cycle during the stop sewing mode after the first timing cycle is shown in FIG.

At time T1, the EMC-P pulse at the end of the memory cycle goes high, and the single shot circuit SS18 of Figure 21g
A is triggered, resulting in a 7 millisecond delay that ends at time T2. During the second and subsequent timing cycles in the stop stitch mode, the pulses generated in response to timing out of single shot circuit SS18A cause the X and Y travel flip-flops to set, thereby forming a pulse train to the X and Y step motors. , which ends at time T3. Of course, the time period during which the clamp is driven by the step motor depends on the number of pulses output to the step motor in the X and Y directions.

Therefore, this variable time depends on the count of X and Y control words. Once the motor pulse train is formed and the X and Y running flip-flops are reset, the single shot circuit SS22B of FIG. 21d is triggered, resulting in a 5 millisecond delay, which ends at time T4. At this time, the next memory cycle begins, and when completed, the EMC-P pulse is again applied at time T1 to the single shot circuit SS18A of Figure 21g.
trigger.

Therefore, in the second and subsequent timing cycles of the stop sewing mode, the control system
The MC-P signal initiates a sequence through the program. During the sewing mode and low-speed sewing mode, flip-flop ff57A in FIG. 21g is set by the sewing P or low-speed sewing P signal, so the NAND gate NA
A low signal is formed at input 1 of 55B. Therefore, a positive pulse is generated by the differentiator circuit 616 during the sewing and slow sewing modes, but this pulse is generated by the single shot circuit SS1.
NAND gate NA by 7ms delay associated with 8A
The delayed positive pulse at input 2 of this gate prevents the start run N signal from setting low since the input at 55B does not occur until it goes low. Therefore,
Flip-flop ff57A inhibits gate NA55B between sewing mode and low speed sewing mode. However, during each memory cycle flip-flop ff57A is reset by the X strobe N signal, and during the stop stitch mode, gate NA55B is enabled and produces a high signal on its input 1.

Thread cutting starts in the stop sewing mode, and the completion of this operation is
This is done before the clamping movement in this mode. Therefore, the pulses generated by differentiator circuit 616 in response to the triggering of single shot circuit SS18A are inhibited during the first timing cycle of the stop edge mode to prevent premature starting of the X and Y step motors; This is because a 7 millisecond delay is not enough before the thread breaks.

When the thread breaks, it is detected by the circuit shown in Figure 21h. When the thread breaks, the cut end signal goes low, triggering the single shot circuit SS18B. When the single shot circuit times out, its Q bar output goes high and differentiator circuit 618 generates a positive pulse that passes through ant gate A32C as the end cut pulse P pulse. As already mentioned, since the program end mode 1P signal is low at this time, this pulse is prevented from passing through the nanogate NA31C.

Referring to Figure 21l, as previously mentioned, when sewing flip-flop ff84A is reset during low speed sewing mode, the main brake clutch solenoid remains deenergized during stop sewing mode. Therefore, the disk 430 of the quick-release device shown in FIG. 17 remains pressed against the main braking surface 434. Referring to FIG. 21g, since the program end P signal is low at this time, the stop stitch P positive pulse is inverted by the NAND gate N
A low pulse is formed at input 12 of A54B.

Since the NTB mode pulse N signal is normally high, this low pulse is inverted by the NAND gate NA54B.
A positive pulse is formed at input 11 of NOR gate NO53A. Since the sewing P signal is low at this time, this pulse is inverted by NOR gate NO53A, and a low pulse is formed at input 1 of flip-flop ff54C to reset this flip-flop and clear out the low speed sewing mode. Therefore, flip-flop ff54
Output 3 of C is set high, which is the same state as the flip-flop described in connection with the sewing mode. In this case, assuming that the normal-repair selection switch is set to the normal terminal side, both inputs of the drive circuit DC88B are high, and the output signal of this circuit, which is a high-low speed sewing command, is also high.

At this time, the sewing machine should operate at a slow speed because the sequence of slow sewing commands is used during the slow sewing mode to slow down the sewing machine. As previously mentioned, the quick device monitors the signal from unit 62 to detect whether the sewing machine is running at low speed.

During the slow stitch mode, the quick device is prevented from starting the cut and stopping the sequence by the low signal output from drive circuit DC88B. However, during the stop stitch mode, this signal is high and the quick device is allowed to start this sequence as soon as it detects that the machine is running at low speed. As mentioned earlier, this should occur at the start of the stop stitch mode. In this manner, the quick device starts the cutter and forces the disc 446 against the auxiliary braking surface 450 to place the needle in the raised position and stop the needle from reciprocating. Upon receiving a pulse of end-of-cut pulse P indicating that the thread has broken, the clamp moves unhindered by the needle.

Referring to FIG. 21g, when the stop stitch P positive pulse is received, flip-flop ff39B is set and its output 1 is set high.

Therefore, the stop edge mode IP signal and the AND gate A42A
input 4 is set high. Flip-flop ff54C is reset and its output 6 is set low and delayed by delay circuit 620 to input 5 of ant gate A42A. As previously mentioned, in the slow sewing mode input 5 of ant gate A 42A is set high and therefore input 4 of this gate is set high so there is a short period in which both inputs of this gate are high. In this way,
The output of AND gate A42A momentarily goes high, setting flip-flop ff57B, and then the delayed signal at input 5 of AND gate A42A goes low, setting input 8 of flip-flop ff57B.
A low signal is generated. Therefore, at this time, output 10 of flip-flop ff57B is set low, so input 13 of NAND gate NA55B becomes low, which is before the single shot circuit SS18A times out and before the differentiator circuit 616 generates a pulse. Occur. The low signal of the input 13 of the NAND gate NA55b is the pulse generated by the differentiating circuit 616 during the first timing cycle of the stop sewing mode.
Prevent passing through A55B. Therefore, during the first timing cycle, no EMC-P pulses are used to initiate the pulse train to the X and Y step motors.

When the thread breaks and receives the end-of-cut pulse P positive pulse, flip-flop ff57B is set by this signal to enable gate NA55B during the next timing cycle. A positive pulse is also formed at input 12 of ant gate A42C. Since output 1 of flip-flop ff39B is set high, the positive pulse passes through this gate and enters input 12 of NOR gate NO44A.

At this time, it is found that input 11 of NOR gate NO44A is low. Since the basic home N signal is high, input 9 of NAND gate NA55A is also high. Since the needle dropout pulse P signal is low, NAND gate NA3
The 5A input 10 goes high. Since the time for the pulse from circuit 616 has passed, the ant gate NA5
Input 2 of 5B is low, and at this time the OR gate O
Input 11 of NA 46D is high, so input 11 of Nanodogate NA55A goes high,
A low signal appears at input 11 of NOR gate NO44A. Therefore, Noah gate NO44A is input 1
2, the positive pulse is inverted to form a low pulse for the start running signal.

As mentioned before, the start run N low pulse is X and Y.
Set the running flip-flop and begin forming pulse trains to the X and Y step motors. After the flange movement is complete, differentiator circuit 550 of FIG. 21d generates a positive pulse which sets flip-flop ff34A and begins another memory cycle. Assuming that the first word continuous stop sewing command is used as the control word, when the EMC-P pulse triggers the single shot circuit SS18A and its Q bar output goes high, the differentiator circuit 616 causes the output of the NAND gate NA55B. Generates a positive pulse at input 2. As already mentioned, flip-flop ff57B has been reset by the end-of-cut pulse -P signal, so it produces a high signal at input 13 of NAND gate NA55B.

Also, since flip-flop ff57A is reset by the X strobe N signal, NAND gate NA5
The signal at input 1 of 5B is also high. Therefore, the positive pulse formed at input 2 of NAND gate NA55B is inverted, and the corresponding low pulse is applied to OR gate O43.
D is formed at input 11. Since the other inputs of this gate are low and input 11 of OR gate O43D is already high, a low pulse passes through this gate and is formed as a low pulse at input 11 of NAND NA55A. The low pulse is this gate NA
Since the inputs 9 and 10 of NAND gate NA55A remain high, the NOR gate N
A stop pulse is formed at input 11 of O44A. Since the end-of-cut pulse p-pulse has decayed before this time, it is low at the input of AND gate A42C, thus forming a low signal at input 12 of NOR gate NO44A. Therefore, input 1 of Noah Gate NO44A
The positive pulse of 1 is inverted to form a low pulse as a start run signal, which sets the X and Y run flip-flops to form a pulse train to the X and Y step motors and the movement of the clamp in the X and Y directions. Start. Also,
After completing the clamp movement and resetting both the X and Y running flip-flops, the single shot circuit S of FIG.
There is a 5ms delay as S22B is triggered,
Then another memory cycle begins. If another stop edge command is encoded in the next control word, an EMC-P positive pulse is used at the end of this memory cycle to trigger single shot circuit SS18A to step X and Y in stop edge mode. Start other movements of the motor.

As previously mentioned, the last instruction provided in the PROM programming sequence is the program termination instruction. As also mentioned above, a sequence of slow stitch commands is provided prior to encoding this command to cause the machine to run slowly in a slow stitch mode for the final command. Also as described above, the end-of-program command stops the sewing machine, cuts the thread, and automatically enters the homing mode to reposition the clamp to the home position relative to the needle after cutting the thread.

Referring to FIG. 21g, upon receiving the program end P positive pulse, flip-flop ff39A is set;
Its output 10 is set low and the program end mode IP signal is set high. Since the low signal at the output 10 of the flip-flop ff39A passes through the delay circuit 512 and enters the input 10 of the NAND gate NA54A, the address clear P signal becomes high. The start pulse N signal is high at this time. Therefore,
The address clear P high signal is the register AR in Figure 21a.
1. Clear AR2 and reset flip-flop ff130A in preparation for other programs.

The program end IP high signal is fed to the OR gate O43D as shown in Figure 21g, so that when the triggered single shot circuit SS18A times out and a pulse occurs, the input 11 of the NAND gate NA55A.
remains high, thus preventing the formation of a low pulse for the start run N signal and the initiation of the clamping movement.

Referring to FIG. 21l, the program end P pulse causes the sewing flip-flop ff84A to open the gate NO44C.
, through NA70A to ensure that the main brake clutch solenoid is deenergized.
This sewing flip-flop is reset during the low speed sewing mode. Referring again to Figure 21g, Noah Gate NO.
The end-of-program P pulse applied to input 5 of 53B resets slow stitch flip-flop ff 54C, whose output 3 is set high and its output 6 is set low to clear out the slow stitch mode. Assuming the normal-repair selection switch is at the normal terminal, the input signals to drive circuit DC88B are both high, and the high and low speed sewing command signals are therefore high.

During the low speed sewing mode, the sewing machine slows down to a low speed, so the quick device starts the cutting device and stops the reciprocating movement of the sewing needle by engaging the auxiliary brake as already mentioned in connection with the stop sewing mode. do.

Referring to Figure 21h, when the thread breaks and the cut end signal goes low, single shot circuit SS18B is triggered. When this single shot circuit times out and its Q bar output goes high, the differentiator circuit 61
8 generates a positive pulse, which passes through AND gate A32C as a positive pulse for the cutting end pulse P signal and is supplied to input 1 of NAND gate NA31C.

As already mentioned, the program end mode 1P signal is high at this time, and the normal state of the NTB mode OP signal is yes. Therefore, the cutting end pulse P positive pulse is inverted by the NAND gate NA31C and is formed as the final cutting end N signal.

As shown in FIG. 21f, the final cutting end N low pulse is applied to the inverter I at the leading edge of the positive pulse thus formed.
91D, differentiator circuit 622 generates a positive pulse that resets flip-flop ff90A.

The flip-flop is set, its output 1 or clamp mode 1P signal is set low and its output 4 or clamp mode OP signal is set high. With the signals from input 8 of NOR gate NO90B and input 11 of NOR gate NO90C, the outputs of these gates become high, and the drive circuit D
C89A and DC89B are made to release the clamp between the cloth and the label. Therefore, the clamp is lifted during the final hominog mode, as described below.

Referring again to FIG. 21j, at this time the start pulse N
The signal is high. Therefore, the low pulse formed at input 4 of NAND gate NA32A is inverted by this gate, and a positive pulse is formed as the homing set P signal. This high pulse is again inverted by inverter I19A to form a low pulse as the homing set N signal. The Homing Set N and Homing Set P signals are used to initiate the start of the final homing mode as previously described. Thus, referring to Figure 21d, the homing set N
The signal sets flip-flop ff21A, whose output signal Basic Home P is high and Basic Home N is low, and the basic homing mode is then entered. If the final approach by the step motor is not made in a particular direction, the homing mode progresses through a basic homing mode, an auxiliary homing mode, and possibly a secondary auxiliary homing mode.

Once homing mode is completed and the clamp is lifted,
The operator removes the cloth sewn according to the program selected in the PROM. The operator inserts a new piece of cloth under the cloth crank and starts a new homing mode and a new program by depressing the pedal as described above.

The operation of the circuit connected to the yarn breakage sensor is described in connection with FIG. 21o. During initialization, flip-flop f
f124A, ff125A, ff125B are reset N
Reset by a signal. Therefore, flip-flop ff125A is reset and its output signal NTB mode OP is reset high, which is the normal state of this signal.

Also, this reset flip-flop ff124
By A, input 10 of Ant Gate A124C
A low signal is generated at the flip-flop ff125.
A YES signal is produced at input 12 of A. Finally, when flip-flop ff125B is initialized,
A low signal is formed at input 2 of NAND gate NA124D.

Referring to Figure 21m, if the NTB inactive switch is selected as its override terminal, a low state is established on the NTB override signal, and the ant gate A1
24C input 10 and flip-flop ff125
The signal at input 12 of A remains low during operation of the control system, and the NTB override switch is in this setting. Therefore, the NTB motor OP signal remains at its normal high state during this time and the yarn breakage sensor does not create a fault condition in the control system. However, with the NTB override switch in its auto terminal, the NTB override signal is removed from ground and the corresponding signal at input 10 of AND gate A124C is forced high. As already mentioned,
Input 1 of Ant Gate 124C during initialization
0 is set low by flip-flop ff124A. As can be seen below, flip-flop ff1
24A is not set until after the sewing mode is entered, and therefore the NTB mode OP signal cannot assume a low fault state until then.

As mentioned above, the sewing flip-flop ff8 of FIG.
The sewing mode P signal from 4A remains low until the sewing mode is entered. Sewing mode P low signal is inverter I127A
Therefore, a high signal is formed at the RST input of counter CT126C. Counter CT126C consists of the same four counting counters as counters CT58 and CT87 described in connection with FIG. 21e.

Therefore, RST of counter CT126c in FIG.
A high signal on the input clears this counter, preventing it from counting at this time. As shown, the needle drop pulse P positive pulse is inverted by inverter I127B to form a low pulse corresponding to the CLK input of counter CT126C. However, since the RST input of this counter is high before entering the sewing mode, the low pulse formed at the CLK input of this counter has no effect on this counter at this time.

When the control system enters the sewing mode, the sewing mode P signal becomes high as shown above, and the sewing mode counter CT1
A low signal is formed at the RST input of 26C. Therefore, the counter is enabled and increments once with each low pulse formed at the counter's CLK input in response to the nail removal pulse P positive pulse.

When four needle drop pulses P pulses are received, this counter increments four times and its QD output goes high at this time. In response, differentiator circuit 950 generates a positive pulse which sets flip-flop ff125B and the output signal at input 2 of NAND gate NA124D is set to a high state. As discussed below, a high signal on input 2 of nanodot gate NA124D enables the circuit to monitor the yarn breakage sensor for possible yarn breaks. Therefore, when the sewing mode is first entered and the thread is first used for sewing purposes, if the thread breakage sensor erroneously indicates a thread breakage, the circuit will operate during the first four sewing operations in the sewing mode. There's nothing to do.

After the counter CT126C counts four times and the flip-flop ff125B is set, the first positive pulse of the needle drop pulse P is output to the single shot circuit SS126 at pin 10.
triggers A because its pin 9 signal is already set low by initialized flip-flop ff124A. The single shot circuit SS126A thus triggered is now subject to a 1 millisecond delay. When the single shot circuit times out and its Q bar output goes high, differentiator circuit 952 generates a positive pulse. Nand Gate NA
Since input 2 of 124D is high at this time, the positive pulse is inverted by this NAND gate, forming a low pulse corresponding to input 4 of flip-flop ff124A, which sets this flip-flop and sets the input of AND gate A124C. At 10 this output signal is set high. (The single shot circuit SS126A is triggered by the pulse before the needle drop pulse P, but the low signal before the input 2 of the NAND gate 124D is triggered by the corresponding pulse in the differentiator circuit 95.)
2 to flip-flop ff124A. ) Flip-flop ff124A is the needle dropout pulse P
It is not set until 1 millisecond after receiving the pulse, so
The pulse of the needle drop pulse P has decayed by this time, and since the signal at input 9 of ant gate A 124C is low before flip-flop ff 124A is set, a continuous low signal is generated at input 12 of flip-flop ff 125A. However, the set flip-flop ff124A prepares AND gate A124C for the next pulse of needle drop pulse P by the delayed high signal at input 10 of AND gate A124C.

After the flip-flop ff124A is set and before receiving the next pulse of the needle dropout pulse P, the thread breakage sensor measures the thread tension to detect whether the thread has broken. When the thread breakage sensor indicates that the thread is not broken and detects that there is tension remaining in the thread, the resulting thread breakage sensor signal formed at the (-) input of comparator CA126B is generated from the +9 volt power supply. The reference signal at the (+) input of the comparator is exceeded for - time. In this case, a low signal is temporarily formed at the input 13 of the flip-flop ff124A, which resets the flip-flop ff124A.
A low signal is formed at input 10 of 4C. In this way, if the thread is not broken, the flip-flop is reset and the AND gate A124C is connected to input 10.
This low signal prevents the next positive pulse of the needle dropout pulse P from passing through the flip-flop ff125A.

However, if the thread breakage sensor indicates that the thread is broken and does not detect thread tension, comparator CA1
The signal at the (-) input of 26B is at a lower state than the reference signal at its (+) input, and the output signal of the comparator appearing at flip-flop ff124A and input 13 remains high. Thus, it remains high in this case. Thus, flip-flop ff124A does not reset in this case and its output signal, which appears at AND gate A124C, remains high. Therefore, upon receiving the next positive pulse after the needle dropout pulse P, this pulse will cause the gate A124C to be
, sets flip-flop ff125A, and its output signal NTB mode OP is set low to indicate to the control system that the sewing machine thread is broken. - When the thread is repaired, the flip-flop ff124A is reset by the thread breakage sensor signal and the next pulse of the needle dropout pulse P triggers the single shot circuit SS126A so that the pulse formed by the differentiator circuit 592 is Flip-flop ff125A is reset and its output signal NTB mode OP is set to the normal high state.

Looking back, after the four sewing operations in the sewing mode, flip-flop ff124A is about 1 after receiving the needle dropout pulse P.
Set in milliseconds. This flip-flop is reset before receiving the next pulse of the needle drop pulse P, unless the thread is broken, and the NTB mode OP signal remains high in this case. However, if the thread of the sewing machine is broken, the flip-flop ff124A is not reset, but the flip-flop ff125A is set by the next pulse of the needle removal pulse P, and the NTB mode OP is set.
The signal is forced low, indicating that the thread has broken.

When the control system enters another mode such as low-speed sewing mode, the sewing mode P signal returns to the low state, so the counter CT62
A high signal is generated at the RST input of , clearing and holding this counter. Also, since the output signal of inverter I127A goes from low to high at this time, differentiator circuit 954 generates a positive pulse, which resets flip-flop ff125B, and its output signal appearing at input 2 of NAND gate NA124D goes low. is set to Nand Gate NA1
The low state of input 2 of 24D is flip-flop f.
Since f124A is prevented from being set, the circuit is inhibited from instructing thread trimming until the sewing mode is re-entered.

It will be seen that flip-flop ff125B is reset to enter other sewing modes as described above in connection with circuit initialization. When re-entering the sewing mode in this way, upon receipt of four pulses from the nail drop pulse P signal, enabled by counter CT126C or its RST input, flip-flop ff125B is set and the signal appearing at input 2 of NAND gate NA124D is set. The actupt signal is set high to re-enable the circuitry to indicate thread breakage.

If the yarn breakage sensor detects a yarn breakage, the control system operates as follows. In the case of thread breakage, the NTB mode OP signal, which is high in the normal mode, becomes low as described above, so the needle is removed immediately after the positive pulse for the pulse P signal is formed.
As shown in Figure h, the NTB mode P signal becomes high. As shown in FIG. 21l, when the NTB mode P signal goes high, differentiator circuit 610 generates a positive pulse, which is inverted by inverter I85C to
Mode pulse N forms a low pulse of the signal. As previously stated, this low pulse is inverted by NAND gate NA70A to reset flip-flop ff84A and clear out the sewing mode. − side, main brake
The clutch solenoid is deenergized, slowing down the sewing machine.

When the control system is in the sewing mode, the output of the drive circuit DC88B of FIG. 21g is high and the quick device automatically stops reciprocating the needle when it detects from unit 62 that the sewing machine has slowed down. The NTB mode OP signal is (a) input 2 of NOR gate NO44D in Figure 21l, (b) input 2 of NOR gate NA78B in Figure 21F.
input 2 and (c) NAND gate N in Figure 21d.
A low state is established at input 5 of A11c. 21st
As shown in figure g, a low pulse is formed at the input 1 of the flip-flop ff54c by the NTB mode pulse N low pulse at the input 13 of the NAND gate NA54B, resetting the flip-flop and clearing out the low speed sewing mode. The sewing machine is forced to stop. Finally, as shown in Figure 21g,
The NTb mode P high signal is formed at the input of NOR gate NO44B.

It is clear that since the signal caused by the thread break is not formed until immediately after the needle drop pulse P, all conditions for driving the X and Y step motors and clamps are established. Therefore, as shown in FIG. 21g, when the pull-out pulse P pulse is received, a low pulse for the start running N signal is formed, the X and Y running flip-flops are set, and the X and Y step motors are clamped. A pulse train is formed in motion. When the clamping motion is complete and the X and Y running flip-flops are reset, the differentiator circuit 550 of FIG. 21d generates a positive pulse which triggers the single shot circuit SS22B. When this single-shot circuit times out, differentiator circuit 578 generates a positive pulse as before, but this pulse entering memory cycle flip-flop ff34A is connected to the NTB mode OP low of input 5 of Nant gate NA11C. Prevented by signals. In this way,
When the thread breaks, the clamp moves according to the last data read from the prom, but does not enter a new memory cycle. - On the other hand, the needle's reciprocation is stopped. Second
Referring to Figure 1h, the NTB mode OP low signal inhibits the formation of the final cut end N low pulse and prevents the clamp from being lifted.

After the thread has been repaired by the operator, the sewing operation can be continued in a few different ways. If desired, the 21st
As shown in Figure b, the reset switch may be pressed to bring the reset N signal low and the control system circuitry may be re-initialized as described above. An override switch is provided to prevent the operator from lifting the clamp if he or she wishes to retrace the current sewing pattern on the fabric. Therefore, after closing the reset switch, the control system enters homing mode as described above. At the end of the homing mode, the control system performs a program sequence and starts a new sewing operation as described above.

Alternatively, the operator may continue the program at the point where it is interrupted in response to a thread break. After repairing the thread, press the second foot pedal to start the stopped program. When the pedal go switch is activated, as shown in Figure 21f, a low pulse is generated as the condo go P signal. Since the NTB mode OP signal is low at this time, the corresponding pulse is blocked by NAND gate NA78B to prevent the formation of start pulse N and start pulse P.

As shown in FIG. 21i, since the NTT mode OP signal is low at this time, the low pulse of Condo-GoP is inverted as a positive pulse through AND gate A70D at its input 2. If you are in program end mode when the thread breaks, the program is complete and you are in program end mode I.
The P signal is set high. In this case, this signal is inverted by inverter I115A and ant gate A
A low signal appearing at the input of 70D prevents the formation of the auxiliary start P pulse. Otherwise, the signal at input 1 of AND gate A70D is high and a positive pulse is formed as the auxiliary start P signal. As already mentioned, if the control system is in sewing mode or slow sewing mode, the STCH-IP signal is high, in which case the pulse from gate NO44D is output to flip-flop ff84.
Gate NA70C is conditioned by this signal to set A and energize the main brake/clutch solenoid to begin reciprocation of the needle. Of course, if you are in slow sewing mode, this solenoid will be deenergized when the next command is decoded and the machine stops again.

As shown in FIG. 21d, the positive pulse of auxiliary start P applied to NOR gate NO135A creates a positive pulse at input 6 of memory cycle flip-flop ff34A, so that this flip-flop is set and ready for the next memory. Start the cycle and read the next three words from Prom.

As previously mentioned in connection with Figure 21o, after thread repair, flip-flop ff125A is reset to N
The T8 mode OP signal is reset to high in response to the needle drop pulse P pulse. As shown in Figure 21h, N
When the T8 mode OP signal goes high, the NT8 mode P inverted signal goes low. As shown in Fig. 2, NT8
After the mode P signal goes low, when the first positive pulse of the nail removal pulse P is received at input 4 of the NAND gate NA55C, a start run N low pulse is formed and a pulse train is sent to the X and Y step motors that drive the clamp. is formed. Therefore, at this point, the program continues in its normal sequence and the signals associated with the thread breakage sensor are in their normal state.

If, for some reason, the flip-flop in Figure 21f goes off so that the clamp is lifted during program control of the control system, and the clamp mode OP signal goes high and the clamp mode IP signal goes low, the operation will be as follows. . That is, as shown in FIG. 211, the lower brake and start solenoid are deenergized by the high signal of the clamp mode OP, and if the sewing machine is in sewing mode, the sewing machine is brought to a low speed and stopped. Further, as shown in FIG. 21g, the low signal of the clamp mode IP prevents the needle removal pulse P from passing through the NAND gate NA55C, and therefore prevents the clamp movement by the step motor. Finally, the second
As shown in Figure 1d, the clamp mode OP high signal prevents the passage of the pulse formed by differentiator circuit 578 and prevents the initiation of a new memory cycle. Closing the reset switch by the operator restarts the control system and puts it into operation as described above in connection with FIG. 218.

[Brief explanation of the drawing]

FIG. 1 is a side view of the sewing machine of the present invention, FIG. 2 is a front view of the sewing machine of FIG. 1, and FIG. 3 is a top sectional view of the sewing machine of FIG. 1.
4 is a front view of the drive means pulley of the sewing machine of FIG. 1, FIG. 5 is a plan view of the pulley of FIG. 4, and FIG. 6 is a sectional view of the upper part of the pivoting extension arm means of the sewing machine of FIG. 1. , FIG. 7 is a sectional view taken substantially along line 7-7 in FIG. 6, FIG. 8 is a sectional view taken substantially along line 8-8 in FIG. 6, and FIG. 9
The figure is a partial cross-sectional view showing the fixing means for the driving means of the sewing machine shown in FIG. 1, FIG. 10 is a cross-sectional view of the fixing means for the driving means, and FIG. 12 is a top sectional view of the homing assembly of FIG. 11, FIG. 13 is a sectional view of the limit assembly of FIG. 11, and FIG. 14 is a clamping means of the sewing machine of FIG. 1. 15 is a partial elevational view of the reciprocating means for the sewing needle of the sewing machine of FIG. 1, FIG. 16 is an exploded perspective view of the synchronizing unit of the sewing machine of FIG. A schematic diagram of the reciprocating means, FIG. 18 is a partial perspective view of the control system cabinet of the present invention, FIG. 19 is a block diagram of the electrical signal circuit of the sewing machine of FIG. 1, and FIG. 20 is a central control of the sewing machine of the present invention. 21a is an electric circuit diagram for the control system of the sewing machine of the present invention, FIG. 218 is an electric circuit diagram, FIG. 21c is an electric circuit diagram, and FIG. 21d is an electric circuit diagram. Figure 21c is the same electric circuit diagram, Figure 21f is the same electric circuit diagram, Figure 21g is the same electric circuit diagram, Figure 21h is the same electric circuit diagram, Figure 21i is the same electric circuit diagram, and Figure 21j is the same electric circuit diagram. Circuit diagram, Figure 21k is the same electric circuit diagram, Figure 21l is the same electric circuit diagram, Figure 21m is the same electric circuit diagram, Figure 21n is the same electric circuit diagram, Figure 21o is the same electric circuit diagram, Figure 22 23 is a timing diagram of a clock signal formed by the control system of the present invention, and FIG. 24 is a timing diagram of a clock signal formed by the control system of the present invention. FIG. 25 is a timing diagram of the sewing machine cycle during normal operation of the sewing machine; FIG. 26 is a diagram showing the data of the memory means of the sewing machine of the invention; FIG. 27 also shows the data. FIG. 28 is a diagram similarly showing data, FIG. 29 is a diagram similarly showing data,
FIG. 60 is a diagram similarly showing data, FIG. 31 is a timing diagram of signals formed by the control system of the present invention, and FIG.
2 is a timing diagram of the various signals generated by the control system of the present invention; FIG. 33 is a schematic diagram showing the various signals used in connection with the formation of the pulse train for the drive means;
4 is a timing diagram showing the relative times of the pulse train formed for the drive means, FIG. 35 is a timing diagram showing the relative times of the various signals used to form the pulse train for the drive means, and FIG. 36 is a timing diagram showing the relative times of the various signals used to form the pulse train for the drive means. FIG. 37 is a timing diagram, FIG. 38 is a timing diagram, and FIG. 39 is a timing diagram of the operation of the sewing machine while the sewing machine needle is stopped reciprocating. 50...Program control sewing machine 54...Sewing machine needle 56...Workpiece holder 62...Synchronization unit 58-60...Step motor 676...Central control logic circuit 772...Address counter 722...Sequence circuit 744... Pulse stop circuit 458... Programming prom 464... Program selection switch

Claims (7)

[Claims] (1) (a) A workpiece holder that holds a workpiece,
(8) a sewing needle; (c) memory means having a plurality of randomly addressable storage locations; (d) means for forming a first signal at a first point in time during a sewing machine cycle; and (e) a first signal. (f) means for reading information from the storage location and generating a signal corresponding to the read information; (g) after reading the storage location; (h) timing pulse generating means for generating a timing pulse at a predetermined second point in time during a sewing machine cycle; (h) responsive to said signal and timing pulse to simultaneously move the workpiece holder relative to the sewing needle along different coordinate axis directions; An automatic sewing machine consisting of a means for (2) The automatic sewing machine according to claim 1, wherein the timing pulse generating means generates the timing pulse at substantially the same time that the sewing needle comes out of the work piece during a sewing machine cycle. (3) The automatic sewing machine according to claim 2, wherein the timing pulse generating means generates the timing pulse slightly before the sewing needle comes out of the work piece. (4) The timing pulse generating means includes means for forming a first pulse at a first time of a sewing machine cycle, means for forming a second pulse at a different second time of the sewing machine cycle, and means for forming a second pulse at a different time of the sewing machine cycle. a first of said timing pulse generating means for forming said timing pulse;
The automatic sewing machine according to claim 1, further comprising selection means for selecting either the pulse or the second pulse. (5) The automatic sewing machine according to claim 4, wherein the selection means comprises a switch means. (6) The automatic sewing machine according to claim 11, wherein the timing pulse generating means generates the second pulse after the sewing needle exits the work piece until it reenters the work piece. (7) reciprocating means for reciprocating the sewing needle at high speed and low speed; and the selection means is a second part of the timing pulse generation means.
and means for starting the operation of the reciprocating means at the low speed when a pulse is selected.
The automatic sewing machine described in section.