JPS595639A - Hybrid integrated circuit - Google Patents
Hybrid integrated circuitInfo
- Publication number
- JPS595639A JPS595639A JP11505082A JP11505082A JPS595639A JP S595639 A JPS595639 A JP S595639A JP 11505082 A JP11505082 A JP 11505082A JP 11505082 A JP11505082 A JP 11505082A JP S595639 A JPS595639 A JP S595639A
- Authority
- JP
- Japan
- Prior art keywords
- solder
- bump
- pattern
- integrated circuit
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3452—Solder masks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明ｔまフリップチップのボンディング方法に関す
るものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip chip bonding method.
近年、成子業界の発展は目覚しく、特に半導体の伸びは
著しいものがある。ＩＣ，ＬＳＩなどは集積度がどんど
んと増加され、高密度化されている。この半導体素子を
実装する方法もいろいろと検討され、実用化されている
。フリップチップ方式もそのひとつで、半導体チップの
能妨面に、バンプという金属の突起磁極を備えている。In recent years, the development of the Seiko industry has been remarkable, with the growth of semiconductors being particularly remarkable. The degree of integration of ICs, LSIs, etc. is increasing rapidly and becoming denser. Various methods for mounting this semiconductor element have been studied and put into practical use. The flip-chip method is one such method, in which a metal protruding magnetic pole called a bump is provided on the non-contact surface of a semiconductor chip.
一般には、半田バンプか良く用いられ、混成集積回路基
板上に他の受動、能動部品と一緒に半田付けされる。Ｉ
Ｃチップの罐極政が多くなると、当然、バンプ攻が増加
し、チップナイズ簡制約からバンプの大きさを小さくし
ていかなければならない、
バンプの大きさが小さくなるに従い、そこに均一な獣の
半田を形成するのが難しくなってくる。Typically, solder bumps are used and soldered together with other passive and active components on a hybrid integrated circuit board. I
As the number of C chips increases, the number of bump attacks will naturally increase, and the size of the bumps must be reduced due to the chip size restriction. It becomes difficult to form solder.
又、フリップチップの半田量だけでは半田接続として充
分なボンディング強度が得られなかったり、ボンディン
グ歩留りの低Ｆが考えられる。そのため、混成集積回路
の基板側導体にも予備半田が必要となる場合がある。こ
の場合も同様、微小導体部に均一半田量を予備半田する
ことは難しい。そのためフリップチップを半田リフｏ
−した後、半田量のバラツキにより半田オープンや半田
ブリッジなとのボンディング不良が生じ易い。Furthermore, it is conceivable that sufficient bonding strength for solder connection cannot be obtained with only the amount of solder on the flip chip, or that the bonding yield is low. Therefore, preliminary soldering may also be required for the board-side conductor of the hybrid integrated circuit. In this case as well, it is difficult to pre-solder the minute conductor portions with a uniform amount of solder. Therefore, it is necessary to solder the flip chip.
- After soldering, bonding defects such as solder opens and solder bridges are likely to occur due to variations in the amount of solder.
第１図及び＄２図は従来の混成集積回路基板上の７リツ
プチツプを塔載するパターンを示す部分平面図及びその
上に７リツプチツプをボンディングされたところを示す
部分断面図である。FIGS. 1 and 2 are a partial plan view showing a pattern on which 7-lip chips are mounted on a conventional hybrid integrated circuit board, and a partial sectional view showing a pattern on which 7-lip chips are bonded.
混成集積回路基板（１）上には、銀、パラジウムなどの
ような金網などで導体パターン（２）が形成されている
。又ガラスダム（３）が上記導体パターン（２）のうち
バンプパターン（４）となる部分のみ穴をあけて形成さ
れており、これは上記バンプパターン（４）の部分に半
田をのせてフリップチップ（５）を半田づけする際に、
ハンダのつかないガラスによって半田が流れるのを防止
するためのものである。A conductor pattern (2) is formed on the hybrid integrated circuit board (1) using a wire mesh made of silver, palladium, or the like. In addition, a glass dam (3) is formed by drilling holes only in the portion of the conductor pattern (2) that will become the bump pattern (4), and this is done by placing solder on the bump pattern (4) and forming a flip chip ( When soldering 5),
This is to prevent solder from flowing due to the non-solder glass.
このように７リツプチツプ（５）のバンプパターンに合
せて、基板（１）上にもバンプパターン（４）か形成さ
れており、この箇所に７リツプチツプ（５）が半田１６
）にてボンディングされる訳であるが、このバングパタ
ーン（４）が微小になればなる程、均一な半田（６）の
量にてフリップチップ（６）をポンディングすることが
錐かしくなり、半田ブリッジ（７）すどの不良が発生し
易くなる。In this way, a bump pattern (4) is also formed on the substrate (1) in accordance with the bump pattern of the 7-lip chip (5), and the 7-lip chip (5) is soldered at 16.
), but the smaller the bang pattern (4), the more difficult it becomes to bond the flip chip (6) with a uniform amount of solder (6). Failure of the solder bridge (7) is likely to occur.
本発明はこれらの従来のものの欠点に鑑みてなされたも
ので、混成集積回路基板上で、７リツプチツプのバンプ
パターンの一部に余分な半田が流れ込めるための特殊な
微細導体パターンからなる半田流れ部を加えてバンプパ
ターンを形成して８き、この上に７リツプチツプをポン
ダイングすることにより、各バンプパターンにおける半
田量にバラツキが生じていても、半田量の多いものは上
記半田流れ部に伝って半田が流れて半田量が多いための
半田ブリッジ不良などが激減し、高品質のポンディング
か得られる混成集積回路を提供することを目的としてい
る。The present invention has been made in view of these drawbacks of the conventional methods, and is a solder flow consisting of a special fine conductor pattern that allows excess solder to flow into a part of the bump pattern of a 7-lip chip on a hybrid integrated circuit board. By adding 8 parts to form a bump pattern and then pounding 7 lip chips on top of this, even if there is variation in the amount of solder in each bump pattern, the part with a large amount of solder will be transferred to the solder flow part. The purpose is to provide a hybrid integrated circuit that can achieve high-quality bonding and dramatically reduce solder bridging defects due to solder flow and a large amount of solder.
以下、本発明の実施例を図に従い詳細に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
第３図、第４図は本発明の一実施例を示す一部平面図及
び断面図である。FIGS. 3 and 4 are a partial plan view and a sectional view showing an embodiment of the present invention.
％３図に８いて、（９）はバンプパターン、＋８１ ｉ
ｌｉこのバンプパターン（９）に連続して形成された余
分な半田を流れ込ませるための微細導体パターンからラ
スダム（３′）は上記パンダパターン（９）がこのよう
な半田流れ部（８）を有するように形成されている。%3 Figure 8, (9) is a bump pattern, +81 i
The last dam (3') is formed from the fine conductor pattern continuously formed on this bump pattern (9) to allow excess solder to flow into it.The panda pattern (9) has such a solder flow part (8). It is formed like this.
本実施例装置に８いてポンディングを行なう場合、基板
（１）側に予備半田を行なう場合でも、バンプパターン
（９）のうちのバンプ形状のところのみ予備半田を行な
い、半田流れ部（８）はそのまま導体パターン（２）を
露出させておく。こうしてフリップチップ（５）を基板
（１）にボンディングすると、他のバンプ部より極端に
半田（６）の量が多いバンプ部は、半田（６）を押しつ
ぶす方向に力が加わるため、半田流れ部（８）に余分な
半田が押しやられ名。そしてすべてのバンプの半田（６
）量のバランスのとれたところで半田（６）の移動はな
くなる。かくて均一な半田高さてもって高品質の７リツ
プチツプのポンディングが完ｒするわけである。When performing bonding using the apparatus of this embodiment, even if preliminary soldering is performed on the board (1) side, preliminary soldering is performed only on the bump-shaped portions of the bump pattern (9), and the solder flow area (8) is Leave the conductor pattern (2) exposed as it is. When the flip chip (5) is bonded to the substrate (1) in this way, the bumps where the amount of solder (6) is extremely larger than other bumps are subjected to force in the direction of crushing the solder (6), so the solder flow area (8) Excess solder is pushed away. and solder all the bumps (6
) When the amount of solder (6) is balanced, the movement of solder (6) stops. In this way, high quality 7-lip chip bonding can be completed with a uniform solder height.
以上のようにこの発明によれば、基板上に７リツプチツ
プが塔載される混成集積回路において、ツ゛リップチッ
プのバンプパターンの一部に余分な半田を流れ込ませる
ための補助用の微細導体パターンを加工たバンプパター
ンを形成して半田付けを行なうようにしたので、各バン
プ半田のバランス力！とれるように半田の移動が行なわ
れ、半田ブリッジ不良などが激減し、高品質のボンディ
ングが得られる効果がある。As described above, according to the present invention, in a hybrid integrated circuit in which seven lip chips are mounted on a substrate, an auxiliary fine conductor pattern is processed to flow excess solder into a part of the bump pattern of the lip chip. Since the bump pattern is formed and soldered, the balance of each bump solder is perfect! The solder is moved so that it can be removed, and the number of solder bridging defects is drastically reduced, resulting in high-quality bonding.
施例を説明するための一部平面部及び−線断面図である
。
（１）・・・混成集積回路基板、ｔ２） ＋２１・・・
導体パターン、１３１１３１・・・ガラスダム、 ＋４
１・・・バンプパターン、＋Ｓ＋・・・フリップチップ
、（６）・・・半田、（７）・・・半田ブリッジ、（８
）・・・半田流れ部１．ｄ＋・・・バンプパターン。
なお図中同一符号は同−又は相当部分を示す。FIG. 2 is a partial plan view and a cross-sectional view taken along the line 10-1 for explaining an example. (1)...Mixed integrated circuit board, t2) +21...
Conductor pattern, 131131...Glass dam, +4
1... Bump pattern, +S+... Flip chip, (6)... Solder, (7)... Solder bridge, (8
)...Solder flow part 1. d+...bump pattern. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
上に形成された導体パターンと、この導体パターンの一
部に形成され余分な半田を流れ込ませるための半田流れ
部を備えたバンプパターンと、上記混成集積回路上に配
置されたフリップチップと、上記混成集積回路のバンプ
パターン上に設けられ上記フリップチップを支持すると
ともに上記混成集積回路に罐気的に結合する半田バンプ
とを備えたことを特徴とする混成集積回路。(1) a hybrid integrated circuit board, a conductor pattern formed on the hybrid integrated circuit board, a bump pattern formed on a part of the conductor pattern and provided with a solder flow portion for flowing excess solder; A flip chip disposed on the hybrid integrated circuit, and a solder bump provided on a bump pattern of the hybrid integrated circuit to support the flip chip and to be electrically coupled to the hybrid integrated circuit. Features of hybrid integrated circuits.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11505082A JPS595639A (en) | 1982-06-30 | 1982-06-30 | Hybrid integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11505082A JPS595639A (en) | 1982-06-30 | 1982-06-30 | Hybrid integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS595639A true JPS595639A (en) | 1984-01-12 |
Family
ID=14652936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11505082A Pending JPS595639A (en) | 1982-06-30 | 1982-06-30 | Hybrid integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS595639A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| FR2854760A1 (en) * | 2003-05-06 | 2004-11-12 | Wavecom | ELECTRONIC SYSTEM WITH FUSED MATERIAL OVERFLOW CONTAINERS, AND ASSEMBLY METHOD THEREOF |
-
1982
- 1982-06-30 JP JP11505082A patent/JPS595639A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5478007A (en) * | 1993-04-14 | 1995-12-26 | Amkor Electronics, Inc. | Method for interconnection of integrated circuit chip and substrate |
| US5795818A (en) * | 1996-12-06 | 1998-08-18 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection and method |
| US6163463A (en) * | 1996-12-06 | 2000-12-19 | Amkor Technology, Inc. | Integrated circuit chip to substrate interconnection |
| FR2854760A1 (en) * | 2003-05-06 | 2004-11-12 | Wavecom | ELECTRONIC SYSTEM WITH FUSED MATERIAL OVERFLOW CONTAINERS, AND ASSEMBLY METHOD THEREOF |
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