JPS595647A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To use a circuit element through a time division, and to realize a number of functions by the same chip-size by controlling a logical gate according to the contents of a memory cell set up separately and changing functions. CONSTITUTION:DATA 1 or DATA 2 are latched in a rise of a terminal CL in a cell 500. A functional mode of a cell 600 changes by the data latched. When the cell 500 and the cell 600 are brought to the state in which they are not connected, two are combined and can be used as D flip-flops in the D-latch of sections which need not be brought to programmable states. Logics are assembled in a hard manner in an IC, and the types of the gates can also be controlled by the result. For constitute the D flip-flop by using the cell 500, A or A' of the cells on the lower side is connected to the DATA 2 of the cells on the upper side, and B or B' may be used as a Q output terminal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and in particular, the present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit, in which the operation mode is controlled not only by changing the function by changing the wiring (turn), but also by changing the contents of the built-in memory element. Possible, programmable, master, related to slicing.

Conventionally, there has been a circuit of this type as shown in FIG. The figure shows 2NAND in silicon, Ga), CMC)S
, which can be obtained using two-layer metal interconnection technology.In this way, two sets of bare P-channel FETs and N-channel FETs with common gates are lined up as a basic cell, and this basic cell is shown in Fig. 2. Arranged in a matrix like this,
Generally, there is room for metal wiring between each row.

That is, two sets of N-channel FETs 2 are formed in the P-well 1, while two sets of P-channel FETs 3 are separately formed. Each Fl (T2.

3 is silicon MOS by polysilicon 4.5
It is an FET.

2111 WIUP--FIG. 2 shows details of the N-channel MO8FET 2 of FIG. 1 formed in well 1; N
Type drain region 21, N type source region 22 and polysilicon 4, furthermore N type source region 23, N type drain region 22 and polysilicon 5 are FET Q A*
It constitutes QB. In the case of 2NAND, the aluminum wiring 6 is connected to the source 23 of FETQB through a contact hole 61 and connected to the reference potential 1.

Still aluminum distribution #! 7 is contact hole 71 F E
T Connected to the drain of QA and becomes an output terminal, F E
TQAeQB are connected in series.

Similarly, the drains of the two P-channel FETs 3 are connected to the FETQA through contact holes 72 and 73, and the aluminum wiring 8 is connected to the common source through the contact hole 81, and connected to the power source V])D. has been done. The FETs wired in this way form a two-way NAND gate as shown in the equivalent circuit in Figure 3, where the polysilicon 4.5 corresponds to the points A and H, respectively, and the output X is connected to the aluminum wire 7. It corresponds to Then, these first layer aluminum wiring lines 6. 7. By changing the wiring pattern of 8, it is possible to configure a two-man power NOR gate, an inverter, etc. The gates thus obtained are interconnected by bending metal wires onto the wiring area 20.

For example, in FIG. 1, the wiring area 20 is composed of a plurality of wirings 71201 to 205, and the gate 4
) are connected to the wiring layer 20 by contact holes 91 and 92, respectively.
The gate (Bl) is connected to the wiring 1@202 through the contact hole 101.

A logic circuit having a desired function is obtained by forming a plurality of cells 300 composed of these four FETs and wiring areas 20 as shown in FIG. 4, and changing the wiring pattern.

A logic circuit having a certain function can be realized by using forceful means, and the circuit formed on a semiconductor substrate is commercially available as a master or a slice.

In mastering and slicing, the processes before the wiring process are common even for the next generation of ICs, and are manufactured using normal mass production technology, but when the type changes, only the mask for the wiring process needs to be created. However, various functions can be realized by changing the wiring bars. Regarding the IC1 variety,
The costs involved in making a full-thickness mask are enormous, and the unit price is high if the lifetime production quantity is small.In addition, if there is a mistake in the mask and it is corrected, the entire process will be required.)
This would require a long product development period. In addition, with mask-slice, the same pattern is repeated and thickened, so it is easy to automatically design using a computer. has no choice but to rely on human labor, and is a master in terms of the cost of developing a single ice product. Slices are advantageous.

However, as mentioned above, in conventional mass slicing, a predetermined number of circuit elements such as FETs and cross wiring bodies are formed in advance, so the chip size is the same regardless of the circuit scale, and the same circuit is manufactured using all masks. Compared to the case of using the Massumi slice, there are 711 L unused circuit elements, so the area is three to four times larger.

This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is possible to incorporate a memory element so that circuit elements can be used in time division, and to change the contents of this memory element. Therefore, the objective is to provide a master and a slice that can realize more functions with the same chip and size by changing the functions and reducing the circuit scale.

An embodiment of the present invention will be described below with reference to FIGS. 5 and 6. In FIG. 5, two cells 500 each use a D-latch as a storage element and a transmission gate.
It is composed of Bl, B2 and (member 4B3mB4) and operates as a memory cell.

Further, the cell 600 is a logic cell and is composed of FETQ□ to Q, which are gates that have different functions depending on the contents of the storage element. The storage element may also be a static RAM, a dynamic RAM, a dynamic D flip-flop, or the like.

Although other circuit configurations are possible for the gate, the cell 600 shown in FIG. 5 is superior in terms of the number of elements. In the cell 600, terminals X and Y are provided as input signals, and terminals Z are provided as output signals, and the functions are (a).
Z=X, (b) Z=Y, (c) Z=X+
Y, (di z=x, Y (7) 4-bit function is possible. In order to realize the 4-bit function, 2 bits of information are required, so for 6001 cells, the memory element 4) A button is provided to switch between 111 and 111 functions using the 2-bit signals A and B shown in FIG. In this example, a D latch is used as the memory element, so
Terminal DATA that supplies data to be read to the D lug
1. DATA2 is provided, and terminals CL and CL for supplying a signal for the D-latch to read data are provided.

An example of arranging a plurality of basic circuits is shown in Fig. 6 (□). In this way, the cells 500 are arranged in a row, and the cells 600
are arranged in a line with 5002 cells, so that one cell is included, and cells 500. Leave cell 600 unwired,
As will be described later, it is more advantageous in terms of application to provide a wiring area 700 between the cells 500 and 600 and to connect them according to one circuit.

Next, the operation of this invention will be explained. Figure 5 Cell 5
00 is a well-known D-latch, and when CL rises, DATA1, internal data, and DATA2 are latched. This latched data changes the functional aspect of cell 600, but A=O, B=O%, so A=1. B=1
When Qs=Q+, Q・, Qll is conductive, Q.

, Qu*Q@*Qt. is non-conducting and cell 600 is NOR
It becomes equivalent to a gate. A=1, B=1, therefore λ==
0. When B=O, Q s −Q 4−Q8Qss
is non-conducting, Ql -Qs -Qo -Qt. is conductive,
Cell 600 becomes equivalent to a NAND gate.

When Awo1, B=0, therefore %^==0 and B=1, Qs, Qs, Qt. , Ql, are conducting and sQt* Q4 * Qa * Qs are non-conducting, making the cell 600 equivalent to an X inverter. A=O,B
=1, therefore, when A=1.8=O, sQs+Qs
eQs. 5Qts is non-conducting, Ql # Q4 s Q
When s*Q@ is conductive, cell B becomes equivalent to Y's inno (-).

When the basic cells in Fig. 5 are arranged as shown in Fig. 6,
Leave cells 500 and 600 unconnected,
In this way, two D-latches that do not need to be made programmable can be combined and used as a D flip-flop. It is also possible to construct a heart-like logic inside the IC and control the gate type based on this result. Using cell 500,
To configure a D flip-flop, in FIG.
A or λ of the lower cell, DATA of the upper cell
2 and use B or 100 as the Q output terminal.

In the above embodiment, the circuit configuration is used, but of course,
In other logics such as NMO8, TTL, ECL, etc.
Exactly the same thing can be achieved, and in the fourth garden, A, A,
B, B and positive/negative logic are used, but if some FETs in the cell 600 are changed from P type to N type and from N type to P type, it can be realized with two Shintan lines. You can also do it.

Further, in the above embodiment, it is assumed that the memory element is one in which data can be written bit by bit, but it may be a shift register, a CCD memory, or the like. However, as shown in FIG. 6, if the cell 500. cell 60
If 0 is left unconnected, it can be used for either a type that writes data bit by bit or a type that writes data serially, and can also be written on the same chip.

In addition, in the above embodiment, a two-manpower, one-output gate was considered as the cell 600, but a gate with three or more manpower and two outputs or more could be constructed using a similar method, although the circuit configuration and wiring would be complicated. It is also possible to change the function. Further, in the cell 600, a buffer is not attached to the two terminals, but if the chip size is large and there is a possibility of driving a long wiring line, a buffer may be attached.

Also, cell 500. Although it is assumed that the circuit in cell 600 is a fixed circuit, it is also possible to configure a circuit equivalent to this embodiment by changing the wiring using a normal master slice. Or cell 60
This does not prohibit leaving the internal parts of 0 unconnected and wiring them according to the circuit.

Furthermore, it is possible to adopt a single circuit configuration in one part of one chip and control other circuits, and it is not possible to implement a circuit that controls this circuit on the same chip. This is also a desirable aspect of the circuit configuration.

As described above, according to the present invention, the logic gate is configured to be controlled and change the function according to the contents of the separately provided memory element, so that the logic gate functions by transferring control data. It is possible to realize a semi-folding integrated circuit with different characteristics.

Moreover, the masks that are created depending on the circuit are only those for the wiring process, similar to the conventional square 4-slice, so the flexibility to change one circuit at low development costs and rapid development speed is completely lost. GanaX/-ht.

Furthermore, since the elements in the circuit can be used in a time-sharing manner by transferring control data, a wide range of functions can be realized with a small number of circuit elements, which is also detrimental to chip size reduction.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the basic cell since then, Figure 2 is a diagram showing details of a part of the cell in Figure 1, Figure 3 is a diagram showing the equivalent circuit of the cell in Figure 1, and Figure 4 is a diagram showing the equivalent circuit of the cell in Figure 1. FIG. 1 is a diagram showing the overall configuration of a combination of a plurality of cells. FIG. 5 is a diagram showing the basic circuit of a cell according to the present invention, and FIG. 6 is a diagram showing the overall configuration obtained by combining a plurality of cells shown in FIG. 300.500.600... Self 00...
... Connection area B1. B2...Transmission 2-)B3
．． Inverter Q, ~Q11...FET for B4... Patent applicant Pioneer Co., Ltd. Figure 1 and Figure 2 (i) Figure 8 o7 Figure 4

Claims (2)

[Claims] (1) A memory circuit that stores different memory contents according to external data, a control signal line that outputs data corresponding to the memory contents, and a plurality of different logical functions depending on the data contents of the control signal line. A semiconductor integrated circuit comprising a variable logic circuit. (2) a memory circuit that stores predetermined memory content; a control signal line that outputs the memory content; a logic circuit that changes to a different logic function depending on the data content of the control signal line; and the memory A semiconductor integrated circuit comprising a wiring means interposed between a circuit and a logic circuit, wherein a control signal line is changed by the wiring means to give the content of a predetermined control signal line to the logic circuit. .