JPS5954956U - semiconductor package - Google Patents
semiconductor packageInfo
- Publication number
- JPS5954956U JPS5954956U JP14995782U JP14995782U JPS5954956U JP S5954956 U JPS5954956 U JP S5954956U JP 14995782 U JP14995782 U JP 14995782U JP 14995782 U JP14995782 U JP 14995782U JP S5954956 U JPS5954956 U JP S5954956U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor package
- tip
- length
- wiring
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は本考案による半導体パッケージの一実施例にお
いて半導体ICを取着した状態を示す断面図、第2図は
その一部を示す平面図である。
11・・・絶縁基板、15・・・半導体IC117゜1
71・・・金属配線、19・・・電極リード。FIG. 1 is a cross-sectional view showing a state in which a semiconductor IC is attached in an embodiment of a semiconductor package according to the present invention, and FIG. 2 is a plan view showing a portion thereof. 11... Insulating substrate, 15... Semiconductor IC117゜1
71...Metal wiring, 19...Electrode lead.
Claims (1)
続する多数の金属配線を具備した半導体パッケージにお
いて、前記金属配線のうち標識となるべき金属配線の先
端部の長さを他の金属配線の先端部の長さと不揃いとし
たことを特徴とする半導体パッケージ。In a semiconductor package equipped with a large number of metal wirings that electrically connect the electrodes of a semiconductor element mounted on an insulating substrate, the length of the tip of the metal wiring that is to become a mark is A semiconductor package characterized by the length of the tip of the wiring being uneven.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14995782U JPS5954956U (en) | 1982-09-30 | 1982-09-30 | semiconductor package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14995782U JPS5954956U (en) | 1982-09-30 | 1982-09-30 | semiconductor package |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5954956U true JPS5954956U (en) | 1984-04-10 |
Family
ID=30332723
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14995782U Pending JPS5954956U (en) | 1982-09-30 | 1982-09-30 | semiconductor package |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5954956U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6260418U (en) * | 1985-10-04 | 1987-04-15 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5279658A (en) * | 1975-12-25 | 1977-07-04 | Citizen Watch Co Ltd | Semiconductor device |
-
1982
- 1982-09-30 JP JP14995782U patent/JPS5954956U/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5279658A (en) * | 1975-12-25 | 1977-07-04 | Citizen Watch Co Ltd | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6260418U (en) * | 1985-10-04 | 1987-04-15 |
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