JPS5947772A - Manufacture of field effect transistor - Google Patents

Abstract

PURPOSE:To improve reproducibility and controllability by a method wherein the first and second metallic films having thermal resistance are successively formed, the source and drain regions are formed by implanting donor ions with the second metallic film as the mask, and the donor ions are activated by removing only the second metallic film. CONSTITUTION:An active layer 22 serving as the channel part of a field effect transistor is kept formed by selectively implanting the donor ions onto a GaAs semi-insulation substrate 21. The W film 23 and the Ni film 24 are successively deposited over the entire surface by electron beam vapor deposition method. The Ni film 24 and the W film 23 are etched by ion milling method with a photo resist 25 as the mask, resulting in the perfect removal of the Ni film 24, and accordingly the W film 23 is etched about half. When plasma etching is performed, the Ni film 24 and the GaAs semi-insulation substrate 21 are not at all affected, but only the W film 23 is etched. The donor ions are implanted at high density, resulting in the formation of N<+> implanted layers 26, the Ni film 24 is removed by chloric acid, and heat treatment is performed by covering the entire surface with an insulation film.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing GaAs' superfluous field effect transistors at high speed and with high integration.

GaAs (gallium arsenide) has an electron mobility several times higher than that of St (silicon), and a semi-insulating substrate can be easily obtained. The high-speed logic integrated circuit 41 (metal-semiconductor contact type) is important as a basic element of the circuit, and GaAs logic integrated circuits of several scales or more have already been prototyped.

However, in field effect transistors in which the gate, source, and drain are independently fabricated using common photolithography (etching technology), it is necessary to provide a margin of T(+: It is necessary to separate the electrodes by 1 μm and 8 degrees, and as a result, the source resistance decreases and the high-speed performance is lost to some extent.

In order to solve the above-mentioned drawbacks, the self-plasticization process is devised to automatically bring the gate electrode and the source/drain region close to each other. The self-alignment process is also considered to have a divine form, but the method described below using heat-resistant r-) is superior in terms of simplicity. There is.

As shown in FIG. 1, one is Tf-W (titanium tungsten combination > 1) or Ti-W silicide i! with a heat resistance of 1° and a 1-chip gain of 11. After depositing a thick layer of gate electrode (I) on the entire semi-insulating GaAs substrate 11 using 4i2, using a snotzing method, it is processed into a gate electrode shape using a plasma etching method, and then it is masked. and 1
7, implant donor ions at a high concentration and heat-treat.
'Jn input, key xf+-me4. Please make sure that the J fee is ready before it arrives.

FIG. 1(a) shows the I'iW"r or 'l'i-W silicide film 12 deposited on the entire surface of the semi-++es GaAs group 11, and FIG. After processing, N implantation was performed and heat treatment was performed to form source/drain converters 16 and 17.

'I'i-W i up to 750℃, 'i-W silicide with rectifying contact 1 with GaAs at temperatures up to 850℃
Since the crystallinity of the ion-implanted layer does not change, a heat treatment using a dirt electrode is sufficient to restore the crystallinity of the ion-implanted layer.

The biggest problem with this structure is as shown in Figure 1(c).
Gate Φ: In plasma etching of the electrode 15, if the gate electrode 15 is slightly bent, the gate electrode 15
This is the case when the n-ladling area 14 contacts (1)
part 8). Kate City using plasma etching,
Since it takes 1,υ11h to process the pole 15 into a perfect shape 11, a certain 8 degree contact inevitably occurs, which causes a decrease in l1lit kE between the keys and an increase in capacity.

On the other hand, in order to resolve the above-mentioned problems, a method has been developed in which W (tungsten), which is a heat-resistant matrix material, is deposited by the four-beam method and processed by the lift-off method. . ＼V has superior heat resistance as a dart material than Ti-W silicide, and since the lift-off method is used, the gate electrode shape is single-sided, so there is less risk of expansion between the gate and source. However, the W film deposit 4
Jt technology is very difficult.

Since W is a crystalline metal with the highest melting and boiling points of all metals, it is necessary to supply a large amount of exciting force in order to emit light, which is necessary for lift-off.
In order to maintain the substrate temperature below 00°C, it is necessary to reduce the radiant heat by increasing the distance between the evaporation source and the substrate (as a result, the evaporation rate naturally slows down), and at the same time, a special device 6 for cooling the substrate is required. Become.

In addition, since W produced by vapor deposition is quite porous, the film thickness decreases due to ion bombardment during ion implantation, and its performance as a mask during ion implantation is poor, and it is expected to have poor ion stopping ability. Thick in advance (40
When attempting to deposit a W film (00 to 5,000 λ), there is a problem that not only lift-off becomes difficult, but also thorns between GaAs and W tend to occur.

This invention was made in order to solve the essential gap b'kJ point in the Selfaline structure using the above two types of heat-resistant 1'L-)-. '71'i, which is expected to significantly improve performance, yield, and reliability of GaAs high-speed logic integrated circuits.
An object of the present invention is to provide a method for manufacturing a field effect transformer.

Embodiments of the method for manufacturing a T-valve effect transistor according to the present invention will be described below with reference to the drawings. FIGS. 2(a) to 2(d) are process explanatory diagrams of the actual M11 example.

First, as shown in FIG. 2 (at), donor ions are selectively implanted onto a GaAs semi-insulating substrate 21 to form an active layer (nJ layer) 22 that reaches the chamfer part of the field effect transistor. The heat treatment for activating the active layer 22 may be carried out at this point, or may be carried out at the same time as the Y6 conversion in the subsequent n implantation.

Typical conditions for implanting this active layer 22 are S1 ions, acceleration energy 60 Kev, implantation i1.5-3Xlj)
%-2.

Thereafter, as shown in FIG. 2(a), the W film 23 is
About 3,000 people deposited the Ni film 24 continuously on all four sides using an electron beam vaporization method using about 3,000 people. There is no need to cool this removed GaAs semi-insulating substrate 21, but rather the W film 23 and the GaAs semi-insulating substrate 2
In order to improve the adhesion with 1, this GaAs semi-insulating substrate 21 is heated to 200 to 250°C.

Next, after performing the trisodarination process 21 of the dirt pattern, the Ni film 24 and the WJlψ 23 are etched by the ion milling method using the VC photoresist 25 as a mask, as shown in FIG. 2(b). The ion milling method involves colliding a parallel beam of Ar ions with approximately 500 ev], 1 ζ
11[F Directly < (more than SO'), and there is no need to draw the hem.

When the Ar ion current is 1m, 11cm, energy is 500ev, the etch speed of N'i h% 24 and WH23 is 600X/1nin, 300 people A old n
s4 presentation 1 phlegm is straight. Etching is Ni11 negative 24
completely disappears, and half of WIkG23 is etched/ends here.

This end point does not compromise accuracy much,
As long as Nil Desert 24 is completely destroyed and WIllJ23 is still left, the etching time will be ±10%.
Cheng This g4 difference is forgivable.

Then, as shown in FIG.
The film 24 and the GaAs semi-insulating substrate 21 are not etched at all, and only the W film 23 is etched. Therefore, if this plasma etching is performed sufficiently, i=J: A structure as shown in FIG. 2(c) can be obtained. Here, due to the side etching effect, W
II! The edge of +23 enters the 1st law within 1000λi 51 degrees than the 91 of Ni1l・424.

Figure 2 (When the structure of cJ is reached, Figure 2 ((1)
As shown in FIG. 1, donor ions are implanted at a high concentration (!) to form the n-implanted layer 26. Typical conditions are u: si ions, acceleration energy 120-150 Kev, implantation ht2-5 x 1013 CM-,2. To prevent V ions from being implanted in regions other than the active layer, cover with a layer of resin (3000 Ni + 100 O) with a thickness sufficient to cause a drop of more than 34'rj.
−)ru,.

f" end stage, as shown in Figure 2(d),
is removed with hydrochloric acid. N implanted layer 26 and W film 23'
A gap of about zooooX is automatically created between them, and they never come into contact. In this state, there is an insulating film (5
in2.5t3N4. AA'20. ,,Al1 cutting, etc.)
Heat treatment is performed by covering the surface with a gas of A s Jl s (Arsine) l 112 gas. The conditions are a temperature of 800 to 850°C and a time of 15 to 20 m1n. In this heat treatment, W j! In the rectifying contact characteristics between 423 and the GaAs semi-insulating substrate 21, there is almost no change in t, 1, and since the W film 23 is as thin as 1000 Å, it will not peel off.

In the above process, the gate electrode and the source and drain n-regions are formed by self-line, so after this, the source and drain electrodes are separated by 1 to 2 μm from the gate and the Au-Ge layer is placed 1-2 μm away from the gate. /Ni steamed and heat treated,
If you wire the wiring with metal such as TI/F7'A, the copper spear will be completed.

This practical example eliminates all the problems of the conventional heat-resistant case cell 7 alignment process.

First, the cross-sectional shape t of the gate electrode is almost vertical due to the use of ion milling, and the side etching effect of KWW>23 causes the problem shown in FIG. 1<c+, namely dirt 1j1. No contact between the poles and the source/drain regions occurs.

Since the extremely thick Ni1M24 is used as a temporary mask for ion implantation, the problem of poor ion blocking ability of vaporized Bw is solved, and by being able to reduce the film thickness of Wit23, vaporization Not only is this easier, but the problem of peeling during heat treatment is also improved.

The electrical resistivity of W is about 5 x 10 Ωcm, which is more than an order of magnitude lower than 'l''i-W silicide, so Wl with a thickness of 100A is
lr, 423 or r-) The size of the resistance hardly matters.

In addition, in this example, there is a problem with reproducibility, and the lift-off method, which has severe thermal constraints, is not used for dart electrode processing, and ion milling, which has excellent controllability and reproducibility, is used. The reproducibility of the process as a whole is greatly improved due to the use of this method.

In addition, in the example of Akira Tonori, an example was explained in which W was used as the commercial melting point metal and Ni was used as the second metal, but other metals having similar physical and chemical properties,
It is also possible to use alloys, intermetallic compounds and metal silicides, metal carbides, metal ferrides. Naturally, structures equivalent to this embodiment using those materials are also included within the scope of the present invention.

As described above, according to the method for manufacturing a field effect transistor of the present invention, heat-resistant first and second metal films are successively formed on a semi-insulating substrate having an active layer, and
By using the second metal film as a mask, donor ions are implanted to form the source and drain regions, and only the second metal film is removed to activate the donor ions, which eliminates problems with similar conventional processes. problem is solved, reproducibility and controllability are improved. This will greatly improve the performance, yield, and reliability of GaAs high-speed logic integrated circuits.

[Brief explanation of drawings]

Figures 1(a) to 1(e) show the conventional 'I''i-W
Or a schematic diagram of the manufacturing process of a Ti-W silicide gate GaAs field effect transistor, FIGS. 2(a) to 2
Figure (d) is a process explanatory diagram of an embodiment of the method for manufacturing a field effect transistor according to the present invention. 21... GaAs semi-insulating base, 22... active layer,
23...Wg, 24...Ni film, 25...Photoresist, 26+...N implantation layer. Patent seal person Oki Electric Industry Co., Ltd. Figure 1 Figure 2 Procedural amendment dated May 20, 1982 Kazuo Wakasugi, Commissioner of the Patent Office 1. Indication of the case Patent application No. 158024 No. 158024 2. Invention of the invention Name Field-effect transistor manufacturing method 3, relationship with the case of the person making the amendment Patent Applicant (029) Oki Electric Industry Co., Ltd. 4, Agent 5, Date of amendment order Showa Year Month I+ (
Voluntary) 6. Column 7 of the detailed description of the invention in the specification subject to amendment. Contents of the amendment 1) "Group 11" on page 3, line 10 of the specification is corrected to "substrate 11." 2) On page 7, line 4, ``material'' is corrected to ``physical.'' 3) On page 8, line 19, correct it to read "AsHs (arsine) IH2 gas" k r A8H3 (arsine)/H2 gas. 4) On page 9, line 15, "ion milling" is corrected to "ion milling". 5) On page 9, line 18, ``Source Drain'' is corrected to read ``1 source, 1 drain''. 6) On page 10, line 11, correct it to read ``Yo ni'' in place of all 1.'' 7) Correct the same page 10, line 11, ``Reproduced'' to read ``Reproduced''. -32′l

Claims (1)

[Claims] The above-mentioned second metal film is formed by sequentially forming a first metal film having a heat property of 1 and a second gold film on the surface of a semiconductor substrate having an active layer, and an ion milling method. After etching a part of the metal film and the first metal film, a step of slightly side-etching only the first metal film, and a step of removing donor ions using the -1=1 (12i42) metal film as a mask. 4. A method for manufacturing a field effect transistor, comprising the step of implanting donor ions into regions to become source and drain regions, and activating donor ions by heat treatment after removal of the iB2 metal film.