JPS5940727A - Automatic equalization system - Google Patents

Abstract

PURPOSE:To attain automatically the correction of tap coefficient even during communication, by utilizing a coding rule of an AMI signal to detect an isolated wave signal from a random input signal for correcting the tap coefficient and making the amount of correction depending on the amount of equivalent error variable to save the training period. CONSTITUTION:The input signal to a terminal 1 is the AMI signal and even if the isolated wave signal in the random input signal is changed into a consecutive signal of same polarity with the echo component according to the coding rule, the isolated wave signal is detected. A coefficient set circuit 8 discriminates the polarity of an output signal of a synthesis circuit 3, and when the isolated wave signal exists, the tap coefficient is corrected in the same way as the training signal, the amount of equivalent error is discriminated with the comparison with a threshold value, and when the amount of error is large, the amount of correction is increased. The output signal is delayed at delay circuits 4, 5, and the signal is multiplied by the said tap coefficient by coefficient devices 6, 7, and the synthesis between the result of multiplication and the input signal is performed at the synthesis circuit 3, and an equalized output signal is outputted from a terminal 2.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an automatic equalization method that detects solitary wave components from random input signals and performs equalization processing.

Prior Art and Problems The conventional bridged tap equalization method that equalizes an input signal with transmission distortion sets a training period and transmits a solitary wave signal as a training signal within this period. The tap coefficients were corrected to equalize waveform distortion, communication was started at the end of the training period, and the corrected tap coefficients were held during the communication.

At the time of this tap coefficient correction, since the amount of correction at one time is small even if the amount of equalization error is large, it was necessary to lengthen the training period in advance. That is, a training period must be set prior to communication, and it is not possible to correct equalization errors that vary during communication.

Purpose of the Invention The purpose of the present invention is to make it possible to omit the training period, to automatically perform tap coefficient correction even during communication, and to enable even faster equalization. That is. Examples will be described in detail below.

Composition of the Invention The present invention detects a solitary wave signal from a random input signal using the coding rules of the AMI signal, corrects the tap coefficient using this solitary wave signal, and calculates a constant value of the equalization error amount. The amount of correction is made variable depending on the magnitude of the difference.

Embodiment of the Invention FIG. 1 is a block diagram of main parts of an embodiment of the invention.
This example shows the case of a tap.

In the figure, 1 is an input terminal, 2 is an output terminal, 3 is a synthesis circuit, 4.5 is a delay circuit, 6.7 is a coefficient unit, and 8 is a coefficient setting circuit. The input signal applied to input terminal 1 is AMI
This AMI signal has a coding rule in which a positive polarity signal is followed by a negative polarity signal, and a negative polarity signal is followed by a positive polarity signal, and the coding is done so that the same polarity signals do not continue. It's something to do. For example, if the original signal is “101101”, the transmitted signal is +1°0,
-1. +1. O, -1 to prevent signals of the same polarity from continuing. Therefore, even if a solitary wave signal in a random input signal changes into a continuous signal of the same polarity due to an echo component, the solitary wave signal can be detected.

A solitary wave signal is a signal in which n bits before and after a +1 or -1 signal are 0, for example, 0. If +1 of +1, 0, O is a solitary wave signal, the echo component causes 0. +1. +1
．． Although it may be 0, since signals of the same polarity should never continue, this is detected as a solitary wave signal.

The coefficient setting circuit 8 judges the polarity of the output signal of the synthesis circuit 3 to detect whether it is a solitary wave signal or not. The tap coefficient is corrected, and the magnitude of the equalization error amount is determined by comparing it with a fixed threshold value, and when the equalization error amount is large, the correction amount is increased.

The output signal is delayed by the delay circuit 4.5, and the coefficient multiplier 6.
7, the multiplication with the tap coefficient set by the coefficient setting circuit 8 is performed, and the signal resulting from these multiplications and the input signal are synthesized by the synthesis circuit 3, and an equalized output signal is output from the output terminal 2. It will be output.

FIG. 2 is an explanatory diagram of a solitary wave signal and coefficient correction, and shows (7)0. +1. 0.
0 and O, -1, 0, 0 signals are shown. Note that L is the darkness value, (ab) is the absolute value, and the time (-T),
If the darkness value at (0), (T), (2T) is greater than 1. The case where it is small is indicated by O, and [pol
) is polarity, and positive polarity is 1. Negative polarity is indicated by 0, and × indicates that any polarity may be used. Further, Δ indicates the l-step coefficient correction amount, t indicates the coefficient correction period, and the upper row of each column from +al to (d) is for the first tap, and the lower row is for the second tap.

For example, (al tliil time (-T),
(0).

The absolute values (a b) of (T) and (2T) are 0. 1. 1
．． 1, the polarity (pol) is X, 1. 1. It is determined that the solitary wave signal has the same polarity as 1 or x, and the coefficient correction periods of the first and second taps are set to 2t. By setting the coefficient correction amount for unit period t to Δ, and assuming that the coefficient correction period is 2t, the coefficient correction amount becomes 2Δ
becomes.

(In the bl column, the absolute value at each equalization point [ab]
is 0, 1.1.0, the polarity (pot) is the same as the (al column), and the coefficient correction period is 2t when it is on the first tap.
, J2 tap is set to t. Therefore, the coefficient correction amount for the first tap is 2Δ, and the coefficient correction amount for the second tap is Δ
becomes. (In column C1, the absolute value (a b) at each equalization point is 0.1°0.1, the coefficient correction period of the first tap is t, and the coefficient correction period of the second tap is is set to 2t.

Also, in the (dl column), the absolute value (a b) is 0.1.0°0, and the coefficient correction period of the first and second taps is set to t. In the case of an external signal waveform, no coefficient correction is performed.

FIG. 3 is a block diagram of main parts of an embodiment of the present invention, and C
OMPl is a comparison circuit that determines the polarity of a signal and outputs a polarity signal PL, COMP2 is a comparison circuit that compares the signal with a threshold value and outputs an absolute value signal AB, and REGI is a polarity signal from the comparison circuit Co-MPI. PL to clock signal CLK
RBG2 is a shift register that shifts the absolute value signal AB according to the coding rule of the AMr signal according to the clock signal CLK; FFI to FF3 are flip-flops; CK is a clock terminal, D is a data terminal, Q, Q is an output terminal, AI
, A2 indicates input terminals, and QA to QD indicate output terminals. Also G
1 to G20 are gate circuits, CI and G2 are exclusive NOR circuits, and G3°G4. G8. G9,011 to G16 are AND circuits, G5. G6. G]7 to G20 are OR circuits, G7 is a NAND circuit, and GIO is a NOR circuit.

Also, the output signal H of the OR circuit GI9 is the second tap coefficient correction signal, the output signal I of the OR circuit G20 is the first tap coefficient correction signal, the output signal J of the OR circuit G17 is the second tap coefficient correction period signal, and the OR circuit 018 The output signal becomes the first tap coefficient correction period signal.

The absolute value signal AB of the output of the comparison circuit COMP2 is sent to the input terminal A of the shift register REG2 as the output signal B of the AND circuit 0th when the output signal of the NAND circuit G7 is "1".
2 and is shifted by the clock signal CLK applied to the clock terminal CK. When the output signals A and C of the OR circuit G5 and the OR circuit G6 are "1" and the absolute value signal AB is "1", the output signal of the NAND circuit G7 is "0".
Therefore, the AND circuit G8 is closed and the absolute value signal AB is not input to the shift register REG2. And output terminal QA-QD of shift register REG2 is o
ioo”, the output signal E of the NOR circuit GIO becomes “1”.
”.The flip-flops FFI to FF3 store the output signal “0” of the NAND circuit G7 according to the clock signal CLK to set the coefficient correction period, and the output terminal QD of the shift register REG2 becomes “1”. "When,
Flip-flop FF2. Output terminal Q of FF3 is “1”
Then, the output signal G of the AND circuit Gll and the output signal F of the AND circuit G12 each become 1''.

In FIG. 4, when the input signal IN corresponds to the signal waveform in column (al) of FIG. 2, the signals of each part are indicated by the same symbols as the signals in FIG. teeth,
This corresponds to the case where the dark value is larger at times (0), (T), and (2T), and the polarity signal PL and absolute value signal A
B are shown as PL and AB in FIG. 4, respectively. The polarity signal at each time is p(i), and the absolute value signal is y (
+) However, +=-1. o, 1.2. ...
), positive polarity is 1, negative polarity is O, and absolute value signal greater than the threshold is 1. If the small signal is 0, the contents of shift registers REGI and REG2 are REGI-QA to QD.
and REG2-QA-QD. For example, at time (0), the polarity signal p(0);1 and the absolute value signal y(0);1 are shifted to the shift registers REGI and REG2 at the rising edge of the clock signal CLK, and are shifted to the shift registers REGI and REG2 at the rising edge of the clock signal CLK. The timing is the equalization point of (T), and the polarity signal p(1); 1 is shifted to the shift register REGI, but since each output terminal QA of the shift registers REGI and RBG2 is "1", the NAND The output signal of circuit G7 becomes "0", and the absolute value signal y(1) becomes "1".
”, the AND circuit G8 is closed and the result is shifted into the shift register REG2 as y (1);0.

The same applies to the timing of the next clock signal CLK, and at time (2T), shift register REG2 (7
) Output terminal QA-QD is y (2) ;0, y (1
);0. y(0);1. y (-1): 0, which indicates "oioo" of the solitary wave signal. At that timing, the shift register REG117) output terminals QA-QC are p(2);1, p(1);1. p
(0); becomes 1.

Also, since the output terminals of the flip-flops FFI to FF3 become "1" according to the timing of the clock signal CLK, the output signal G of the AND circuit Gll and the AND circuit G1
The output signal F of No. 2 is as shown in G and F in FIG. Also, the output signal E of the NOR circuit GIO is sent to the shift register REG.
The output terminals QA-QD of 2 become "1" as shown by E in FIG. 4 at the timing of "001o". Therefore, the first. The second tap coefficient correction period J, has a two clock period “1”.
”. That is, it indicates a coefficient correction period of 2t.

Also, number 1. When the second tap coefficient correction signal [2] and [2] become "I", the correction amount Δ of one step is set. Since the coefficient correction period is 2t, the coefficient correction amount is 2Δ. This shows that the distortion of the solitary wave signal is large due to the large echo component, and in order to equalize it, the coefficient correction amount can be doubled to quickly reduce the equalization error.

As mentioned above, in the 2-tap bridged tap equalization method, a solitary wave signal is detected by determining the polarity of the first bit and the last two bits of the signal at time (0). Depending on whether the next two bits of the signal are larger or smaller than the threshold, it is determined whether the coefficient correction amount is Δ or 2Δ, and the random input signal is automatically equalized. Of course, the number of taps in the vase is not limited to two, and can of course be applied even when the vase has more taps.If the number of taps is two or more, the number of stages of the shift register may be increased. However, in order to increase the amount of coefficient correction at one time, it is sufficient to increase the number of stages of flip-flops and the number of stages of shift registers, and if a gate circuit is provided accordingly, the desired amount of coefficient correction can be set. You will be able to do that.

As described in detail, the present invention detects a solitary wave signal included in a random input signal during communication based on the AMI signal coding rule, and calculates the influence of the echo component of the solitary wave signal at time (0 ), and the equalization error amount is determined based on the absolute value signal at another time relative to time (0), and the coefficient correction amount is adjusted by one step.

This is a variable setting such as 2 steps, etc., and automatic equalization can be performed even during communication, so communication can be performed without a training period. There is an advantage that automatic equalization can be performed for various fluctuations in the temperature. Furthermore, by making the amount of coefficient correction at one time variable, automatic equalization can be performed at high speed.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a main part of an embodiment of the present invention, Fig. 2 is an explanatory diagram of signal waveforms and tap coefficient correction, and Fig. 3 is a block diagram of a main part of a tap coefficient setting circuit part of an embodiment of the invention. , FIG. 4 shows an example of a time chart for explaining the operation of FIG. 3. 1 is an input terminal, 2 is an output terminal, 3 is a synthesis circuit, 4.5 is a delay circuit, 6 and 7 are coefficient units, 8 is a tap coefficient setting circuit,
COMPI, GOMP2 are comparison circuits, REGI, REG
2 is a shift register, 01 to G20 are gate circuits, FF
I to FF3 are flip-flops. Patent applicant Fujitsu Ltd. Representative Patent Attorney Gobe Tamamushi and 3 others OOIG G OLL (J
LLI'-132-

Claims (1)

[Claims] In the bridged tap equalization method, the delayed output signal is multiplied by a tap coefficient and combined with the input signal, and the tap coefficient is automatically set according to the equalization error. comprising means for detecting a solitary wave component according to a coding rule, and means for correcting the tap coefficient by detecting the magnitude of an equalization error amount with respect to a constant dark value only when a solitary wave component is detected by the means, An automatic equalization method characterized in that the amount of correction of the tap coefficient is made variable according to the amount of equalization error.