JPS5936833B2 - semiconductor equipment - Google Patents

Description

[Detailed description of the invention] The present invention relates to a high voltage semiconductor device.

Conventionally, in order to increase the withstand voltage of a semiconductor device, a structure was created in which the junction that mainly bears the burden of withstand voltage was terminated in an annular structure formed on the main surface of the semiconductor substrate, and this groove was filled with a stabilizing material such as glass. Are known.

This structure will be explained using a planar reverse blocking thyristor as an example. In FIG. 1, the thyristor base 10 has a PE layer 11.

The NB layer 12, the PB layer 13, and the NE layer 14 are laminated in this order, and PN junctions J4, J2, and J3 are formed between each layer. Grooves 5 are formed on the main surface of the thyristor base. J4 and J2 terminate in groove 5;
is filled with crow 6. 2 is a cathode electrode, 3
is an anode electrode, 4 is a gate electrode, and T is SiO2
It is a membrane.

When a voltage is applied between electrodes 2 and 3 of this thyristor so that electrode 2 becomes negative, and electrode 4 is opened, the thyristor enters a forward blocking state. The state of the depletion layer inside the thyristor base at this time will be explained using FIG. 2. Note that the NE layer and electrodes are omitted in FIG. Figure 2a shows the case where the crow has a positive surface charge.

At this time, a depletion layer is formed as shown by diagonal lines, and the electric field strength reaches its maximum at a point 21 marked with an x in the figure, and its value becomes so large that there is a strong possibility that the forward blocking breakdown voltage of the thyristor will be broken. On the other hand, FIG. 2b shows the case where the glass has a negative surface charge.

At this time, the depletion layer is formed as shown by diagonal lines, and the electric field strength is also maximum at the point 21 marked with an x in the figure, but its value is relatively small and does not have as much of an adverse effect on the forward blocking voltage of the thyristor as on the left. However, in this case, the depletion layer is adjacent to the ordinary layer P
It may reach the E layer, and the temperature is high (100-120℃)
This results in a disadvantage that the forward blocking voltage deteriorates significantly over time. As described above, since the surface charge of glass, both positive and negative, tends to be a factor that deteriorates the characteristics of a semiconductor device, conventional efforts have been made to reduce this surface charge to as close to zero as possible.

However, the surface charge of the glass is affected by the amount of alkali metal ions such as Na+ contained in the glass, the interface state due to the stress at the interface between the semiconductor and the glass, and it has been difficult to control it to a constant value. An object of the present invention is to overcome the above-mentioned conventional drawbacks and to provide a semiconductor device with excellent breakdown voltage characteristics and reliability.

In order to achieve such an object, the present invention is characterized by having a structure in which a groove is provided on the main surface, a bond that mainly bears the withstand voltage terminates in the groove, and when this bond is negatively biased, The semiconductor layer in which the depletion layer is mainly formed has a width adjacent to the trench bottom that is approximately equal to or greater than the thickness of this semiconductor layer, and the polarity is such that the depletion layer is extended in the trench more than in the bulk. The point is that it is filled with glass that has a surface charge of .

In the present invention, the maximum electric field strength at the PN junction end exposed in the groove is reduced by making the width of the adjacent semiconductor layer, which mainly bears the burden of breakdown voltage, and the groove bottom equal to or greater than the thickness of this semiconductor layer. be.

In addition, by actively biasing the polarity of the surface charge of the glass as described above, the influence of the above-mentioned unstable factors that affect the surface charge of the glass is reduced. Embodiments of the present invention will be described below with reference to the drawings.

In the thyristor according to one embodiment of the present invention shown in FIG. 3, the junction structure of the semiconductor substrate 10 is similar to that of the conventional example shown in FIG. 1, so a detailed explanation will be omitted.
Indicated by the same reference numerals as in the figure. Note that 15 is an N+ type tunnel stopper and has a width of 20 μm. In FIG. 3, the thickness of the capacity portion of the PE layer 11 is approximately 45 μM. NB layer 1
2 has a thickness of approximately 120 μM, . The resistivity of the N layer 12 is 50Ω
−α. Each of these semiconductor layers was formed by a known thermal diffusion method using an N-type single crystal Si substrate as a starting material. In the thyristor of this embodiment, the semiconductor layer that mainly bears the burden of breakdown voltage is the NB layer 12.

The depth of the groove 5 is approximately 30 μm, and the inside of the groove 5 is made of ZnO-B.
2O3-SiO2 based glass powder was deposited by electrophoresis, preheated at 575°C for 15 minutes, fired at 680°C for 40 minutes, and then slowly cooled, and the resulting glass 6 was filled.

The polarity of the surface charge of this glass 6 was negative, and its density was about 7 x 1011 cm-2. The width of the bottom of the groove 5 outside the exposed part of the joint J2 (W in the figure) is about 120 μm, and the distance from the outer periphery of the channel stopper 15 to the PE layer 11 (W2 in the figure) is 40 μm. And so.

Note that 7 is SiO2 formed by a known steam oxidation method.
It is a membrane and has a positive surface charge. In this embodiment, glass having a negative surface charge polarity is present adjacent to the N layer 12 which mainly bears the burden of forward blocking voltage.

Therefore, the depletion layer formed in the N3 layer 12 in a forward blocking state is
The adjacent parts of the glass are more elongated than in the bulk under the influence of negative charges in the glass. As a result, electric field concentration on the surface as described in Fig. 2a does not occur,
The withstand voltage in this part is improved. FIG. 4 shows the effects of the present invention.

In the figure, the horizontal axis is W, and the vertical axis is the maximum electric field strength value at the channel stopper 15. This graph shows that the electrode 3 of the example element shown in FIG.
This is when V is applied. In this case, the electric field strength in the bulk of junction J2 is approximately 170 KV/CTn. As shown in the figure, Tl. &? M1 is the thickness of N3 layer 12 (approximately 120
μm) or more, the channel stopper 1
5 can be made smaller than in the bulk. That is, according to the present invention, there is no reduction in breakdown voltage due to concentration of electric field on the surface, which occurs in the conventional example. Note that when the polarity of the voltage applied between the electrodes 2 and 3 of the example element shown in FIG. 3 is reversed (reverse blocking state), the junction that mainly bears the withstand voltage becomes J1. In this case, the part that gives the maximum electric field strength is the bulk, and W2 is the N3 layer 12
It has been experimentally confirmed that a decrease in pressure resistance at the surface can be prevented if the thickness is approximately 1/3 or more of the thickness of the surface. In the case of this example, when the N8 layer thickness was about 120 μm and the W2 was about 40 μm, no decrease in breakdown voltage at the surface was observed. In the above embodiments, a reverse blocking three-terminal thyristor has been described, but the invention can also be applied to thyristors of other structures, transistors, and diodes. Furthermore, the effects of the present invention can be expected even if the conductivity types of each semiconductor layer are alternated between P and N. In this case, it is necessary to also reverse the polarity of the surface charge on the glass. As described above, the present invention is effective in obtaining a high voltage semiconductor device.

[Brief explanation of drawings]

Figure 1 is a diagram showing the conventional example, Figure 2 is a diagram showing the relationship between the polarity of the surface charge of the crow and the shape of the depletion layer in the conventional example,
FIG. 3 is a diagram showing a thyristor according to an embodiment of the present invention, and FIG. 4 is a diagram showing the relationship between W1 and the maximum value of the surface electric field strength in the thyristor according to the embodiment. 10... Semiconductor base, 11... PE layer, 12...
NB layer, 13...PB layer, 14...\ layer, 15...
・Channel stopper 1, 2. 3, 4...electrode, 5.
...Groove, 6...Glass, 7...SiO2 film.

Claims (1)

[Claims] 1 A PN junction is formed between a first semiconductor layer of one conductivity type and a first semiconductor layer adjacent to the first semiconductor layer.
a second semiconductor layer of a local conductivity type having a larger cross-sectional area in the direction along the junction than the first semiconductor layer; the PN junction is exposed in a groove formed on one main surface; a semiconductor substrate in which the width of the second semiconductor layer adjacent to the bottom is substantially equal to or greater than the thickness of the second semiconductor layer; and the second PN junction filled in the groove of the semiconductor substrate. 1. A semiconductor device comprising glass having a polar surface charge such that a depletion layer extends along a groove when negatively biased into a second semiconductor layer. 2. The semiconductor device according to claim 1, wherein the surface charge density of the glass is in the range of 0 to 15 x 10^1^1 cm^-^2. 3. The semiconductor device according to claim 1 or 2, wherein the second semiconductor layer extends to one main surface of the semiconductor substrate outside the groove. 4. The semiconductor device according to any one of claims 1 to 3, wherein the second semiconductor layer has a higher impurity concentration in a portion contacting the outer periphery of the trench than in other portions.