JPS5935469A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain wiring bodies of multilayer structure having the small resistance values when the wirings are to be provided on a semiconductor element by a method wherein the silicides of high melting point metals are provided on polycrystalline Si layers doped with impurities, and a heat treatment is performed to make impurities to be diffused into the silicides from the Si layers. CONSTITUTION:An n<+> type buried region 2 is provided in a p type Si substrate 1, the buried region is surrounded with an oxide film 10 having a p<+> type channel stopper region 11 as the underlay, and an n type layer 3 is made to grow epitaxially on the surrounded region 2. Then an n<+> type region 8 and a p<+> type loop region 15 are formed according to diffusion in the layer 3, and a p type region 4 and an n type region 5 positioning thereon are provided in the loop type part of the region 15. After then, the polycrystalline Si layers 7, 6 containing impurities are deposited respectively on the regions 8, 5, and the high melting point metals 40, 41 of Mo, W, Ta, etc., are adhered thereon. Then the heat treatment is performed to make impurities in the layers 7, 6 to be diffused respectively in the metals 40, 41, and the wiring bodies are made to be multilayer structure of Si and the metals to reduce the resistance values.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and more particularly to a structure of a semiconductor device that simultaneously improves the wiring structure and the characteristics of a semiconductor element.

[Technical background of the invention and its problems]

Figure 1 shows an example of impurities conventionally used to form a semiconductor region. It is a crystalline silicon layer. In addition, in the figure (II is p
type substrate, (2) is an n+ type buried region, (1υ bitaxial layer, (41*tJ' is a p type impurity region, (5)
.

(8) is an n+ type impurity region, 191 s u@T,
For I311111, the silicon oxide type region (5) is the emitter,
The p-type and p+-type regions (4), <4) constitute a base, and the n-type and n+-type regions 2), (3), and 8) constitute a vertical transistor that operates as a collector. .

Generally, the maximum oscillation frequency fTmaX % or the pace-emitter voltage VBK of a transistor is used to express the electrical characteristics of a transistor, and these are expressed as follows.

Here, fT is the new station wave number, rb: base resistance, ro:
Emitter resistance ■B base current, 1. : emitter current,
Io: Collector current, k: Portuma/constant, T: Absolute temperature, αi: Intrinsic current amplification factor, IEBO' saturation current s C
TC' is the collector capacitance.

It is well known that the resistance value is extremely large in comparison, but if a polycrystalline silicon layer is used as the wiring body for the emitter region, as in semiconductor devices with such conventional structure, In this case, the emitter resistance r8 shown in equation (2) becomes a large value, and therefore the emitter current I
The change in VHEi with respect to B becomes large, which becomes a major obstacle in circuit design for low pressure. In addition, as shown in Figure 1, the wiring for the pace area (151 is connected to the emitter wiring (6)
By straddling the structure and taking it out from both ends of the base region, the pace resistance rb can be suppressed to a low level.

Vl is improved.

FIG. 2 shows an example of a conventional semiconductor device designed to eliminate the drawbacks caused by the high resistance of the polycrystalline silicon film mentioned above.

That is, in the conventional example shown in FIG. 2, the polycrystalline silicon layer 2! J, (31), Platinum (pt) silicide layer pt on C(2), Si layer (9 countries, 1.
3(1) is provided to prevent the resistance from becoming high due to polycrystalline silicon ttti.

However, in such a conventional structure, pt.s
Since the PT of 1 reacts with the substrate and becomes unstable when processed at high temperatures (approximately 900°C or higher), in order to provide a semiconductor device with stable characteristics, the PTSI layer must be formed by polarization formation such as AJ. There was a limitation in the manufacturing process that it could only be formed at a stage close to the final process, such as a pre-process.

In addition, it is known that the high-melting-point metal Kikado layer becomes stable at high temperatures (Japanese Patent Application Laid-Open No. 57-37856).
Sufficient studies have not been made on how to apply it to semiconductor devices, for example to improve the electrical characteristics of transistors.

[Purpose of the invention]

The present invention was made in view of such conventional drawbacks, and an object of the present invention is to realize an improvement in increasing the resistance by using polycrystalline silicon/layers without imposing restrictions on the manufacturing process.

[Summary of the invention]

In the present invention, a silicide layer of a refractory metal is provided on a polycrystalline silicon layer doped with impurities, and this is used as a wiring body, thereby reducing the increase in resistance caused by the polycrystalline silicon layer. This also gives greater freedom to subsequent manufacturing processes.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a diagram showing an embodiment of the semiconductor device according to the present invention, and parts corresponding to those in FIG.

That is, in the semiconductor device according to the present invention, a high melting point metal such as molybdenum (Mo), tungsten (4
), silicide layer 141. of tantalum (Ta), etc. (edges) are provided.

Therefore, by using this multi-no structure as a wiring body, the resistance value can be reduced. Since the silicide layer of high-melting point metal is stable even at high temperatures, reliability is maintained even when high-temperature treatment is required in subsequent steps.

From FIG. 4 onwards, an embodiment of the manufacturing method will be described. On the p-type substrate +17, an n+-type buried region 2), a channel stopper region (1υ, n-type epitaxial layer!3)
), a resist Id (!tl) was formed on the surface of the semiconducting wafer on which an oxide film (11 Jl au) was formed, and boron (8) ions were implanted through the oxide film Qil formed at several hundred to 1000 Ai [. , for example 40 KeV,
Conducted at an impurity concentration of 1.7 x 10"/CI/l, 1
After heat treatment at 000°C for 5 minutes in an N2 atmosphere, the activation of boron added by ion implantation is shown in Figure L p-type region (
4) Form. Area (4) formed in this way
will be used as the base area later, but the depth of this area xi
is #0.4-0.5μ.

Layer resistance ρ8: 500Ω/mouth value.

After this, the resist layer 6ω and the oxide film 61) are removed, and the L
By the PCVD method, a polycrystalline silicon layer (6) of about 600 to 700'O with no impurity added is formed on the surface thereof (FIG. 3(B)). In this state, arsenic (As) is heated to 40KeV,
Ion implantation is performed under conditions of 1 to 1.5XIO/d.

Next, molybdenum (Mo) silicide (MoS) is applied to this surface.
i2) M (41') is approximately 3000~ by sputtering method.
It is formed with a film thickness of 4,000 people ((0) in the same figure).

Thereafter, a resist layer is formed on the surface, and this is selectively removed (45A), leaving (45B).

Then, the remaining resist layers (45A) and (4
Using 5B) as a mask, Mo5iz is patterned to selectively leave the Mo5iz layers +40 and +41). For this patterning, a plasma etching method using a mixed gas of CF4102 is used. this is,
This method utilizes the phenomenon that etching temporarily stops at the interface between MoSi2 and a polycrystalline silicon layer implanted with high concentration As ions (see specification of Japanese Patent Application No. 56-2988). After this Regis) 1114 (45
A) and (45B) were removed and annealing was performed at a temperature of 0 to 900°C for 5 to 10 minutes to remove arsenic that had been added to the surface of polycrystalline silicon #(41) by ion implantation. layer (4υ) to fully dope the polycrystalline silicon layer. After this, IIF:
kMO3: RAc: H20= 10: 20:
Approximately 0.1 g of iodine (■2
), the polycrystalline silicon layer L411 is patterned using the MoSi2 layer as a mask, and the polycrystalline silicon layers (6) and (7) are selectively left (FIG. 4(g)). In addition, here HAc is C
H3CO0H (acetic acid). After this, resist layer t
4br is formed on the surface, and boron (B) ions are implanted through the opening (46A) at 30-40 KeV, 1
The impurity concentration is ~2X10/Cd (see figure ■).
).

Note that (4n) is a thin oxide film formed prior to ion implantation to protect the surface and to improve the adhesion of the resist layer (4G).

Next, layer 14 (IL) is removed. After that, silicon oxide (S) of about 100 OA is formed as a passivation film.
i02) film (-II(), same < xooo (6) , (Diffusion of impurities from force is performed to form an n+ type impurity region (5),
+8) is formed ((G) in the same figure).

After this, 5 I
02 Opening in the II leg (48), Si3N4 film t19) (
After forming all of 47A), (47B), and (47C), an AI layer is formed on the surface and patterned to form A/wiring body 1141, 7+5) (H in the same figure). Then, in such a hinoki layer, a polycrystalline silicon layer (
6) and MoSi2 addition (4]) are used as wiring bodies from the emitter region (5). Same as Tongda,
The double structure of the polycrystalline Norifun layer (7) and the Mo5iz layer j40 is used for extraction polarization of the collector region.

Therefore, when only the impurity-doped polycrystalline silicon layer is used as the electrode, the layer resistance is about several tens of Ω to several hundreds of Ω/hole, whereas the layer resistance of %MoSi2 is about several Ω/hole, 1 2 from digit
Since the value is an order of magnitude lower, the wiring resistance can be significantly reduced by using the multilayer structure as a wiring body.

As shown in one embodiment of this manufacturing method, in the semiconductor device according to the present invention, a silicide layer of high melting point metal such as Mo5iz, which is stable even at high temperatures, is formed on the polycrystalline silicon layer. In a multilayer structure, impurity regions (e.g. emitter region) are formed by diffusion of impurities from the polycrystalline silicon layer.
Therefore, a semiconductor device can be manufactured without any restriction on the conventional manufacturing process of a semiconductor device using doped polycrystalline silicon.

In addition, the polycrystalline silicon layer is patterned using MoSi2 as a mask, and in order to selectively leave the polycrystalline silicon layer, the side etching effect of the polycrystalline silicon layer is utilized to finely process the polycrystalline silicon layer, e.g. Also suitable for patterning.

Furthermore, the polycrystalline silicon layer serves as a diffusion source for impurities, and M
oSi exists between the two-layer silicon substrate -1 and also acts as a buffer for the alloying phenomenon between these two layers, so it also has the role of preventing short-circuiting between the base and emitter of the transistor.

As an example, due to the reduction of the emitter resistance (re) of the transistor due to the presence of MoSi2, the △VBE increases by about 1oo to 200 μA for a 100 μA change in the emitter current Ie.
This can be improved to mV, making it fully applicable to low voltage circuits, for example, circuits with a power supply voltage of 3 V or less.

In the example of the manufacturing method shown in FIG. 4, a plasma etching method is used, but a reactive ion etching (RIE) method may also be used, for example.

In the case of the RIE method, a resist layer (
R with selectively leaving 45A) and (45B)
By performing IE, both the MoSi layer and the polycrystalline silicon layer can be patterned at the same time. After this, the resist layer used is removed and the resist layer shown in FIG.
The structure will be as shown in the figure, and the steps below will be carried out.

In the case of this RIE method, this polycrystalline silicon layer may be formed by a polycrystalline silicon layer (CVII as a doped polycrystalline silicon layer containing A8 from the beginning when forming 6f).

FIG. 5 is a process diagram showing another embodiment of the method for manufacturing a semiconductor device according to the present invention. In this embodiment, as shown in FIG. 6, a plan view of a semiconductor device according to the present invention (FIG. 6 (A)) and a longitudinal view taken along line BB' in FIG.
This is an example of a manufacturing method for manufacturing a semiconductor device having a structure that avoids the so-called wafer emitter structure in which the end of the emitter region t5) does not come into contact with the oxide film 0.

Incidentally, FIG. 5 and the following show the order of the steps taken along the line AA' shown in FIG. 6. Hey, first
The same reference numerals are given to the parts corresponding to those in the figure, the third drawing, and the fourth drawing, and the explanation thereof will be omitted.

First, as shown in Figure 5, with a thin oxide film 6υ formed on the wafer surface, openings (51A) and (51B) are formed in this oxide film using normal PEP technology. (B)). This opening (51A), (51
B) is the polycrystalline silicon layer 16) shown in FIG. 6(4),
(This corresponds to the contact portion between the sword and the emitter region (5) and collector region (3).

Next, a polycrystalline silicon layer and a MoSi2 layer are formed, and these are patterned by the plasma etching method or PIE method described above to form a polycrystalline silicon layer containing impurities.
(41) is selectively left ((Q) in the same figure).

Next, a fifth resist layer is formed, and this opening (53A) is formed.

(53B), poron ions are implanted into the p-type region (4) to form a p+ type region ((2) in the same figure).
.

Thereafter, in the same way as the process shown in FIG. 4, a passivation film and a null are formed. S i02 film t12 %S i 3N4 film (formed 43, p+ type region 4 by activating poron ion grand region by heat treatment at 1000°C for 20 to 30 minutes after completion), and polycrystalline silicon layer The n+ type region 5) and B8) are formed by impurity diffusion using a force of +61 and B8 (FIG. 6(G)).

Next, I) EP technology is used to form a Si02 layer (4Si, Si3N
4 layers (opening to 43 (47A), (47B),
After the formation of (47C), the A1 layer is formed and patterned to form a wiring layer +141.

(15) is formed ((II') in the same figure).

Further, FIG. 6 shows a plan view and a vertical sectional view (B) of an embodiment of a semiconductor device according to the present invention manufactured by the manufacturing method shown in FIG. 5 as described above.

Note that some elements are omitted from the figure to simplify the explanation, especially to show the relationship of contact between the silicon substrate and the polycrystalline silicon layer. That is, a polycrystalline silicon layer (6),
Contact between the f force and the n+ type sacrum 15), +8) is made through the openings (51B), (51A) of the oxide film 5υ, and similarly, contact with the A/wiring a51 is made through the openings (47B), (47).
C) Te is carried out. Further, the two-dot chain line t6+6 in the figure indicates the boundary between the thick oxide film CI[ll, which becomes the field oxide film, and the thin oxide film.

Furthermore, as shown in the same figure, according to the manufacturing method of FIG. 5, contact between the end of the n+ type emitter region (5) and the field oxide film (11) can be avoided, and a wall emitter structure can be avoided.Wall emitter If the emitter-base valley t CT E is increased, the speed characteristics of the transistor will deteriorate if the structure is avoided. , a short circuit between the collector and the so-called emitter.

It is expected that the occurrence of the collector pipe phenomenon will be significantly reduced, leading to improved reliability and yield.

Although the structure of an NPN transistor has been described in the above embodiment, it can be widely used in a PNP transistor or a structure in which it is desired to reduce wiring resistance.

〔Effect of the invention〕

As explained above, according to the present invention, the wiring for the emitter region of a semiconductor device, particularly a transistor, has a multilayer structure of a doped polycrystalline silicon layer and a silicide layer of a high melting point metal, thereby reducing emitter resistance. It is possible to significantly improve drowsiness characteristics. Furthermore, since the silicide layer of the high melting point metal is stable even at '+Q temperature, there is no restriction on heat treatment in the manufacturing process.

[Brief explanation of the drawing]

1 and 2 are diagrams showing the structure of a conventional semiconductor device, and FIGS. 3 to 6 are diagrams showing an embodiment of the structure of the semiconductor device and its manufacturing method according to the present invention. 10.16, 28, 35, 42, 47, 48.51...
・Fermentation smell 13.43.49...S i 3N4 membrane, 6
, 7... Polycrystalline silicon layer, 40.41... Refractory metal silicide layer, 14.15... Metal wiring layer. Army 1 diagram den 20 221 Kan 3 diagram 4 diagram (/1) (nA <f3) r4 diagram (C/) CD+ (E) 04 no 4M (0) Ding de diagram (A) t8) IC) No. evening diagram ([)) (E) tp+

Claims (3)

[Claims] (1) - A first semiconductor region of a conductivity type, a second semiconductor region of an opposite conductivity type formed in the first region, and a second semiconductor region formed on the second region and having the same conductivity as the second region. a polycrystalline silicon film containing a type of impurity, and a refractory metal silicide layer formed on the polycrystalline silicon film, and the polycrystalline silicon film and the refractory metal silicide layer are used as electrode wiring. A semiconductor device characterized in that it is used. (2) The semiconductor device according to claim 1, wherein the second region is formed by diffusion of impurities from the polycrystalline silicon film. (3) The semiconductor device according to claim 1 or 2, wherein the second region is formed as an emitter region of a bipolar transistor.