JPS5931735B2 - Central processing unit for data processing systems - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates generally to digital data processing systems, and more particularly to central processing units for use in such data processing systems.

A digital data processing system has three basic elements: a memory element, an input/output element, and a processing unit element.

Memory elements store information in addressable storage locations. This information includes data and instructions for processing the data. The processing unit element transfers information from the memory element. Processor elements also interpret incoming information as data or instructions. The instructions include an operation code that specifies in coded form the operation to be performed by the processing unit. An instruction may also include information specifying one or more operands. This information is called an operand specifier. Processor elements of a digital data processing system process data through programs consisting of a number of instructions.

This program is stored in a memory element. The memory elements may also contain other programs, known as subroutines, that perform specific functions. A program designated as a calling routine can utilize a subroutine by incorporating a subroutine calling instruction. There are many types of call instructions used in known data processing systems. Generally, these calling instructions are characterized by specifying the start address of the subroutine and return information that allows the subroutine to return control to the calling routine when the subroutine completes execution. When a calling routine moves into a subroutine, basic information must be provided or maintained.

For example, it is necessary to create environmental conditions that allow the subroutine to work. The addresses used by the subroutine to obtain input data and send output data are included as part of the environmental conditions for the subroutine.
Other information must also be saved, including trap enablement information and interrupt routine information. Known data processing systems typically establish this environmental condition by explicitly transferring information under the control of instructions contained in subroutines. It is also necessary to save the state of the processing unit when the calling routine executes the calling instruction.

This transfers information in specific registers that may be used by the subroutine to a memory location, as well as the contents of an argument list pointer that specifies the first position in the argument list for the subroutine. including transferring to a location. In known systems, the state of the processing unit is also explicitly saved through the use of subroutine instructions. Therefore, part of the subroutine must be devoted to instructions for storing the state of the processing unit and establishing the environment of the subroutine.

Moreover, at the end of the subroutine, the state of the machine must be re-established explicitly by using further instructions. All of these explicit information transfers occur in the form of housekeeping or overhead. The need for subroutines to include specific instructions to perform this overhead or housekeeping function complicates the subroutines. Moreover, the number of memory locations required by subroutines not only increases;
Since each instruction must be executed separately, the overall time required to execute the subroutine will also be affected.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a calling instruction and a central processing unit that responds to the instruction so as to simplify the transition operation from a calling routine to a subroutine.

Another object of the present invention is to provide an instruction for transferring operation to a subroutine that automatically stores the state of the central processing unit and allows easy restoration of this state.

Yet another object of the present invention is to provide a subroutine call instruction that automatically establishes the subroutine's environment and reestablishes the calling routine's environment.

According to the invention, a subroutine call instruction has two operand specifiers.

One specifier identifies the first position in the argument list and the other specifier identifies the first position in the subroutine.

In response to this call command, the central processing unit automatically stores the state of the central processing unit at the time of this call command by storing the contents of a predetermined register in memory. Additionally, the central processing unit automatically establishes the subroutine's environment by creating argument list indicators for the subroutine and establishing other conditions under which the subroutine operates. When the execution of the subroutine ends, a return instruction is executed. The central processing unit responds to this instruction and uses information stored during the transition to the subroutine to reestablish the environment and state of the calling routine.
The invention is particularly defined in the claims.

The above objects and other objects and advantages of the present invention will be understood from the following detailed description with reference to the accompanying drawings. General Description Referring to FIG. 1, the basic elements of a data processing system according to the present invention include a central processing unit 10, a memory device 11, and an input/output device 12.

A synchronous backplane interconnect (SBl) 14 interconnects central processing unit 10, memory devices 11, and input/output devices 12. The central processing unit 10 includes an operator's console 15, an SBI interface memory cache circuit 16, an address conversion buffer circuit 17, an instruction buffer circuit 18, and a data path. and an internal register circuit 19.

SBI interface memory cutter circuit 16 is S
It forms an interface circuit necessary to transfer information to the memory device 11 and input/output device 12 via the BLL4.
This circuit 16 also receives all data from the memory and all address translation from the buffer circuit 17. This circuit 16 includes an associative memory or cache memory. At any time data is written from the data path/internal register circuit 19 to the cutout memory of circuit 16, and
This data is also written to the corresponding location in the memory device 11. This particular embodiment of central processing unit 10 operates with virtual addresses.

The address translation buffer circuit 17 translates this virtual address into a physical address, which is used to determine whether the circuit 16 contains data from its corresponding location or This is the address used by the circuit 16 to initiate the transfer from the actual corresponding location of the device 11. The instruction buffer circuit 18 includes means for storing instructions, or portions thereof, retrieved directly from the cache memory or retrieved from the memory device 11, as described below. Operator's console 15 serves as the operator's interface.

This allows the operator to inspect and archive data, halt operation of central processing unit 10, or advance operation of central processing unit 10 through a series of program instructions. The operator console also allows the operator to initiate system operation via a bootstrap procedure and to perform various diagnostic procedures on the entire data processing system. In FIG. 1, the memory device 11 includes two memory controllers 20A and 20.
It is equipped with B.

Each memory controller is connected to multiple memory arrays. In particular, the memory controller 20A is the memory array 21
A, the memory controller 20B is connected to the memory array 21
Connected to B. The operation of memory device 11 is described in detail in US patent application Ser. No. 845,415. Various types of input/output devices 12 are shown.

I/O bus adapter 22 interconnects various input/output (1/O) devices 23, such as teletypes, to bus 14. I/
The interconnection, operation, and signal transfer between the 0 bus adapter 22 and the I/O device 23 is described in U.S. Patent No. 3,710,3.
It is disclosed in No. 24. Two separate I/O devices 12 provide secondary storage for the data processing system;
A secondary storage device bus adapter 24 and a plurality of disk drives 25 are provided.

Also shown are secondary storage bus adapter 26 and tape drive 27. The interconnection of secondary storage bus adapters 24 and 26 with their respective disk drives 25 and tape drives 27 is described in U.S. Pat.
No. 999,163.

The aforementioned US Patent Application No. 845,415 shows the interaction of each element via SBIl4.

It may be helpful in understanding the following description to generally describe these interactions and to define certain terms, including designations for data items or groups that can be processed by this particular embodiment of the invention. Become. The basic or most basic information group is a byte. This is shown in FIG. 2A and consists of 8 bits in this particular embodiment of the invention. In order of increasing information size, the next group of information is words. A word is shown in Figure 2B as consisting of two bytes. FIG. 2C shows a V1 length word consisting of two consecutive powers or four consecutive bytes! 1 is shown. FIG. 2D shows a 14x word 11 consisting of two consecutive long words or four consecutive words or eight consecutive bytes. SBIl. Any information transfer via 4 will involve long words. SBI14 is time division multiplexed and includes signal paths for sending information and control signals.

In terms of the present invention, information comprises control information and data. Control information is information that forms the basis for data processing and is used to perform control, and data is information created by a program and is the object of the processing itself. SBI
Each device connected to the network is called a nexus (coupling device).

The particular system shown in FIG. 1 includes six nexuses. A nexus is further defined with respect to its function during information exchange. At least two SBI transactions are required to exchange information between two nexuses.

During the first transaction, one nexus acts as the sending commander nexus and sends commands and address information to all nexuses. This nexus is called a transmission nexus because it drives the SBI14, and it is called a commander nexus because it sends commands and address information. All other nexuses during this transaction are receiving nexuses. However, only one receiving nexus responds with address information. This netasus is the responder nexus, which after the commander nexus sends command and address information, sends confirmation at regular intervals that it has received that information. Therefore, when the central processing unit 10 needs to retrieve data from the memory controller 20A, the central processing unit 10 acts as a commander nexus and sends a read command and address, in response to which the memory controller 20A retrieves data. It responds first as a receiving nexus and then as a responder nexus. After some time, memory controller 20A is ready to send the retrieved data to central processing unit 10.

As stated in the aforementioned patent application, the memory controller 20A is
Attempts to gain control of BIl4. Upon gaining control, memory controller 20A becomes a transmit responder nexus and transfers the requested data to central processing unit 10 via SBI14. During this transaction, central processing unit 10 is the receiving commander nexus. Similar transactions occur for any information exchange between two nexuses, but the memory controller typically only acts as a responder nexus and the central processing unit typically only acts as a commander nexus.

For purposes of the present invention, typical information exchange involves transferring instructions, operand specifiers, and related information and data to central processing unit 10 and processing processed data to memory device 10.
It will be clear that this includes reverting to 1. S.B.
The I-interface memory cutter circuit 16 is, as the term suggests, provided with a cutter or associative memory.

To transfer information to central processing unit 10, this cutlet memory is first interrogated to determine whether it already contains the required information.

If the necessary information is already included, there is no need to exchange information with the memory device 11. If it does not contain the necessary information,
The SBI interface circuit initiates a memory read operation involving a quadruple word. This information is transferred to the cutlet memory along with its physical address in memory. At the same time, this information is sent to the instruction buffer circuit 18 if an instruction is transferred, or to the data path and internal register circuit 19 if other information is transferred. When the central processing unit 10 returns information to the memory device 11, it transfers this information to the cutlet memory. and S
The BI interface memory cache circuit 16 first initiates the necessary command and address information and then the necessary SBI transactions to send the data. Details of these transactions are disclosed in US Patent Application No. 845,415.

The invention may be understood without understanding these details.
FIG. 3 shows a generalized block diagram of central processing unit 10.

Also, FIG. 3 shows the operator's console 15, SBIl4
, as well as other circuits constituting the SBI interface memory cache circuit 16, address translation buffer circuit 17, and instruction buffer circuit 18. especially,
Central processing unit 10 operates under timing established by clock signal generator 30. The specific timing will become clear from the description below in conjunction with the flowchart. RB interface memory cutout circuit 16 connects SBI14 and physical address (PA) bus 3.
The SBI control circuit 31 is connected to the SBI control circuit 2. P.A.
The bus 32 is connected to a data cache circuit 33 and a conversion buffer 3.
Connected to 4. The conversion buffer 34 converts the virtual address (A
) information and other control information into physical addresses;
This physical address is sent to the SBI controller 31 and data cache circuit 33 at the same time. Data cutter circuit 33
data from SBll or alternatively passes through the SBI controller 31
Data from other locations in 4 is stored in memory data (MD
) to other elements of central processing unit 10 via bus 35. These devices include a data path 36 and an instruction buffer decode circuit 37. Microprogram control (
The UPC bus 38 carries signals from the instruction buffer decode circuit 37 to the program control storage circuit 40.

At this time, the program control storage circuit 40 generates various control signals on the CS bus 41, which is connected to the conversion buffer 34,
It signals data path 36, instruction buffer decoder 37, and trap-to-interrupt arbitration circuit 42. These circuits and the operator's console 15 provide instruction data (ID
) communicates via bus 43 with microsequencer 44, which controls the operating sequence in response to microinstructions stored in program control storage circuit 40; Microsequencer 44 establishes a search state for obtaining instructions. A program count specifying the starting address of the next instruction to be retrieved is passed from data path 36 through translation buffer 34 to PA bus 32. If the data cutter circuit 33 contains valid information at the location corresponding to the designated physical address, the MD bus 3
5, the data is sent to the instruction buffer/decode circuit 37. When the instruction buffer/decode circuit 37 decodes an instruction, the microsequencer 44 converts the conversion buffer 3
4, thereby transferring additional data from data cache circuit 33 to registers on data path 36, or retrieving from memory device 11 or other memory locations in SBI14. After that, another data is transferred from SBI controller 31 to a register on data path 36. If an instruction requires data to be transferred to a physically addressed location, microprocessor 44 establishes the data path necessary to transfer the signal to conversion buffer 34, thereby The data cache circuit 33 and S
Data is transferred to the BI controller 31 at the same time. During such transfer, SBI controller 31 initiates information exchange with the designated memory location. FIG. 4 shows typical instructions that can be processed by central processing unit 10 shown in FIG.

The instruction shown at the top of FIG. 4 includes an operation code 50 shown as one byte long. However, it will be clear from the following description that central processing unit 10 is also capable of processing multi-byte operation codes. In this particular instruction, three operand specifiers 51, 52, 53 follow the operation code in sequence. Operand specifiers 51 and 52
each consists of one byte, and the operand specifier 53 consists of two bytes.
Consists of bytes. The format of the l-byte operand specifier is also shown in FIG. This operand specifier consists of two fields. Its high order bits constitute the register mode field and its low order bits constitute the register address field. The register address field specifies a particular register located in the data path circuit 36 shown in FIG. 3 and shown in detail in FIG. In this particular embodiment, one byte is 8
There are four bits available in each of the register mode field and the register address field, so that one of the 16 general purpose registers can be addressed by the operand specifier.
If the two most significant bits of register mode field 54 are zero (register mode 0-3), operand specifier 51 comprises an operand or literal that can constitute a data value of up to 6 bits representing decimal numbers 0 through 63. There is.

Register mode field 54 of operand specifier 53
As shown in FIG.
If the decimal number 4 is included, index mode is specified.

When a register mode field, such as register mode field 54A, specifies an index address mode, the corresponding register field 55A specifies one of the general purpose registers to be used as the index register when processing the operand specifier. do. Secondary operand specifiers are included in instructions for index address operations.

This secondary operand specifier provides the base address to which the contents of the specified index register are to be added. Index address operations are discussed in detail below. When register mode field 54 contains VV5lW, register mode address operation is designated.

In this mode, the general purpose register addressed by the register field contains the operand. For each of register modes 6, 7, and 8, the designated register contains the memory address of the operand.

In mode 6, the designated register contains the address of the operand. In register mode 7, the contents of the specified register are first decremented before checking the address, and in mode 8, the contents of the specified register are decremented after determining the address using the specified register. The content of will be increased. Register mode 9 corresponds to register mode 8, but the difference between them is that the contents of the specified register specify the memory address where the address of the operand is to be found, rather than the operand itself. Modes 10 to 15 are all displacement modes. In displacement mode, the displacement value is added to the contents of the designated register to obtain the operand address. Thus, the displacement values constitute bytes, words, or long words in modes 10, 12, and 14, respectively. Corresponding operations occur in modes 11, 13, and 15, except that the sum of the quantile and the contents of the register identifies the memory address at which the address of the operand can be found. be. In each of modes 8 through 15, the register field 55 of the operand specifier can specify a general-purpose register containing a program counter.

Specific Description 1 Initial Instruction Processing Figures 5 and 6A show data path 36 and instruction buffer decode circuitry 39 in detail.

One basic operating characteristic of this particular embodiment is that it optimizes the performance of central processing unit 10. It is not necessary to know these operations in detail to understand the invention, and therefore a general description is provided. Referring to FIG. 6A, instruction buffer decode circuit 37 includes an instruction buffer 60 that stores eight consecutive bytes. This transfer to command buffer 60 is performed in response to a signal from command buffer control circuit 61. Each byte position of instruction buffer 60 contains a validity bit position, which indicates whether the data in the remaining positions of that byte position is valid (i.e., this validity bit position is Cleared when the byte is no longer needed).

If the validity bit indicates that the data in a particular byte location or locations is no longer valid, instruction buffer control circuit 61 generates a 1BREQ signal, which is sent to data cache circuit 33 or SBI. Requests the transfer of information from the controller 31 to the command buffer 60 via the MD bus 35. Other circuitry in instruction buffer control circuit 61 detects the highest byte locations with invalid data and shifts the higher bytes into these byte locations. All high byte data is modified during these transfers. That is, the instruction buffer controller 61 causes valid bytes of the instruction buffer 60 to be stacked from higher byte positions to lower byte positions having invalid bytes or bytes that have already been used and decoded for the series of instructions; , the high end of instruction buffer 60 causes a new instruction byte to be inserted in place of the shifted byte. This instruction buffer 60 is similar to a first-in-first-out buffer, but
The operation code is always stored in the least significant byte position of the buffer, and the operand specifier byte is shifted down to the byte position one higher than the least significant byte position of the buffer to be decoded. The long word transferred via MD bus 35 (FIG. 2C) passes through multiplexer 62.

Shifting circuitry 63 is also coupled to the output of instruction buffer 60 and the input of multiplexer 62 used in shifting data bytes. Therefore, instruction buffer control circuit 61 correctly sends the appropriate information to the designated byte location of instruction buffer 60. Actually, the instruction buffer control circuit 6
1 continuously fills the instruction buffer 60 with valid data.
The responses of the central processing unit 10 to typical commands will be described below.

The instruction buffer control circuit 61 issues an instruction buffer request (IBR).
EQ) signal. At this time, the contents of the program counter register 64 of FIG. 5A, which includes the virtual address, are transferred to the virtual address (VA) latch of FIG. 5A via the B multiplexer (BMX) 65 and the arithmetic logic unit (ALU) 66 of FIG. 67 and instruction buffer address (I
BA) is transferred to latch 68. Virtual address latch 6
7 stores an instruction address in order to establish a physical address by the conversion buffer circuit 34 circuit. The instruction buffer address latch 68 is used during the transfer of information to the instruction buffer 60 (FIG. 6A) after the information from the instruction buffer 60 (FIG. 6A) has been used and the information has become obsolete. The above-described operation constitutes step A1 in FIG. In step A2, the incoming information appearing on MD bus 35 of FIG. 6A constitutes part or all of the command. This information is transferred to the instruction buffer 60 via the multiplexer 62 in response to a signal from the instruction buffer control circuit 61. At this time, byte 0 position of instruction buffer 60 contains operation code information. In this particular embodiment, each operation code consists of only one byte. However, an operation code can also consist of two or more bytes, and such multi-byte operation codes can be processed by circuits similar to those described below for decoding operand specifiers. It will be understood from the following explanation that it can be decoded. Assuming that only the byte 0 location of instruction buffer 60 contains the operation code, the byte 1 location contains some or all of the first operand specifier. Byte 0 is stored in byte 0 latch 70 which controls execution address memory 71. The contents of the byte 1 location are provided to specifier decode logic circuit 72 along with the output signal from execution address memory 71. Execution address memory 7
1 stores a table with an entry for each instruction that central processing unit 10 can execute.

The location of specific items in this table is the operation code signal from byte 0 latch 70 and execution point counter 73.
is derived by the signal from First, the execution point counter 73 is set to a reference number (eg, O). As each operand specifier is decoded, execution point counter 73 is incremented to define a new entry in the table. Each item in this table indicates whether the operand specifier indicates a location where the operand should be transferred into or out, and whether the operand specifier indicates the location where the operand is transferred into or out, and whether the operand specifier indicates the location where the operand is transferred into or out, Identify certain characteristics of operand specifiers, such as size. The signals for each selected table entry are used to control a portion of the starting address used by microsequencer 44 of FIG. 3 to establish the sequence and data path for decoding operand specifiers. It is sent to child decode logic circuit 72. The UPC bus 38 is the specifier decode logic circuit 7.
2 sends a signal to the micro sequencer 44. FIG. 6B shows execution address memory 71. Figure 2 illustrates the characteristics of operand specifiers retained in a particular embodiment of the invention.

The two low order bits from execution address memory 71 specify the type of data item contained, which typically consists of an integer or floating point number. The next two bits indicate the length of the operand. The two bits that follow indicate the action to take. The last two bits determine information regarding the access. For example, byte 0 latch 7
0 and where execution point counter 73 identifies a location containing the binary number 01001000, the corresponding operand specifier specifies the integer of the long word to be retrieved from memory.

As mentioned above, there is an input in execution address memory 71 for each operand specifier of each instruction that central processing unit 10 can process. The operation code from byte 0 latch 70 thus produces a base address, and execution point counter 73 produces a signal that is combined with the base address to sequentially identify the table entry corresponding to each operand specifier. The signals from execution address memory 71 as well as the operand specifier in byte 1 position of the instruction buffer are transferred to specifier decode logic 72 which responds to these signals to determine the start of a given operand specifier. Identify sequence addresses. The starting address of a given microinstruction in this sequence has a high order bit that depends on the instruction itself and a low order bit that depends on the nature of the information in the operand specifier. A typical lower address bit is shown in Figure 6C. In particular, if the register mode field of the operand specifier contains 1141W and the register field does not specify a program counter, the lower start address bit is FllC[W (in hexadecimal notation). This in turn sends the sequence to the microsequencer 4 starting with the Mitalo instruction located in the program control storage circuit 40 (FIG. 3) at the location identified by the start address.
Controls the position where 4 starts executing. However,
Until this information is decoded, microsequencer 44 continues to perform other operations.

In step A3 of FIG. 7, the microsequencer 44 uses the register field position of byte 1 of the instruction buffer 60 to store the contents of the register of the register memory 76 corresponding to the contents of the register field as shown in FIG. 5B. Transfer to A latch 75. Even when the register mode filter of the operand specifier specifies one of modes 0 to 3, the operand specifier includes the operand and is decoded. Mitaro sequencer 44 then begins processing the instruction's next operand specifier or begins executing the instruction. Assuming that the operand specifier does not contain a literal, the microsequencer moves from step A3 to step A4.

In this step, byte 1 of the instruction buffer 60
The contents of the register in register memory 80 identified by the location information register field are transferred to B latch 81. In this particular embodiment, A and B register memories 76 and 80 are maintained as copies of each other and constitute all general purpose registers addressable by the contents of the register field of the operand specifier. For modes other than literal mode, B latch 81 contains the address. Therefore, in step A5, the microsequencer 44 connects the B multiplexer 65 and the ALU 6.
6 and transfers the address to virtual address latch 67. Furthermore, this address is sent to the D register 85 via the shift circuit 82, DF multiplexer 83 and demultiplexer 84 without any modification. The bit corresponding to the exponent part of a floating point number is A
They are simultaneously transferred from LU 32 to index section 86 of data path 36. At step A6, the system transfers the contents of program counter 64 to program count storage register 90 so that certain instructions requiring long processing times can be aborted if an interrupt occurs. Circuitry to detect interrupt conditions and control tracking operations is then enabled. Microsequencer 44 of FIG. 3 transfers the contents of bytes 2 through 5 of instruction buffer 60 via ID bus 43 and then via Q multiplexer 91 to Q register 92.

These byte locations contain information representing potential displacement values if the operand specifier defines one of the displacement modes. In step A8 of FIG. 7A, the instruction buffer controller 61 is enabled and requests the transfer of information to continuously fill the instruction buffer 60 with valid information.

If a certain number of bytes in the instruction buffer can be cleared, this clearing operation is performed in step A9, and in step AIO the program counter 64 is incremented to compensate for the number of bytes cleared. . This tallying operation and updating of the program counter is accomplished when the relevant data is prepared in the Q register 92. In step All, central processor 10 determines whether the operand specifier contains a linear. If it contains a literal, the microsequencer 44
branches to step Al2 and provides the Q register 92 with a literal. The next operand specifier is then decoded, or if all operand specifiers have been decoded, central processing unit 10 processes the operand in response to the operation code. If the operand specifier does not contain a literal, the microsequencer 44 branches to step Al3 and completes the operand specifier decoding operation. At this point in the sequence, A latch 75 is connected to instruction buffer 60 (sixth
Contains information corresponding to register bit positions from byte 2 position in Figure A).

B latch 81, virtual address latch 67, and D register 85 contain the contents of the register selected by the register field bit in byte 1 position of instruction buffer 60. Q register 92 contains any instruction flow data that may be present, and program counter 64 contains the address of the next operand specifier. Further behavior depends on the particular instruction being decoded and the nature of the operand specifiers. There are numerous ways in which the central processing unit can perform operand specifier decoding operations. It would take a great deal of explanation to exhaustively explain each possible case. However, the operation of central processing unit 10 in accordance with the present invention may be clearly understood by considering the operation of the central processing unit in response to certain representative commands. 11 Decoding operation of operand specifier in addition instruction A. Literal and Displacement Address Modes Figure 8A shows an instruction that adds the information in two locations and places the sum in a third location, but does not affect either the first or second storage location. It shows
This is similar to what appears in the instruction buffer 60 after the instruction is retrieved in step A2 of FIG.

Is Figure 8B 1WC1? The table entry shows the information stored for the operation code associated with this instruction, which is I. The meaning of specific bit positions making up the operand specifier information is shown in FIG. 6B. The first operand specifier is 1078.

If the execution point counter 73 is 1001Y, the corresponding table entry (FIG. 8B) in the execution address memory 71 contains the following information. (1) The specifier is selected (bits 4 and 5); (2) the operand is a select number (bits 0 and 1); (3) the operand contains four crosses (bits 2 and 3). ); (4) Operand is read from memory (bits 6 and 7). Furthermore, the specifier decoding logic circuit Z starts from the byte 1 position of the instruction buffer 60.
The information transferred to the logic circuit 72 is used as the lower bit of the start address of the microsequencer 44.
Let 2 yield 1000. (See Figure 6B.) Following the sequence of Figure 7, microsequencer 44 passes this literal, ie 117', from Q register 92 through data aligner 93 and D multiplexer 84 in step B1 of Figure 8C. D register 85
Establish the data path necessary to transfer the data to the At this point, the instruction buffer controller 61 converts the 5 bytes 2 to 7 into 1
Shift to the right by the byte position and execute the execution point counter 73.
Proceed to step 101 (step B2). As is clear from the table in Figure 8B, this means that the information now in byte 1 is
This indicates that it is an operand specifier for the long word integer t to be transferred to the central processing unit 10. The system now immediately returns to the steps in Figure 7.

In step All, the second operand specification is evaluated. In combination with the information now given by the various tables of FIGS. 4, 6B, 6C and 8B, the microsequencer can determine the data paths necessary to decode the operand specifier using byte position mode addressing. response to establish the sequence. During this decode sequence, A latch 75 and B latch 81 both receive the contents of register R1 (step B3). At step B4, the Q register receives byte 3 with a byte displacement value of 1520Tt. At step B5, ALU66
is the B latch 81 containing the contents of the specified register.
and the contents of the Q register 92 containing the displacement value. In particular, the contents of the Q register 92 are passed through the RA multiplexer 94 and the A multiplexer 95 to the ALU 6.
6, while the contents of B latch 81 are sent to ALU 66 via B multiplexer 65. The sum of these two inputs represents the displacement address, which is then transferred to virtual address latch 67 and also back to Q register 92 via shift network 82, DF multiplexer 83 and Q multiplexer 91. Microsequencer 44 now enables instruction buffer controller 61 in step B6 to clear the contents of the second operand specifier and also initiates a request to obtain the second operand in step B7. Step B
At 8, the microsequencer 44 transfers the second operand from the MD bus to the D register 85 via the data aligner 96 with '>J1 and the D multiplexer 84, and the first operand is transferred to the Q register 92. This time, the microsequencer 44 advances the execution point counter 73 to the third item in the table of FIG. 8B that specifies execution (step B9).

Therefore, in the microsequencer 44, during step BIO, the ALU 66 has two addends, ie. Q register 9
2 and D register 85 (see FIG. 5C) to form an operational sum of the first and second operands received through A multiplexer 95 and B multiplexer 65 and transfer this sum to D register 85.
66. At step Bll, microsequencer 44 advances execution point counter 73 to %11111, the final state shown in FIG. 8B.

The information in the table indicates that the operand specifier specifies the memory address to which the 4-byte integer should be written! ing. The value C2 is in the byte 1 position of instruction buffer 60 and 1C1 in the register mode field defines the word displacement address. Microsequencer 44 therefore uses steps B12 through B16 to calculate the memory address and begin transferring the sum to that memory location. Upon completion of these steps, microsequencer 44 clears execution point counter 73 in step B17 and returns to the steps of FIG. 7 to begin transferring and decoding the next instruction in the sequence. B. Index Address Mode The third operand specifier shown in FIG. 8A was to define the word displacement mode.

If it is desired to use the add instruction repeatedly and store successive sums in aligned locations, the programmer may choose to use the word displacement mode but index the locations. This central processing unit can be used to create such index displacement addresses. The programmer changes the third operand specifier shown in Figure 8A to appear as the instruction in Figure 9A. This instruction identifies the R7 register index register. In particular, the first byte 4 of the instruction buffer
Locations include 11471 at the beginning of the instruction decode operation.

Step C1 in FIG. 9C corresponds to step Bll in FIG. 8C. In step C1, the execution point counter 73 of FIG. 6A is set to indicate a write operation with a long word integer.
will proceed. At this time, A latch 75 and B latch 8
1 contains the contents of register 7, Q register 92 and virtual address latch 67 contain the second operand address,
The D register 85 then contains the sum of the addition operations. At step C1, the third operand specifier occupies byte 2 through byte 5 positions of instruction buffer 60. A latch 75 therefore contains the contents of register R7, which is the designated index register. In step C2, the contents of the A latch are transferred to the A multiplexer 95 and the ALU.
The signal is transferred to the shift circuit 82 via 66. Shift circuitry 82 shifts the index value to the left by a number of positions corresponding to the length signal from execution address memory 71 during step C3.

In this case, since a long word is involved, the length field contains 11101 and the index value is shifted two positions, thereby effectively multiplying the index value by 4 and increasing the size of the long word item to be transferred. Compensate for. When a byte is transferred, no shift is performed, so the index register is effectively multiplied by 1, whereas when a quadruple word is transferred, the contents of the index register are shifted to the left three times. , effectively multiplying the index by 8 and compensating for a quadruple word size of 8 bytes. This operation therefore shifts the index value up to the size of the data item being transferred. After this digit shift, the index value is stored in a predetermined location in the C register memory 97 designated as the T7 register during step C4.

Also, the contents of the byte 1 position of the instruction buffer 60 are cleared and the value 1C2t1 is shifted to this byte 1 position. In step C5, the contents of byte positions 2 to 5 including the variable position 1014011 are transferred to Q via the 1D bus 43.
Transferred to register 92. Based on the operand specifier and operation code being processed, specifier decode logic 72 then controls the clearing of byte positions 1 through 5 of the instruction buffer in step C6 and the program counter in step C7. The number of correspondence increases. During step C8, instruction buffer controller 61 is enabled to retrieve information from the location identified by the contents of virtual address latch 67. Step C
9, the operational sum of the D register 85 is transferred to the Q register 92, and the displacement number 1101401' is sent from the Q register 92 to the D register 85. B latch 81 contains the contents of register 2, and this value is passed to the input of ALU 66 via B multiplexer 65 in step ClO. The displacement value from the D register 85 is sent to the A input. This sum constitutes the displacement address, which is D register 8
5 and virtual address latch 67, but is not used. In step Cll, the remaining byte portion of the third operand specifier is cleared. An indexing operation is then performed.

At step Cl2, the contents of register T7 of register memory 97 are transferred to C latch 98. This is the index value shifted by digits, and B during step Cl3.
It is transferred to the B input of the ALU 66 via the multiplexer 65. At the same time, the displacement address is changed from D register 85 to RA
A via multiplexer 94 and A multiplexer 95
Transferred to LU66 A personnel. An index address is then created by adding the numbers of the two inputs, and the sum, which is the index address, is transferred to D register 85. In step Cl4, this address is sent to virtual address latch 67. The operand is now in the Q register 92.

Microsequencer 44 returns this sum from Q register 92 to D register 85. Next, in step Cl4, the microsequencer 44 passes through another data aligner 96 for the operand, and then the data dump circuit 3 via the MD bus 35.
3 and memory device 11 to the location addressed by the contents of virtual address latch 67. As the final step, the execution point counter 73 and instruction buffer 6
Byte 0 position of 0 is tallied. This means that the buffer control circuit 61 outputs the next valid data in the instruction buffer 60.
and the subsequent byte position. From the foregoing description, it should be clear that index mode is not a separate and dedicated mode.

This is an extension of any of the general address modes (ie, modes 6 to 15) that refer to memory.
These general modes are shown in FIG. Index mode is implemented with a single byte specifying the index register, which can be combined with a further extension of the operand specifier of one to nine additional bytes. In this regard, the index mode can be thought of as providing a base register that includes physical offsets and an index register that includes logical offsets in some arrangement. The shift provided by the shift operation automatically compensates for the size of the data word, so the index register itself represents the logical shift of the data item regardless of its size. It will be apparent that the variable length nature of the operand specifiers further facilitates indexed mode. This is because the instruction only needs to have space for the index information when the index address is to be created. 111 Subroutine Call Instructions Figures 10A and 10B show two separate subroutine call instructions.

The call instruction in FIG. 10A is the IlCALLGll instruction, and in this particular figure has a 1-byte operation code 11FA71, followed by a 1-byte operand specifier to define the argument list, and the destination. It is followed by a 1-byte operand specifier for determining the starting position of the subroutine to be called. Figure 10B shows operation code 11FBl.
1CALLS1 call instruction is shown. The CALLG instruction shown in Figure 10A calls a subroutine when the argument list is stored in various locations in memory, and the CALLS instruction in Figure 10B ◆
The calling subroutine stores the argument list to be used in Rl, which serves as the stack pointer register.
4. Calls the subroutine if it has already transferred to the memory stack identified by the general purpose register. The agent list contains input addresses and values to be used by the subroutine and output addresses for output values produced by the subroutine. Now, number 10
Referring to Figure C-1, in step D1 central processing unit 10 evaluates the first operand specifier and, in the case of the instruction shown in Figure 10A, the argument list address or In the case of the instruction shown in FIG. 10B, the argument counter is transferred to the D register 85.

At step D2, the contents of D register 85 are transferred to Q register 92 and the destination field of the destination operand specifier is evaluated. The initial address of the resulting subroutine is sent to D register 85 and virtual address latch 67. According to one aspect of this call instruction, the initial location of the subroutine contains a subroutine mask that is interpreted as follows. Bit position 0 to 1
1 directly corresponds to general-purpose registers RO to Rll.
Each bit position in this subroutine mask is set or cleared depending on whether the contents of its corresponding general purpose register are to be saved. As can be seen, the contents of a general register are saved when a subroutine changes the contents of that general register. The other general purpose registers Rl2-Rl5 are either always saved or never saved.゛Especially, R
The l2 register constitutes an argument pointer register and its contents are always saved. Similarly, the Rl3 register constitutes a frame pointer register that contains the address of the stack of items that are flushed to the top during a subroutine call, and the Rl5 register constitutes a program counter register, the contents of which are also always saved. On the other hand, the Rl4 register constitutes a stack pointer register, and its contents are not saved. Therefore, the four most significant bit positions of the subroutine mask can be used for other purposes. In this particular example,
Although bit positions 12 and 13 are always O, they can also be used for other purposes.

Bits 14 and 15, on the other hand, establish the initial state of integer overflow on entry to the subroutine itself and the error condition flag of decimal overflow. With further reference to Figure 10C-1 and step D3, program counter 64 has been incremented to identify the first instruction following the subroutine call instruction of the calling routine.

Q register 92 is then cleared and the subroutine mask is transferred from D register 85 to T in C register memory 97.
2 register. Bit positions 12 and 13 of the subroutine mask are tested to determine if they have a value of zero. If the value is not O, an error condition exists and an appropriate trap condition occurs. Normally, when the subroutine mask is transferred to C latch 98, step D5 is executed.
The process moves to step D6. At step D7, the number of ones in the subroutine mask is counted to establish the number of general purpose registers that need to be reserved to store the state of the calling routine. Step D8 goes to the step shown in FIG. 10C-2A for the call instruction shown in FIG. 10A, or to step 10B.
For the illustrated call instruction, a branch is shown which transfers the operation to the illustrated step 10C-2B.

Assuming that the CALLG instruction shown in FIG. 10A has been decoded, it is then necessary to establish the total space in the memory stack occupied by the calling routine's state.

Five additional long words are set aside for this instruction. Therefore, in step D9, that number is added to the number of ones in the mask, the sum is converted to a number of bytes, and then used with the contents of the stack pointer register to determine the last position of the stack. used (step DlO). As mentioned above, central processing unit 10 operates as a virtually addressed machine. Therefore, steps must be taken to ensure that sufficient space exists in the memory stack allocated to the particular program being implemented to accommodate all registers being set aside. During step Dll, the contents of the Rl4 register, which is the stack pointer register, are transferred to the A and B latches 75 and 81, and in step Dl2, the contents of the Rl4 register are transferred from the bottom to the second register.
One bit is transferred to the T4 register of C register memory 97. In step D12, the stack pointer is also aligned by replacing the least significant two bits of the R14 register with zeros, thereby causing the address of this register to form a long word boundary. When information is exchanged with the memory device 11 and the cutlet memory device on the boundary of long words, this sorting procedure allows each register to be saved by one memory transfer. , and improve the overall efficiency of the instructions. Otherwise, the transfer may have to be performed twice to save each register, thereby reducing the time required to execute the normally aligned subroutine call instruction and subsequent instructions. This will increase significantly. After performing the alignment, the aligned contents of the SP register are decremented to successively identify a series of empty long word locations in memory.

This is done by the microsequencer 44 at step Dl3.
transfers the contents of program counter 64 and general-purpose registers designated by the subroutine mask to the memory stack. This step determines the location in the calling routine where instructions following the calling instruction are found;
Make sure to save general-purpose registers used by subroutines. After completing step D13, the state of the calling routine is saved and the central processing unit therefore moves to the step shown in Figure 10C-3. 10th
Figure C-2B shows the steps taken when the CALLS instruction shown in Figure 10B is decoded.

In steps D14 and D15, the central processing unit 10 again determines whether there is sufficient space in the memory stack allocated to it to store the information. The lowest two bits of the SP register are step Dl.
6, it is sent to the T4 register of the C register memory 97. In step Dl7, the C register memory 9
The address of the argument count from the T3 register of 7 is sent to the Q register 92. Furthermore, CALLG/
The CALLS flag is set. This flag is then saved on the memory stack and used later by the return instruction to control retrieval of information from the memory stack. Therefore, subroutines can be called interchangeably using the CALLG and CALLS instructions. The SP register is decremented to identify the next available location and its decremented contents are stored in D register 85. The address of the argument count in Q register 92 is then stored on the memory stack to complete the argument list. During step D18, the contents of the D register are modified and the R14 register, or stack pointer, is aligned on a long word boundary in the 5th available location. In step Dl9,
The microsequencer 44 saves the state of the called chip by saving the contents of the general purpose registers and program counters used by the subroutines to the memory stack. This is similar to step D13 of FIG. 10C-2A, which began with an aligned position in the memory stack. Now, referring to Figure 10C-3,
After the microsequencer 44 completes the transfer indicated by step D13 in FIG. 10C-2A and step D19 in FIG. 10C-2B, it proceeds to step D2O.

In particular, the contents of the R13 register, which serves as the frame pointer register, is transferred to the next available location on the memory stack. This is followed by the contents of the Rl2 register, which constitutes the argument pointer register. Step D2
At step 2, the calling routine's status flag is cleared. Here, the status flags are normal negative numbers, zeros, overflows, and carry (borrow) codes generated by arithmetic operations, and are status codes recorded in the processor status word. Next, the central processing unit 10 stores the start address of the subroutine in the T register memory 97.
1 register to the virtual address latch 67 and program counter 64 (step D23). In particular, the second operand specifier (see step D2) specifies the location of the first instruction of the subroutine that comprises the subroutine mask. The next instruction of the subroutine is located at the next position after the subroutine mask, and is the start address referred to in step D23. Step D2
At some time between and step D23 (it does not matter when), the location specified by the second operand specifier is incremented and stored in the T1 register of the C register memory. C register memory is used by the processor as a scratch pad register memory, unlike the instruction addressable A and B register memories. Next, the command buffer controller 61
begins transferring the first instruction of the subroutine to instruction buffer 60. In step D24, the microsequencer 4
4 is the old processor state word, subroutine mask,
Form a word from the stack alignment bits and CALLG/CALLS flags and store the word in the memory stack. In step D25, the microsequencer 44 transfers the contents of the stack pointer register to the R13 register as a new register frame indicator.
Next, in step D26, T of the calling routine is
The T bit is set corresponding to the bit, and in step D27, the microsequencer 44 sets the decimal and integer overflow flags based on the most significant two bits of the subroutine mask, and sets the floating under flag. You can also control other flags such as .

Here, to explain the T bit in detail, when it is set, the T bit indicates that when an error j is detected during the execution of a certain program, or more specifically during the execution of a certain instruction, the processor performs a trap operation. be able to do so.
Such errors occur, for example, when an operand specifier for an instruction specifies a memory location that does not exist, or when the user program specifies an instruction that is assigned to and can only be executed by the operating system or supervisor. This can occur in cases where Other examples of errors that can cause traps include (1) when an instruction's operand specifier specifies (for example) a byte operand and the instruction requires a word or longword operand; (3) when the stack limit is exceeded; and (3) when there is a power failure. If any of these conditions occur and the T bit is set, the processor will locate the error and notify the operator that an error has occurred, or if the condition is a power failure. Run a routine that causes the machine to save its state. In step D28, information is transferred to the Rl2 register as a new argument indicator.

If the instruction is the CALLG instruction shown in FIG. 10A, this information includes the address of the first position in the argument list containing the argument count. The command is 10B
For the CALLS instruction shown, this information includes the value of the stack pointer after the argument count operand is sent to the memory stack. In either case, the next action is to store a value of zero for the address of the state handler stored in the next available location on the memory stack. (Step D28). This reserves a location in the memory stack for the address of the next succeeding state handler and also indicates that no state handler initially exists. A condition handler is a secondary subroutine that can be called if some exceptional condition occurs during execution of the primary subroutine.

In particular, state handler subroutines are used to return the data processing system to a known state in the event of an error. For example, a status handling subroutine can be called when an attempt is made to access a file for which no subroutine exists. For such use, the subroutine stores the initial address for the state handler subroutine in a reserved location on the memory stack. After step D28, the central processing unit can begin processing the first instruction of the subroutine for which instruction buffer controller 61 began searching in step D23.

The two subroutine call instructions described above have very powerful functions. At the end of execution of any call instruction, all the information necessary to transition to and from a subroutine is correctly stored. In particular, the memory stack contains the contents of the calling routine's program counter and other information that saves the state of the calling routine. By using the argument pointer in the Rl2 register, the argument is easily retrieved and various status flags are set, thus establishing the environment for the subroutine.
The last instruction of the subroutine is a return instruction consisting of one operation code, which has no operand specifiers.

In response to this instruction, the contents of the current frame pointer in the Rl3 register are modified and returned to the Rl4 register to point to the bottom of the memory stack established by the previous call instruction, and the microsequencer 44 immediately Allows you to proceed to the beginning of the section. The contents of the next location in the memory stack are (1
) the state of the processing unit for the calling routine; and (2)
Subroutine mask and (3) subroutine is 10A
(4) the 2-bit value stored during stack alignment.

The subroutine mask is tested to determine whether bit positions 0-11 are zero. If it is zero, there is no need to restore the register, so isolate the saved subroutine master and test the two high order bits of this saved subroutine mask to reestablish the decimal and integer overflow flags. can do. If any of bits 0-11 of the subroutine mask contain a 1, those registers must be searched. The stack pointer is then properly aligned in response to the saved stack alignment bits. The central processing unit tests the bits that identify the calling instruction. 1st
When the instruction in Figure 0A is called and its return operation is complete, microsequencer 44 begins processing the next instruction in the calling routine. Otherwise, microsequencer 44 retrieves the argument count from the memory stack, increments that count by one, converts this count to a number of bytes, and adds this number of bytes to the contents of the stack pointer register. , and the sum is stored in the virtual address latch 67. Next, using the retrieved contents of the program counter, the instruction buffer controller 61 retrieves the next instruction from the memory, which is the instruction following the calling instruction of the calling routine, and performs the return operation from the calling instruction shown in FIG. 10B. can be completed. In this point,
This will be further explained with reference to FIG. Figure 11 shows the CAL
The state of the stack in response to LS and CALLG subroutine call instructions is shown. The arguments for the CALLS subroutine are stacked by the calling program. Upon return from a subroutine instruction, the following operations are performed. In response to the return command ◆, the state handler is discarded, the state word is restored to the state register, and the argument pointer,
The frame pointer and program counter are restored and the saved registers are restored to the locations specified by the subroutine mask. After this, the low order bits are restored to the stack pointer and the decimal and integer overflow fields are restored to the status register. By this time, the stack pointer points to the entire stack count word if the subroutine call instruction was a CALLS instruction (otherwise, the stack pointer points to the entire stack count word). (pointing to the top of the stack before the instruction).The processor then searches for the calling instruction pointed to by the restored program counter, and if that instruction is CAL
Determine whether it is an LS instruction or a CALLG instruction. If the instruction was a CALLG instruction, there is no argument list or count on the stack and the return instruction is complete. However, if the call instruction was a CALLS instruction 01, the processor retrieves the argument count from the stack (located at the location pointed to by the stack pointer) and Adds a counter to the contents of the stack pointer.

This sum is at the top of the stack before the argument list is pushed onto the stack by the calling program. The program counter is incremented and points to the next instruction of the calling program. The argument list is still on the stack, but the stack pointer does not need to be changed when arguments are retrieved by the calling program. Generally speaking, a data processing system has been described that includes a processing unit that decodes various types of instructions that can have any given length.

Some of these instructions include one or more operand specifiers, and each operand specifier defines the location of an operand. According to the present invention, the central processing unit is responsive to a subroutine call instruction, which automatically performs a number of functions that would otherwise have to be included by the instructions written and expressed in either the calling routine or the subroutine. Execute according to purpose. As mentioned above, the central processing unit responds to instructions by saving the state of the device while processing a calling routine, or by establishing an environment for a subroutine. All of these actions simplify the programmer's work and reduce the number of instruction locations that must be allocated to calling routines or subroutines. Although the foregoing description is limited to specific embodiments of the invention, it may be applicable to data processing systems having a variety of basic instructions or using internal circuitry other than those described herein. It will be apparent that the invention may be practiced in any other manner and still achieve some or all of the objects and advantages set forth above.

It is therefore intended that the appended claims cover all such changes and modifications that fall within the scope of the invention.

[Brief explanation of drawings]

1 is a block diagram of a digital data processing system constructed in accordance with the present invention; FIGS. 2A-2D are diagrams illustrating the format of data used in connection with a particular embodiment of the present invention; FIG. A block diagram of the central processing unit shown in Figure 1,
FIG. 4 is a diagram showing the format and organization of instructions that can be processed by the central processing unit shown in FIGS. 1 and 3, and FIGS. 6A is a block diagram of the instruction buffer and decoding circuit shown in FIG. 3, and FIGS. 6B and 6C are block diagrams of the data path shown in FIG. 6A. 7 and 7A are flowcharts useful in understanding the operation of the central processing unit shown in FIGS. 1 and 3; and FIG. 8A is a diagram illustrating the format of certain instructions. , FIG. 8B shows some information derived from this instruction, and FIGS. 8C-1, 8C-2, and 8C.
3 is a flowchart showing the operation of the central processing unit of FIGS. 1 and 3 in response to the above command; FIGS. 9A and 9B are diagrams showing another format of the command shown in FIG. 8A;
Figures 9C-1 and 9C-2 are flowcharts illustrating the operation of the central processing unit of Figures 1 and 3 in response to this modified command; Figures 10A and 10B are useful for the pop-up subroutine; 10C-1, 10C-2A, 10C-2B, 1
Figures 0C-3 and 10C-4 are flowcharts showing the operation of the central processing unit of Figures 1 and 3 in response to these commands, and Figure 11 shows the state of the stack in response to the CALLS and CALLG subroutine call commands. FIG. 10... Central processing unit, 11... Memory device, 12... Input/output device, 14...
SBI interconnect, 15...operator's console, 16...SBI interface memory cutter circuit, 17...address translation buffer circuit, 18...instruction. buffer circuit, 19.
...Data path/internal register circuit, 20A, 20
B...Memory controller, 21A, 21B...
...Memory array body, 22...1/0 bus adapter, 23...I/O device, 24, 26...
...Secondary storage device bus adapter, 25...Disk drive device, 27...Tape drive device, 30
......Clock signal generator, 31...S
BI control circuit, 33... data cutter circuit,
34...conversion buffer, 36...data path, 37...instruction buffer/decode circuit,
40...Produlum control storage circuit, 42...
...Trap-interrupt arbitration circuit, 44...
Mitaro sequencer.

Claims (1)

[Scope of Claims] 1. A central processing unit (Fig. 1: 10) for a data processing system including a memory (Fig. 1: 11) for storing instructions classified into routines, the central processing unit comprising at least one the two routines constitute a subroutine for processing information in the argument list, a first memory location of the subroutine storing a subroutine mask, and at least one other routine in said memory uses the subroutine and the operation code (FIG. 10A: FA, FIG. 10B: FB),
A first operand specifier (Figure 10A: Argument List, Figure 10B: Argument Count) for identifying the argument list indicator to be passed from the calling routine to the subroutine; a second for identifying the location of the subroutine mask in said memory;
In a central processing unit such as a calling routine containing an operand specifier (Figures 10A and 10B: Destination) of A, a plurality of general-purpose registers, specifying which of the general-purpose registers to be used by the subroutine. general-purpose register means (FIGS. 5A and 5A) including a subroutine mask in a subroutine to perform a subroutine, a program counter register for addressing instructions in said memory, and a stack pointer register for addressing locations in a memory stack containing a block of successive memory locations; 5
Figure B: 76, 80, 97) and B, instruction decoding means for decoding the instruction operation code (Figure 3:
37), and C, operand retrieval means connected to the instruction decoding means and for decoding the first operand specifier from the subroutine when the instruction decoding means decodes the operation code as a subroutine call instruction (FIG. 3: 36, 40), and D, which is connected to the general-purpose register means, the instruction decoding means and the operand retrieval means, and is designated by the stack pointer register before execution of the subroutine in response to a subroutine call instruction and a subroutine mask. control means for storing the contents of the general purpose register and the program counter register designated by the subroutine mask in the memory stack at a location and automatically retaining processor state information for the calling routine; Fig. 3: 44). 2. The memory includes a plurality of adjacent memory blocks each having a predetermined number of byte positions, the memory stores information as information blocks, and the predetermined information block is present in the adjacent memory blocks. Well,
each memory address has a first part for addressing a memory block and a second part for identifying a starting byte location for the addressed information block, the control means further comprising: i , means for storing a second part of a memory address from said stack pointer register (FIG. 3: 44, FIG. 10: D12); ii. a second part of an address in said stack pointer;
The start byte position addressed by the stack pointer register ensures that each information block of the same size or smaller than the memory block is placed in a single memory block. Means for transferring (Fig. 3: 44, 1st
0: D12). The central processing unit according to claim 1. 3 The control means (Fig. 3: 44, Fig. 10: D9, D
10, D14, D15) include means for determining whether sufficient locations in the memory stack are available for storing processor state information for a calling routine in response to a subroutine mask. The central processing unit according to scope 1. 4 includes state register means (PSW) for storing the operating state of the central processing unit;
FIG. 44, FIG. 10: D24) includes means for storing the contents of the status register means at a location designated by the stack pointer before execution of the subroutine. The central processing unit according to item 1. 5. said general purpose register means includes general purpose registers functioning as a frame pointer register R13 and an argument pointer register R12, respectively; means for transferring the contents of a pointer register and said argument pointer register to said memory stack; and for an argument list to be processed by a subroutine in response to said first operand specifier. means for obtaining an argument reference address of the memory stack; means for identifying a frame reference address in the memory stack; and transferring the argument reference address and the frame reference address to the argument pointer and the frame pointer registers, respectively. 2. A central processing unit according to claim 1, further comprising means for: