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JPS5928360A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5928360A
JPS5928360A JP13902082A JP13902082A JPS5928360A JP S5928360 A JPS5928360 A JP S5928360A JP 13902082 A JP13902082 A JP 13902082A JP 13902082 A JP13902082 A JP 13902082A JP S5928360 A JPS5928360 A JP S5928360A
Authority
JP
Japan
Prior art keywords
layer
wiring
tungsten
film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13902082A
Other languages
Japanese (ja)
Inventor
Masaharu Yorikane
頼金 雅春
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13902082A priority Critical patent/JPS5928360A/en
Publication of JPS5928360A publication Critical patent/JPS5928360A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain extremely excellent layer conduction by using gas plasma method containing F, when a layer conduction hole is provided through an electric insulation film which covers a W film. CONSTITUTION:A poly Si 24 and the W film 25, by covering the apertures of SiO2 films 22 and 23, are formed on an Si substrate 21 whereon a P or N type conductive layer has been finished in forming. An Si3N4 film 26 is superposed on the surface by plasma vapor growing method, and an aperture 27 is opened by plasma etching method using CF4. Next, an Al layer 28 is provided. This constitution enables to obtain excellent connection between the W layer and the Al layer and then generate no disconnections even in heat treatment.

Description

【発明の詳細な説明】 本発明は半導体装置の製造方法にかかり、とくに配線の
形成方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming wiring.

近年半導体装置の高密度化・高性能化の要請から高融点
金属を配線層に使用する例が多い。特にタングステン膜
は低比抵抗でかつ熱的に安定であるなどの優れたノ持性
を有している。しかしながらタングステン或は、これを
主成分とする材料(以下タングステンと総称する)を配
線層とした従来の多層配線の半導体装置では、タングス
テン層と他の配線層との間で良好な導通が得られない。
In recent years, due to the demand for higher density and higher performance of semiconductor devices, high melting point metals are often used in wiring layers. In particular, tungsten films have excellent durability such as low resistivity and thermal stability. However, in conventional multilayer wiring semiconductor devices in which wiring layers are made of tungsten or a material containing tungsten as a main component (hereinafter collectively referred to as tungsten), good conduction cannot be obtained between the tungsten layer and other wiring layers. do not have.

例えば、第1図の従来例では、タングステン配線層15
上に所望の導通開孔17を弗酸金倉む溶液で設けたシリ
コン酸化膜】6が被着されている。前記開孔17全通し
て前記タングステン配線層15に接続したアルミニウム
金属層18が形成されている。前記開孔17を通ずる導
通を調べた所1ヶ当ル数百オームあり、熱処理を施すと
、断線状態になりた。このメカニズムは明らかではない
が、前記開孔170開孔法に問題があることが考えられ
る。尚、同図で11はシリコン基板、12はシリコン酸
化膜である。
For example, in the conventional example shown in FIG.
A silicon oxide film 6 in which desired conductive holes 17 have been formed using a hydrofluoric acid solution is deposited thereon. An aluminum metal layer 18 is formed through the entire opening 17 and connected to the tungsten wiring layer 15. The conduction through the opening 17 was examined and found to be several hundred ohms per hole, and when heat treated, it became disconnected. Although this mechanism is not clear, it is thought that there is a problem with the hole 170 hole opening method. In the figure, 11 is a silicon substrate, and 12 is a silicon oxide film.

本発明は、上記従来法の欠点に鑑みなされたもので、タ
ングステンを配線層として含む多層配線構造に於ける各
層間の良好な導通を得、信頼性の高い半導体装置を得る
ことを目的とする。
The present invention has been made in view of the above-mentioned drawbacks of the conventional method, and aims to obtain good conduction between each layer in a multilayer wiring structure including tungsten as a wiring layer, and to obtain a highly reliable semiconductor device. .

本発明によればタングステン膜を被覆する電気絶縁膜に
配線層間の導通孔設置に際し、フッ素を含むガスプラズ
マ等のドライエツチングを用いることによって極めて良
好な配線層間の導通を得ることができる。
According to the present invention, extremely good conductivity between wiring layers can be obtained by using dry etching such as fluorine-containing gas plasma when forming conductive holes between wiring layers in the electrical insulating film covering the tungsten film.

本発明はよシ具体的には、所望のP型及びN型導電領域
を半導体基板の一生面に形成する工程、前記基板に電気
的に接続したタングステンを主成分とする層を少々くと
も含む配線N′(i−形成する工程、前記配線層を含み
前記第一の電気絶縁膜上に第2の電気絶縁膜を被着する
工程、前記第2の電気絶縁膜に前記配線層に通ずる開孔
を少なくとも前記配線層表面が露出する直前には、フッ
素を含むガスプラズマエツチング法によち設ける工程、
前記開孔を通して前記配線層に接続する金属層を形成す
る工程と余有する半導体装置の製造方法にある。
The present invention particularly includes forming desired P-type and N-type conductive regions on the entire surface of a semiconductor substrate, and at least a tungsten-based layer electrically connected to said substrate. a step of forming a wiring N'(i-), a step of depositing a second electrical insulating film on the first electrical insulating film including the wiring layer, and a step of forming an opening in the second electrical insulating film leading to the wiring layer; forming a hole at least immediately before the surface of the wiring layer is exposed using a gas plasma etching method containing fluorine;
The method of manufacturing a semiconductor device includes a step of forming a metal layer connected to the wiring layer through the opening, and a remaining step.

次に本発明をより良く理解するため実施例を用る半導体
材料であるシリコンを用いる。
Next, silicon, which is a semiconductor material, will be used as an example in order to better understand the present invention.

第2図A:通常の拡散・蝕刻等によりシリコン基板21
の一生面には、P型及びN型導電領域(図示せず)が形
成されている。ここでは、文献(IEEE JOURN
AL OF 5OLIL)−8TATE CL−RCU
ITS、VOL、8C−13,NO,5,0CTOBE
R1978、PP693−697)VC述べられている
PsA法により形成した。
Figure 2 A: Silicon substrate 21 is formed by normal diffusion, etching, etc.
P-type and N-type conductive regions (not shown) are formed on the entire surface of the substrate. Here, the literature (IEEE JOURN
AL OF 5OLIL)-8TATE CL-RCU
ITS, VOL, 8C-13, NO, 5, 0CTOBE
R1978, PP693-697) VC was formed by the PsA method described.

次に、文献(Solid 5tate Technol
ogy/December 1980 pp>9−82
)  に記載のタングステン(5)を気相成長し、多結
晶シリコン24上にタングステン層25を形成する。
Next, the literature (Solid 5tate Technology
ogy/December 1980 pp>9-82
) is vapor-phase grown to form a tungsten layer 25 on the polycrystalline silicon 24.

第21図B=前記タングステン層25を含む前記シリコ
ン基板21の表面にプラズマ気相成長法によりシリコン
窒化膜26を被着し、導通用開孔27を設ける。開孔2
7を設ける方法は、フッ素を含むガス、例えばテトラフ
ロロカーボン(CF4)などを用いたプラズマエツチン
グを用いる。
FIG. 21B: A silicon nitride film 26 is deposited on the surface of the silicon substrate 21 including the tungsten layer 25 by plasma vapor deposition, and a conductive hole 27 is provided. Opening hole 2
The method for providing 7 uses plasma etching using a gas containing fluorine, such as tetrafluorocarbon (CF4).

第2図C:次に金属層として例えばアルミニウムを被着
し、選択蝕刻として金属層28を形成する。
FIG. 2C: Next, a metal layer, for example aluminum, is deposited and a metal layer 28 is formed by selective etching.

このようにして得た半導体装置の開孔27全通して導通
するタングステン層25とアルミニウム金属(−28の
歩留は100パーセントであり、開孔1ヶ当りの抵抗値
は概0.5オーム以下であり、実用上間叶のない値であ
った。上記実施例ではタングステンを気相成長したが、
スノ(リングによっても良い。また、タングステン層と
アルミニウム層を絶縁分離する層間絶縁膜としてプラズ
マ気相成長シリコン基板膜を用いたが、これに限らず、
シリコン酸化膜をプラズマ気相成−良しても良く、また
哀バッタリング法で被着しても良い。また、導通用開孔
の形成方法としてのプラズマエツチング法には、一般的
にプラズマエツチングと呼称されているものの他、反応
性イオンエツチングやその他ガスプラズマによってエツ
チングするレドラノ・エツチング全てを含む。これらの
エツチング法は少なくともタングステン層が露出する直
前に適用すれば本発明の効果が発揮されるのであり、開
孔がタングステン層に到達する直前まで他の工、チング
法により蝕刻した後、これらのエツチング法を適用すれ
ば良い。
The yield of the tungsten layer 25 and the aluminum metal (-28) which are electrically conductive through all the openings 27 of the semiconductor device thus obtained is 100%, and the resistance value per opening is approximately 0.5 ohm or less. , which was a practically acceptable value.In the above example, tungsten was grown in a vapor phase, but
It is also possible to use a snow ring.Also, although a plasma vapor grown silicon substrate film was used as an interlayer insulating film to insulate and separate the tungsten layer and the aluminum layer, the present invention is not limited to this.
The silicon oxide film may be deposited by plasma vapor deposition or by a battering method. Further, the plasma etching method used as a method for forming conductive holes includes, in addition to what is generally called plasma etching, reactive ion etching and other redrano etching methods in which etching is performed using gas plasma. The effects of the present invention can be achieved by applying these etching methods at least immediately before the tungsten layer is exposed. The etching method may be applied.

また、タングステンj−に通ずる第2の金属層としては
、アルミニウムの他アルミニウムーシリコン、アルミニ
ウムー鋼その他のアルミニウム合金、或は、チタン−白
金−金などにても同様の効果が期待できる。また適用可
能な半導体装置としては、バイポーラ、モス、FETな
どほとんどの装置に適用できる。
Further, as the second metal layer connected to tungsten j-, similar effects can be expected with aluminum-silicon, aluminum-steel, other aluminum alloys, titanium-platinum-gold, etc. in addition to aluminum. Further, as applicable semiconductor devices, it is applicable to most devices such as bipolar, MOS, and FET.

以上1本発明を実施例を用いて説明したが、本発明の本
質的部分は、タングステン或は、タングステンを主成分
とする層の表面に設けた電気絶縁膜に開孔を設けるに際
し、前記タングステン或は、タングステンを主成分とす
る層に達する開孔は、少なくともフッ素を含むガスプラ
ズマ法により設けることであり、本発明の大きな効果は
、高歩留で信頼性に優れた半導体装置を提供することで
ある。
Although the present invention has been described above with reference to embodiments, the essential part of the present invention is to Alternatively, the openings reaching the layer containing tungsten as a main component are provided by a gas plasma method containing at least fluorine, and the great effect of the present invention is to provide a semiconductor device with high yield and excellent reliability. That's true.

【図面の簡単な説明】[Brief explanation of the drawing]

fJ1図は、従来装置の断面図であり、第2図は本発明
の一実施例を示す各工程の断面図である。 図に於て、 1ル、21・・・・・・シリコン、12,13,22゜
23・・i・・シリコン酸化膜、14.24・・・・・
・多結晶シリコン、15.25・・・・・・タングステ
ン、16・・・・・・シリコン酸化膜、18.28・・
・・・・アルミニウム、26・・・・・・シリコン窒化
膜、である。
Fig. fJ1 is a sectional view of a conventional device, and Fig. 2 is a sectional view of each process showing an embodiment of the present invention. In the figure, 1, 21...silicon, 12, 13, 22゜23...i...silicon oxide film, 14.24...
・Polycrystalline silicon, 15.25...Tungsten, 16...Silicon oxide film, 18.28...
. . . aluminum, 26 . . . silicon nitride film.

Claims (1)

【特許請求の範囲】[Claims] 基板の一主面上にタングJステン金主成分とするNk少
なくとも含む配線)@全形成する工程と、前記配fi!
海上に電気絶縁膜を被着する工程と、前記i11気絶縁
膜に前記配線)@に通ずる開孔を少なくとも前記配線層
表面が露出する直前には、フッ素を含むプラズマエツチ
ング法により設ける工程と、前記開孔を通して前記配線
層に接続する金属層を形成する工程とを有することを特
徴とする半導体装置の製造方法。
A step of completely forming a wiring containing at least Nk mainly composed of tungsten and gold on one main surface of the substrate, and a step of completely forming the wiring containing at least Nk mainly composed of tungsten and gold, and the above-mentioned wiring!
a step of depositing an electrical insulating film on the sea; a step of providing an opening in the i11 insulating film leading to the wiring at least immediately before the surface of the wiring layer is exposed by a plasma etching method containing fluorine; A method for manufacturing a semiconductor device, comprising the step of forming a metal layer connected to the wiring layer through the opening.
JP13902082A 1982-08-10 1982-08-10 Manufacture of semiconductor device Pending JPS5928360A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13902082A JPS5928360A (en) 1982-08-10 1982-08-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13902082A JPS5928360A (en) 1982-08-10 1982-08-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5928360A true JPS5928360A (en) 1984-02-15

Family

ID=15235598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13902082A Pending JPS5928360A (en) 1982-08-10 1982-08-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5928360A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5071789A (en) * 1985-08-02 1991-12-10 Kabushiki Kaisha Toshiba Method for forming a metal electrical connector to a surface of a semiconductor device adjacent a sidewall of insulation material with metal creep-up extending up that sidewall, and related device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5071789A (en) * 1985-08-02 1991-12-10 Kabushiki Kaisha Toshiba Method for forming a metal electrical connector to a surface of a semiconductor device adjacent a sidewall of insulation material with metal creep-up extending up that sidewall, and related device

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