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JPS5928344A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5928344A
JPS5928344A JP13900482A JP13900482A JPS5928344A JP S5928344 A JPS5928344 A JP S5928344A JP 13900482 A JP13900482 A JP 13900482A JP 13900482 A JP13900482 A JP 13900482A JP S5928344 A JPS5928344 A JP S5928344A
Authority
JP
Japan
Prior art keywords
film
polycrystalline silicon
silicon film
pattern
polycrystalline
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13900482A
Other languages
Japanese (ja)
Inventor
Kazutaka Ikeyama
池山 一孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP13900482A priority Critical patent/JPS5928344A/en
Publication of JPS5928344A publication Critical patent/JPS5928344A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To form the pattern surface into a gentle taper and eliminate the disconnection of a wiring provided thereon, by a method wherein when a polycrystalline Si film, which is formed on an insulating film provided on a semiconductor substrate, is patterned, diffusion or ion implantation is effected to an intermediate part of the thickness of the Si film, and the etching rate at the surface layer of the Si film is set to be high. CONSTITUTION:An insulating film 2 is provided on a semiconductor substrate 1, and a polycrystalline Si film 3 is deposited on the film 2. Diffusion or ion implantation is effected to an intermediate part of the thickness of the film 3 to form a polycrystalline Si film 5 different in film quality, i.e., high in etching rate. Then, a thin oxide film 6 is formed by oxidation on the surface of the film 5, and a photoresist film 7 is provided on the oxide film 6 in a predetermined pattern. Etching is effected to remove the exposed part of the film 6. With the remaining film 6 used as a mask, the different-quality film 5 and the film 3 thereunder are etched to obtain under the film 6 a laminate of the films 5 and 3 in which the film 5 on the film 3 is smaller in width than the film 3. The film 6 is removed, and an Al wiring 9 is deposited on the whole surface including the laminate through an insulating film 8.

Description

【発明の詳細な説明】 この発明は半導体装置の製造方法に係り、特に多結晶シ
リコン膜のパターン形成方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a pattern on a polycrystalline silicon film.

従来、半導体基板上の絶縁膜上に成長された多結晶シリ
コン膜のパターン形成方法は、多結晶シリコン膜表面t
−a化処理しフォトエツチング工程を経て多結晶シリコ
ン膜表面に酸化膜のパターンを形成し、該酸化膜パター
ンを保護膜として工。
Conventionally, a method for forming a pattern of a polycrystalline silicon film grown on an insulating film on a semiconductor substrate is
An oxide film pattern is formed on the surface of the polycrystalline silicon film through a -a treatment and a photoetching process, and the oxide film pattern is used as a protective film.

チング処理するか、又はフォトレジスト膜を残したまま
エツチング処理を行なっていたが、双方共、工、チング
液又は工、チングガスによる多結晶シリコン膜のエツチ
ング処理は等方性にエツチング処理されるため、保護膜
に覆われた側面方向からもエツチングされ、エツチング
後の多結晶シリコン膜パターンは、該膜厚だけ側面方向
へも進行し、工、チング加工されていfcりめ、多結晶
シリコン膜パターン形状は、非常に急峻な段差となって
いた。この為、後工程において、例えばコンタクト孔を
形成する場合、保護膜となるべき7オトレジストが多結
晶シリコン膜パターン段邪のところで薄く形成されるた
めエツチング処理時に耐えられず、ピンホールが発生し
たシ、各々トランジスタを結線し所望のトランジスタ回
路を得るためにアルミニウム配線を形成する場合には、
該多結晶シリコン膜パターンの段差の急峻な部分をアル
ミニウム配線が横切ると断線を生じたりして、半導体装
置の歩留低下を招いていた。
In both cases, the polycrystalline silicon film is etched isotropically using etching solution or etching gas. The polycrystalline silicon film pattern is also etched from the side surface covered with the protective film, and the polycrystalline silicon film pattern after etching progresses in the side face direction by the same film thickness. The shape was a very steep step. For this reason, when forming, for example, a contact hole in a later process, the photoresist that should serve as a protective film is formed thinly at the edges of the polycrystalline silicon film pattern, and cannot withstand the etching process, resulting in pinholes. , when forming aluminum wiring to connect each transistor to obtain a desired transistor circuit,
When an aluminum wiring crosses a steeply stepped portion of the polycrystalline silicon film pattern, a disconnection occurs, resulting in a decrease in the yield of semiconductor devices.

この発明の目的は、上記問題点を解決し、半導体装置の
歩留低下を誘発させない多結晶シリコン膜パターン形成
方法を提供する事にある。
An object of the present invention is to provide a polycrystalline silicon film pattern forming method that solves the above-mentioned problems and does not cause a decrease in the yield of semiconductor devices.

この発明の特徴は例えば、フォトレジスト膜あるいは酸
化膜を保護膜として、半導体基板上の絶縁膜上に成長さ
れた多結晶シリコン膜を選択的に加工し所望の多結晶シ
リコン膜パターンを形成する半導体装置の製造方法にお
いて、半導体基板上の絶縁膜上に成長された多結晶シリ
コン膜の膜厚途中まで拡散処理あるいは注入処理し、膜
質の異なる多結晶シリコン膜を形成する工程(下層部に
比して上層部のエツチング速度が速くなる様に形成する
工程)と、しかる後、多結晶シリコン膜表面を酸化処理
し、薄い酸化膜を形成し、フォトエツチング工程を経て
、多結晶シリコン膜表面に酸化膜パターンを形成する工
程と該酸化膜を保護膜として、膜質の異なる多結晶シリ
コン膜全下層膜に比して上層膜を、優勢的にエツチング
処理する工程とからなり、これ等3つの工程の組合せに
より、多結晶シリコン膜パターンの形状が、ゆるいテー
パー状に形成したことである。
The feature of this invention is, for example, that a polycrystalline silicon film grown on an insulating film on a semiconductor substrate is selectively processed using a photoresist film or an oxide film as a protective film to form a desired polycrystalline silicon film pattern. In a method for manufacturing a device, a process of performing a diffusion or implantation process halfway through the thickness of a polycrystalline silicon film grown on an insulating film on a semiconductor substrate to form a polycrystalline silicon film with different film quality (compared to the lower layer) After that, the surface of the polycrystalline silicon film is oxidized to form a thin oxide film, and through a photoetching process, the surface of the polycrystalline silicon film is oxidized. It consists of a process of forming a film pattern and a process of etching the upper layer film preferentially compared to the entire lower layer film of polycrystalline silicon film of different film quality using the oxide film as a protective film. Due to the combination, the shape of the polycrystalline silicon film pattern is formed into a gently tapered shape.

次に、この発明の一実施例につき図を用いて説明する。Next, one embodiment of the present invention will be explained using the drawings.

第1図〜第5図は、この発明の一実施例を順に説明する
ための半導体装置の断面図である。この実施例の多結晶
シリコン膜のパターン形成方法は、半導体基板1上の絶
縁膜2上に成長された多結晶シリコン膜3の膜厚途中ま
で、拡散処理あるいは注入処理4を行ない膜質の異なる
多結晶シリコン膜5を形成する工程(第1図)と、しか
る後、多結晶シリコン膜5表面を酸化処理し薄い醸化膜
6を形成し、該酸化膜6表面に7オトレジスト膜7を塗
布しく第2図)フォトエツチング工程を経て、多結晶シ
リコン膜5上に保護膜となるべき酸化膜6をパターンニ
ングする(第3図)。次に該酸化膜6全保護膜としてエ
ツチング処理するが、このとき前工程において、拡散処
理あるいは注入処理4が施され多結晶シリコン膜上層膜
5が多結晶シリコン膜下層膜3に比して、エツチング速
度が速くなる様な膜質になっているため上層膜5が下層
膜3より優勢的にエツチング処理される(第4図)。
1 to 5 are cross-sectional views of a semiconductor device for sequentially explaining one embodiment of the present invention. The method of forming a pattern of a polycrystalline silicon film in this embodiment involves performing a diffusion process or an implantation process 4 halfway through the thickness of a polycrystalline silicon film 3 grown on an insulating film 2 on a semiconductor substrate 1. Steps of forming a crystalline silicon film 5 (FIG. 1) and thereafter, oxidizing the surface of the polycrystalline silicon film 5 to form a thin oxidized film 6, and coating the surface of the oxide film 6 with a photoresist film 7. (FIG. 2) After a photo-etching process, an oxide film 6 to serve as a protective film is patterned on the polycrystalline silicon film 5 (FIG. 3). Next, the entire oxide film 6 is etched as a protective film, but at this time, in the previous step, diffusion treatment or implantation treatment 4 is performed, so that the upper polycrystalline silicon film 5 is different from the lower polycrystalline silicon film 3. Since the film quality is such that the etching rate is high, the upper film 5 is etched more dominantly than the lower film 3 (FIG. 4).

すなわち、半導体基板1の表面に絶縁膜2.多結晶シリ
コ、ン膜3を順に付着させる。次に多結晶シリコン膜3
表面に膜質の異なる多結晶シリコン膜5を形成するため
に拡散処理あるいは注入処理4全行ない、更に多結晶シ
リコン膜3.5の表面に該多結晶シリコン膜3.5を選
択エツチングする際に保護膜となるべき酸化膜6、フォ
トレジスト膜7を順に形成しフォトエツチング工程を経
て多結晶シリコン膜5表面に、酸化膜6をパターンニン
グする。しかる後、該酸化膜6を保護膜として、多結晶
シリコン膜3,5をエツチング処理する場合、上層にあ
る多結晶シリコン膜5が下層の多結晶シリコン膜3に比
してエツチングレートが速い膜質になっているため、優
勢的にエツチング処理され、結果として得られた多結晶
シリコン膜3゜5のパターン形状は、ゆるいテーパーを
生じる様にエツチング加工されている。
That is, an insulating film 2. is formed on the surface of a semiconductor substrate 1. A polycrystalline silicon film 3 is deposited in this order. Next, polycrystalline silicon film 3
In order to form a polycrystalline silicon film 5 of different film quality on the surface, diffusion treatment or implantation treatment 4 is all performed, and further protection is applied to the surface of the polycrystalline silicon film 3.5 when the polycrystalline silicon film 3.5 is selectively etched. An oxide film 6 and a photoresist film 7, which are to become a film, are sequentially formed, and a photo-etching process is performed to pattern the oxide film 6 on the surface of the polycrystalline silicon film 5. After that, when etching the polycrystalline silicon films 3 and 5 using the oxide film 6 as a protective film, the upper polycrystalline silicon film 5 has a film quality that has a higher etching rate than the lower polycrystalline silicon film 3. Because of this, the etching process is predominant, and the pattern shape of the resulting polycrystalline silicon film 3.5 is etched so as to produce a gentle taper.

この実施例によれば、半導体基板1上の絶縁膜2に付着
する多結晶シリコン膜3.5のパターンが、ゆるいテー
パー音生じる様な段を形成しているkめ、後工程におい
て絶縁膜8を形成Lコンタクト孔全開孔する場合、保護
膜となるべきフォトレジスト膜が多結晶シリコン膜パタ
ーン段邪で薄くなることがないのでエツチング処理中に
耐えられずピンホールが発生すると云う問題が発生しに
くくなる。又、この後、各々のトランジスタを結線し所
望のトランジスタを得るために、アルミニウム薄膜9を
形成し、フォトエツチング工程を経て、アルミニウム配
線9をパターンニングした場合(第5図)、多結晶シリ
コン膜3,5上を横切るアルミニウム配線9の断線の問
題も発生しに〈くなり、半導体装置の歩留・品質向上に
大きく貢献できる。
According to this embodiment, the pattern of the polycrystalline silicon film 3.5 attached to the insulating film 2 on the semiconductor substrate 1 forms steps that produce a gentle taper sound. When the L contact hole is completely opened, the photoresist film that is to serve as a protective film does not become thinner due to the thickness of the polycrystalline silicon film pattern, so there is a problem that it cannot withstand the etching process and pinholes occur. It becomes difficult. Further, after this, in order to connect each transistor to obtain a desired transistor, an aluminum thin film 9 is formed, and when the aluminum wiring 9 is patterned through a photoetching process (FIG. 5), a polycrystalline silicon film is formed. The problem of disconnection of the aluminum wiring 9 that crosses over 3 and 5 is also less likely to occur, and this can greatly contribute to improving the yield and quality of semiconductor devices.

【図面の簡単な説明】[Brief explanation of drawings]

第1図〜第5図は本発明の一実施例を工程順に示した断
面図である。 尚、図において、 1・・・・・・半導体基板、2・・・・・・酸化膜、3
・・・・・・多結晶シリコン膜、4・・・・・・注入又
は拡散処理、5・・・・・・リンドープされた多結晶シ
リコン膜(3に比して速いエツチングレートの膜質を持
つ)、6・・・・・・酸化膜、7・・・・・・フォトレ
ジスト膜、8・・・・・・絶縁膜、9・・・・・・アル
ミニウム薄膜(配線)、である。 俸 1 区 第4図 第5 図
1 to 5 are cross-sectional views showing an embodiment of the present invention in the order of steps. In the figure, 1... semiconductor substrate, 2... oxide film, 3
...Polycrystalline silicon film, 4... Implantation or diffusion treatment, 5... Phosphorus-doped polycrystalline silicon film (having a film quality with a faster etching rate than 3) ), 6... Oxide film, 7... Photoresist film, 8... Insulating film, 9... Aluminum thin film (wiring). Salary 1 Ward Figure 4 Figure 5

Claims (1)

【特許請求の範囲】[Claims] 半導体基板上の絶縁膜上に成長された多結晶シリコン膜
の上層部のエツチングレートが下層部に比して速くなる
様に膜厚の途中まで不純物をイオン注入処理あるいは拡
散処理し上層部と下層部で膜質の異なる多結晶シリコン
膜を形成する工程と、しかる後、多結晶シリコン膜表面
を酸化処理し薄い酸化膜を形成し、フォトエツチング工
程を経て多結晶シリコン膜上に酸化膜パターンを形成す
る工程と、該酸化膜を保護膜として前記膜質の異なる多
結晶シリコン膜の上層部を下層部より速く工、チング処
理する様な工程とからなフ、上記3つの工程の組合せに
より加工された多結晶シリコン膜パターンがゆるい段差
をもつ様に形成される事を特徴とする半導体装置の製造
方法。
In order to make the etching rate of the upper layer of the polycrystalline silicon film grown on the insulating film on the semiconductor substrate faster than that of the lower layer, impurities are ion-implanted or diffused to the middle of the film thickness to separate the upper and lower layers. A process of forming polycrystalline silicon films with different film qualities in different parts, then oxidizing the surface of the polycrystalline silicon film to form a thin oxide film, and forming an oxide film pattern on the polycrystalline silicon film through a photo-etching process. and a step in which the upper layer of the polycrystalline silicon film of different film quality is processed and etched more quickly than the lower layer using the oxide film as a protective film. A method for manufacturing a semiconductor device, characterized in that a polycrystalline silicon film pattern is formed with gentle steps.
JP13900482A 1982-08-10 1982-08-10 Manufacture of semiconductor device Pending JPS5928344A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13900482A JPS5928344A (en) 1982-08-10 1982-08-10 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13900482A JPS5928344A (en) 1982-08-10 1982-08-10 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5928344A true JPS5928344A (en) 1984-02-15

Family

ID=15235227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13900482A Pending JPS5928344A (en) 1982-08-10 1982-08-10 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5928344A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7411211B1 (en) * 1999-07-22 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7411211B1 (en) * 1999-07-22 2008-08-12 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device
US7626202B2 (en) 1999-07-22 2009-12-01 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device
US7956359B2 (en) 1999-07-22 2011-06-07 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device
US8258515B2 (en) 1999-07-22 2012-09-04 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device
US8368076B2 (en) 1999-07-22 2013-02-05 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device
US8624253B2 (en) 1999-07-22 2014-01-07 Semiconductor Energy Laboratory Co., Ltd. Contact structure and semiconductor device

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