JPS5928788A - Encoder of chrominance signal - Google Patents

Abstract

PURPOSE:To form a chrominance signal with high accuracy and a small sized circuit, by giving a basic clock, a double clock and data to form the three primary colors to an ROM so as to form a conversion data and A/D-converting the data. CONSTITUTION:The basic clock fsc, a clock 2fsc and the designating data of the three pkrimary colors R, G, B are inputted to an address bus of the ROM21. The ROM21 leads out a parallel output data corresponding to each address data from its output terminal and inputs the data to a D/A converter 23. A chrominance component output is led out from the converter 23. The data required for the chrominance signal is written in the ROM21 in advance and each chrominance signal component is formed with the R, G, B data. Thus, since the ROM is used to form the chrominance signal from the three primary colors and the conversion data is outputted with digital processing, the chrominance signal is formed with high accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color signal encoder device that also creates a color signal when creating a screen display signal from digital data, such as a HachiRevision game device or a teletext receiver.

When creating color signals by processing data sent through a teletext system, data corresponding to the three primary colors of RIG*B and a luminance signal are used to create color signals, but as contrasting data for R, G, and H, , has formal power as shown in Table 1 below. This is described in the NHK color television textbook published by the Japan Broadcasting Corporation. Based on this table, R
Color can be obtained by encoding the IG and B data, but the encoding device is the second one.
The one shown in the figure is known. Terminals 1, 2, and 3 are terminals to which R, G, and B digital ifs are input, and data l input here is input to a decoder 4, which is a binary-decimal converter, and is processed. The output system of decoder 4 is
For example, it is divided into the RY system and the B-Y system.

5.6 is a group of buffer circuits.

The outputs of buffer circuit groups 5 and 6 are each connected to a resistor group 7.8. The respective output terminals of the resistor group 7 are connected in common, and then connected to the voltage terminal 1 through the resistor 9 and also to the multiplier 13 . In addition, after each output terminal of the resistor group 8 is also commonly connected, the voltage terminal 12 is connected via the resistor 1o.
It is connected to the multiplier 14 as well as to the multiplier 14 .

Next, the multiplier 14 has a carrier wave (fsc = 3.53
MHz) is input through the input terminal 17, and the multiplier 14 receives l-1, carrier wave (fBc=3.58 MHz).
) is inputted via the 906 phaser 15. The outputs of the multipliers 13 and 14 are then input to the synthesizer 16.

In the above circuit, when R=Q, G21°B=O, the output Y2 of the decoder is output in negative logic. i') Yx=O, and all others are 1. As a result, the 71277 circuit 5c of the 71277 circuit groups 5 and 6,
6c operates, and in resistor groups 7 and 8, resistor 7C290
A divided voltage output and a divided voltage output of the resistors 8c and 10 are obtained.

The outputs of the respective resistor groups 7 and 8 are input to multipliers 13 and 14 as R-Y and B-Y, respectively. In multiplier 13 (
R-Y)CO5(2fsot) and (B-Y)sin(2J'8ot) are generated in the multiplier 14, and these are combined in the combiner.

In the above explanation, the case where a green color signal is created has been explained, but it can be created similarly for other colors.

According to such an encoder device, (R-Y) (B-Y) color difference signals are created by resistor division, but due to variations in the resistance values and variations in the 90° phase shifter, the color amplitude of the color signal varies by 2. If the hue deviates from the set value,
Also, when integrated circuits are used, it is disadvantageous in terms of occupied area and the like.

If we consider, for example, creating a red signal component in the above device, the waveform diagram of each part is as shown in FIG.

FIG. 5A shows the sections of the color signal, where section X is a red section and section Y is a black section. In the case of red, "R, a
, BJ=ri, o, o''. Color amplitude t shown in Table 1
In order to generate one phase θ, R-Y= 1.142・t2・tan2θ/(1-ha
n2θ)=0.78-Y21.781・(R-Y)
/lanθ = −0,3. This is output from the resistor group. (Fig. 2 (b), (C)) Then, R-Y and fso (CO5 wave) (Fig. 2 (d)) are multiplied by the multiplier 13 to produce the signal shown in Fig. 2 (f). It will be done. Further, B-Y and fsc (sin wave) (FIG. 2(e)) are multiplied by the multiplier 14 to produce the signal shown in FIG. 2(g). The multiplication outputs are then combined in a combiner 16 to obtain the color signal shown in FIG. 2(h). Although a color signal is formed in this way, the hue may deviate from the set value due to variations in resistance values.

This invention was made in view of the above circumstances, and R, c
, H to create a color signal using the binary signals of the three primary colors.
In order to achieve high accuracy with a small circuit, add the basic clock fBc, the 2fBc signal with twice its frequency, and the R, G, and H data needed to create the three primary colors to the address bus of the read-only memory. It is an object of the present invention to provide a color signal encoder device which generates conversion data and applies it to a digital-to-analog converter.

Embodiments of the present invention will be described below with reference to the drawings.

In the 8g3 diagram, 21 is a read-only memory (hereinafter referred to as RO).
fso (3.58 MHz), 2f83, and R, G, B designation data are input to the address bus of this rkOM 21. The output data path 22 is then connected to a digital-to-analog converter 23.

In the above circuit, when creating a red color signal, for example, each line of the address bus A OrAI + A
2 1 person 3 + A4 contains Figure 4(c), (
d).

(e), (f) r Data as shown in (g) is input. 1, timing 1. Then "100oO",
At timing t2, "1001 (JJ)," at timing t3, "10001," and at timing t4, "1
0011" address data is input. In this case, R
The OM 21 derives parallel output data corresponding to each address data from its output and inputs it to the desotal analog converter 23. Here, when the address data II O000J is input to the ROM 21, the r77 analog converter 2. ? Outputs parallel output data such that the output amplitude levels of are -1 and 0. This is data written in the ROM 21 in advance. Similarly, if address data "10010" is input, then r
The output amplitude level of the sotal analog converter 23 is -0,4
Outputs data such that the address data "100
It is set so that when address data 1'-10011J is input, data such as 1.0 is output, and when address data 1'-10011J is input, data such as 0.4 is output.

Therefore, in the f-sotal-analog converter 23, a waveform as shown in FIG. 4(b) is obtained, which is led out to the output terminal as a red signal component. Figure 4 (,)
indicates the section X of the red signal component and the section Y of the black signal, and in the case of black, K, rR, a, BJ as shown in the display.
= “o, o, oJ.

As described above, data necessary to obtain color signals is written in the ROM 21 in advance, and R, G.

Other color signal components can also be created by specifying the color address for the B data. Furthermore, in addition to color signals, color carrier signals (bursts) can also be generated.In this case, one additional line of the address bus is added, and for example, it is set to "1" during the burst period, and "1" is set at other times. O
Just add J and set it to generate the necessary data.

Furthermore, in this circuit, when the color changes (R, G,
When converting address data to i by H) K, ROM 2
If the output data from 1 suddenly changes, interference (dots) will occur in the luminance signal, so it may be configured as shown in FIG. 5 to eliminate this. That is, the output data of the ROM 21 is sent to the digital-to-analog converter 23 via the synthesizer 24.
Configure to add to. Furthermore, the output data of the ROM 21 is transferred to a plurality of delay circuits 25. ．． 252 etc., and the output of each delay circuit is applied to the synthesizer 24. As a result, in the synthesizer 24, for example, when the delay circuit has two stages, data addition is performed as shown in FIG. Output data as shown in FIG. 6(d) K is obtained. Therefore, the data in the color changing portion does not change its value rapidly, so that interference with the luminance signal does not occur.

As mentioned above, this invention uses a ROM when creating color signal components from R, G, and B33 original data, and outputs converted data through digital processing in the equivalent #1 calculation operation, so it is highly accurate. Therefore, it is possible to provide an n-signal encoder device with a compact circuit structure.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of a conventional color signal encoder device, Fig. 2 (a) to (h) are operation signal waveform diagrams of the device in Fig. 1, and Fig. 3
The figure is a configuration diagram showing an embodiment of the present invention, FIG. 4(a) to
(g) is an operating signal waveform diagram of the device shown in FIG. 3, FIG. 5 is a configuration diagram showing another embodiment of the present invention, and FIGS. 6(a) to (d)
5 is an explanatory diagram of the operation of the apparatus shown in FIG. 5. FIG. 2...ROM (Memory exclusively for M protrusion), 23...
・Digital analog converter. Applicant's agent Patent attorney Takehiko Suzue No. 2vA (9) R No. '3rIA Figure 4 tlb b t4

Claims (1)

[Claims] Designation data consisting of a combination of R, G, and H for designating a color signal, a basic clock with the same frequency as the color signal frequency, and a clock with a frequency twice that of this basic clock are input to the address bus, It is characterized by comprising a read-only memory that obtains converted output data corresponding to data input to this address bus, and a digital-analog converter that converts the output data of this read-only memory into digital-to-analog and outputs color signal components. color signal encoder device.