JPS5922349A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5922349A JPS5922349A JP57132553A JP13255382A JPS5922349A JP S5922349 A JPS5922349 A JP S5922349A JP 57132553 A JP57132553 A JP 57132553A JP 13255382 A JP13255382 A JP 13255382A JP S5922349 A JPS5922349 A JP S5922349A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- chip
- semiconductor
- film
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49558—Insulating layers on lead frames, e.g. bridging members
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
（ａ）発明の技術分野
本発明は半導体装置に係り、特に樹脂封止型の半導体装
置に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a semiconductor device, and particularly to a resin-sealed semiconductor device.
（ｂ）技術の背景
樹脂封止型例えば樹脂モールド型半導体集積回路装置（
ＩＣ）等に於て、集積度が向上し半導体チップが大化型
するに伴って、該半導体チップ成るいは半導体チップス
デージと樹脂パッケージとの間に生ずる応力が増大する
。そのだめに半導体チップにクラックが発生して素子特
性が劣化したり、又樹脂パッケージにクランクが発生し
て素子の信頼性が損われるという問題が生じている。(b) Technical background Resin-sealed type, for example, resin-molded semiconductor integrated circuit device (
As the degree of integration in ICs and the like increases and the size of semiconductor chips increases, the stress generated between the semiconductor chip or the semiconductor chip stage and the resin package increases. As a result, problems arise in that cracks occur in the semiconductor chip, deteriorating device characteristics, and cranks occur in the resin package, impairing the reliability of the device.
そこで、近時、上記クラックを防止する手法が、各所に
於て検討されている。Therefore, methods for preventing the above-mentioned cracks have recently been studied in various places.
（Ｃ）従来技術と問題点
上記クラック防止のために従来からよく用いられる手段
に、ワイヤ・ボンティングを終った半導体チップの主面
上にシリコーン樹脂を滴下塗布し、該シリコーン樹脂を
所定の条件でキュアして、該半導体チップの主面上に所
望の弾力性を有するシリコーン樹脂膜を形成し、該シリ
コーン樹脂膜によってモールド後半導体チップと樹脂パ
ッケージとの間に生ずる応力を吸収する方法がある。(C) Prior Art and Problems A conventionally commonly used means for preventing the above cracks is to apply a drop of silicone resin onto the main surface of a semiconductor chip that has undergone wire bonding, and to apply the silicone resin under predetermined conditions. There is a method in which a silicone resin film having a desired elasticity is formed on the main surface of the semiconductor chip by curing the semiconductor chip, and the stress generated between the semiconductor chip and the resin package after molding is absorbed by the silicone resin film. .
しかし、この方法はシリコ−ン樹脂の滴下塗布及びキュ
アの作□が煩雑なため、製造効率が著しく阻害されると
いう問題があった。However, this method has a problem in that the dropwise application of the silicone resin and the curing process are complicated, which significantly impairs production efficiency.
（ｄ）発明の目的
本発明の目的に、弾力性を有する樹脂フィルムを内部応
力の吸収体として用いることにより、半導体チップ及び
樹脂パッケージのクラック発生を防止した樹脂成形型半
導体装置を提供するにある。(d) Purpose of the Invention It is an object of the present invention to provide a resin-molded semiconductor device that prevents the occurrence of cracks in semiconductor chips and resin packages by using a resilient resin film as an internal stress absorber. .
（ｅ）発明の構成
即ち本発明は半導体装置に於て、弾力性を有する樹脂フ
ィルムが主面上に貼着された半導体チップ、或るいは樹
脂フィルムが背面上に貼着されたチップ・ステージ若し
くはその両方を具備し、樹脂成形されてなり、前記樹脂
フィルムにより半導体チップ或るいはチップ・ステージ
と樹脂パッケージとの間に生ずる応力を吸収ざせたこと
を特徴とする。(e) Structure of the Invention That is, the present invention provides a semiconductor device including a semiconductor chip having a main surface affixed with a resin film having elasticity, or a chip stage having a resin film affixed to the back surface thereof. It is characterized in that it is equipped with one or both of them and is molded with resin, and that the resin film absorbs the stress generated between the semiconductor chip or the chip stage and the resin package.
（ｆ）発明の実施例
以下、本発明を実施例について図を用いて詳細に説明す
る。(f) Embodiments of the Invention The present invention will be described in detail below with reference to embodiments.
第１図に本発明の一実施例に於ける要部透視平面図（イ
）及びＡ−Ａ’矢視リード端子延出方向断面図（ロ），
第２図は他の一実施例に於けるリード端子延出方向断面
図で、第３図は更に他の一実施例に於けるリード端子延
出方向断面図である。FIG. 1 shows a perspective plan view (a) of essential parts in an embodiment of the present invention, and a sectional view (b) in the direction of extension of the lead terminal as viewed from the A-A' arrow.
FIG. 2 is a sectional view in the direction in which the lead terminal extends in another embodiment, and FIG. 3 is a sectional view in the direction in which the lead terminal extends in yet another embodiment.
本発明の構造を有する半導体ＩＣは、例えば第１図（イ
）、（ロ）に示すように、通常通りリード・フレームの
チップ・ステージ１１上に例えば金−シリコンの合金等
からなる通常のろう材１２によって半導体ＩＣチップ１
３が固着され、該半導体ＩＣチップ１３のボンディング
・パッド（図示ぜず）とリード・フレームのリード端子
１４とが通常通り例えば金の細線等のボンディング・ワ
イヤ１５によって接続されてなっている。As shown in FIGS. 1A and 1B, for example, a semiconductor IC having the structure of the present invention is manufactured by using a conventional wax made of, for example, a gold-silicon alloy on a chip stage 11 of a lead frame. Semiconductor IC chip 1 by material 12
3 is fixed, and bonding pads (not shown) of the semiconductor IC chip 13 and lead terminals 14 of the lead frame are connected as usual by bonding wires 15 such as thin gold wires.
ぞして、該半導体ＩＣチップ１３の主面のワイヤ・ボン
ディング領域１６を除＜領域上に、２５０［℃］程度以
上の耐熱性を有し、且つ弾力性を有する厚さ２５〜１２
５（μｍ〕程度の樹脂フィルム例えばポリイミド・フィ
ルム１７が、ふつ素樹脂或るいはシリコーン樹脂，エポ
キシ樹脂等からなる熱硬化接着剤１８によって固着され
、該チップ・ステージ１１とボンディング・ワイヤ１５
が接続されたリード端子１４の先端部とを含む領域が、
通常通りシリコーン或るいはエポキシ等のモールド樹脂
からなる樹脂パッケージ１９内に成形刺入されてなって
いる。Then, on the main surface of the semiconductor IC chip 13 excluding the wire bonding area 16, a thickness of 25 to 12 mm is provided on the main surface of the semiconductor IC chip 13, which has a heat resistance of about 250 [°C] or more and has elasticity.
A resin film, for example, a polyimide film 17 with a diameter of about 5 (μm) is fixed with a thermosetting adhesive 18 made of fluorine resin, silicone resin, epoxy resin, etc., and is bonded to the chip stage 11 and the bonding wire 15.
The area including the tip of the lead terminal 14 connected to the
As usual, it is molded and inserted into a resin package 19 made of mold resin such as silicone or epoxy.
上記実施例の構造を有する半導体を形成するに際しては
通常通りダイボンダを用いてリードフレームのチップ・
ステージ１１上に半導体ＩＣチップ１２をろう付けした
後、通常のワイヤボンダを用い半導体ＩＣチップ１２の
ボンディング・パッド（図示ぜず）とリードフレームの
リード端子１４のチップ・ステージ１１に向う先端部と
の間をボンディング・ワイヤ１５により接続する。When forming a semiconductor having the structure of the above example, a die bonder is used as usual to form a chip and a lead frame.
After brazing the semiconductor IC chip 12 onto the stage 11, the bonding pads (not shown) of the semiconductor IC chip 12 and the tips of the lead terminals 14 of the lead frame facing the chip stage 11 are bonded using an ordinary wire bonder. A bonding wire 15 connects between the two.
次いで、例えばテープボンダを用い半導体ＩＣチップ１
２を１５０〜３５０〔℃〕程度に加熱した状態で、該半
導体ＩＣチップ１２のワイヤ・ボンディング領域１６の
中側領域上に、該領域を殆んど完全に覆い、且つ前記厚
さを有し下面に前記熱硬化性接着剤１８膜を有するポリ
イミド・フィルム１７を熱圧着固定する。なお、該熱圧
着の時間は１〜５〔秒〕程度である。Next, the semiconductor IC chip 1 is bonded using, for example, a tape bonder.
2 is heated to about 150 to 350 [° C.], a layer is placed on the middle region of the wire bonding region 16 of the semiconductor IC chip 12, almost completely covering the region, and having the above-mentioned thickness. The polyimide film 17 having the thermosetting adhesive 18 film on its lower surface is fixed by thermocompression. The thermocompression bonding time is approximately 1 to 5 seconds.
次いで、通常通りトランスファモ−ルド技術を用い、半
導体ＩＣチップ１２が搭載されたチップステージ１１及
びボンディング・ワイヤ１５の接続されたリ−ド端子１
４先端部を含む領域を前記樹脂パッケージ１９内に封入
する。Next, using transfer molding technology as usual, the chip stage 11 on which the semiconductor IC chip 12 is mounted and the lead terminals 1 to which the bonding wires 15 are connected are assembled.
The region including the four tips is sealed in the resin package 19.
該実施例の構造に於ては、ポリイミド・フィルム１７に
よっで半導体ＩＣチップ１３と樹脂パックージ１９間に
生ずる応力の吸収がなされ、半導体ＩＣチップ及び樹脂
バッケ−ジ１９のクラックが防止される。In the structure of this embodiment, the stress generated between the semiconductor IC chip 13 and the resin package 19 is absorbed by the polyimide film 17, and cracks in the semiconductor IC chip and the resin package 19 are prevented.
第２図は本発明の他の一実施例を示したものである。該
構造に於ては、図のようにチップ・ステージ１１の背面
に前記ポリイミド・フィルム１７が、前記熱硬化性接着
剤１８を介して熱圧着固定され、ポリイミド・フィルム
１７によってチップステージ１１と樹脂パッケージ１９
との間に生ずる応力の吸収がなされる。なお、第３図に
於て、１２はろう材、１３は半導体ＩＣチップ、１４は
リード端子、１５はボンティング・ワイヤを示している
。FIG. 2 shows another embodiment of the present invention. In this structure, as shown in the figure, the polyimide film 17 is fixed by thermocompression to the back surface of the chip stage 11 via the thermosetting adhesive 18, and the polyimide film 17 connects the chip stage 11 and the resin. package 19
The stress generated between the two is absorbed. In FIG. 3, 12 is a brazing material, 13 is a semiconductor IC chip, 14 is a lead terminal, and 15 is a bonding wire.
更に前記第１、第２の実施例の構造を兼ね備えた他の一
実施例の構造を示したのが第３図である。Furthermore, FIG. 3 shows the structure of another embodiment that combines the structures of the first and second embodiments.
同図に於て、１１は、チップ・ステージ、１２はろう材
、１３は半導体ＩＣチップ、１４はリード端子、１５は
ボンディング・ワイヤ、１７ａ、１７ｂはポリイミド・
フィルム、１８は熱硬化性接着剤、１９は樹脂パッケー
ジを示している。そして、該構造に於てはポリイミド・
フィルム１７ａ、１７ｂによって半導体ＩＣチップ１３
及びチップ・ステージ１１と樹脂パツケージ１９との間
の応力が吸収される。In the figure, 11 is a chip stage, 12 is a brazing material, 13 is a semiconductor IC chip, 14 is a lead terminal, 15 is a bonding wire, 17a, 17b is a polyimide
A film, 18 a thermosetting adhesive, and 19 a resin package. In this structure, polyimide
Semiconductor IC chip 13 by films 17a and 17b
And the stress between the chip stage 11 and the resin package 19 is absorbed.
（ｇ）発明の効果
以上説明したように本発明の構造を有する樹脂成形型の
半導体装置に於ては、半導体チップ或るいはチップ・ス
テージと樹脂パツケージとの間に生ずる応力が、ポリイ
ミド・フィルムによって吸収される。そのため例えば−
６５〜十１５０［℃］程度の過酷な温度サイクル試験を
１０００〔ザイクル〕程度行っても、樹脂クラック等の
発生は見られず、且つ従来構造に比べ効果のばらつきが
少ないことが確認された。(g) Effects of the Invention As explained above, in the resin-molded semiconductor device having the structure of the present invention, the stress generated between the semiconductor chip or chip stage and the resin package is absorbed by. Therefore, for example -
Even after conducting a severe temperature cycle test of about 65 to 1150 degrees Celsius for about 1000 cycles, no resin cracks were observed, and it was confirmed that there was less variation in effectiveness compared to conventional structures.
以上本発明によれば、樹脂成形型半導体装置に於けるチ
ップ・クラック、樹脂クラック等が防止され、その信頼
性が向上する。又本明の構造はテープボンダ等を用いて
容易に形成でき、樹脂成形型半導体装置の作業効率向上
に有効である。As described above, according to the present invention, chip cracks, resin cracks, etc. in a resin molded semiconductor device are prevented, and its reliability is improved. Further, the structure of the present invention can be easily formed using a tape bonder or the like, and is effective in improving the working efficiency of resin molded semiconductor devices.
第１図は本発明の一実施例に於ける要部透視平面図（イ
）及びＡ−Ａ’矢視リード端子延出方向断面図（ロ）、
第２図は他の一実施例に於けるリード端子延出方向断面
図、第３図は更に他の一実施例に於けるり−ド端子延出
方向断面図である。
図に於て、１１はチップ・ステージ、１２はろう材、１
３に半導体ＩＣチップ、１４はリード端子、１５はボン
ディング・ワイヤ、１６はワイヤボンディング領域、１
７，１７ａ，１７ｂはポリイミド・フィルム、１８は熱
硬化性接着剤、１９は樹脂パッケージを示す。
代理人 弁理士 松 岡 宏四郎FIG. 1 is a perspective plan view (a) of essential parts in an embodiment of the present invention, and a sectional view (b) in the direction of the lead terminal extension taken along the line A-A'.
FIG. 2 is a sectional view in the direction in which the lead terminal extends in another embodiment, and FIG. 3 is a sectional view in the direction in which the lead terminal extends in another embodiment. In the figure, 11 is the chip stage, 12 is the brazing material, 1
3 is a semiconductor IC chip, 14 is a lead terminal, 15 is a bonding wire, 16 is a wire bonding area, 1
7, 17a, and 17b are polyimide films, 18 is a thermosetting adhesive, and 19 is a resin package. Agent Patent Attorney Koshiro Matsuoka
Claims (1)
半導体チップを樹脂封止してなることを特徴とする半導
体装置。 ２、弾力性を有する樹脂フィルムを半導体チップが取付
けられるリードフレームのチップ・ステージ背面に貼着
し、該半導体チップを樹脂封止してなることを特徴とす
る半導体装置。 ３、弾力性を有する樹脂フィルムを半導体チップの主面
上及び半導体チップが取付けられるリードフレームのチ
ップ・ステージの背面上に貼着し、樹脂封止してなるこ
とを特徴とする半導体装置。[Scope of Claims] 1. A semiconductor device comprising a semiconductor chip whose main surface is encapsulated with a resin film having elasticity. 2. A semiconductor device characterized in that an elastic resin film is adhered to the back surface of a chip stage of a lead frame to which a semiconductor chip is attached, and the semiconductor chip is sealed with a resin. 3. A semiconductor device characterized in that a resin film having elasticity is adhered to the main surface of a semiconductor chip and the back surface of a chip stage of a lead frame to which the semiconductor chip is attached, and the semiconductor device is sealed with a resin.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57132553A JPS5922349A (en) | 1982-07-29 | 1982-07-29 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57132553A JPS5922349A (en) | 1982-07-29 | 1982-07-29 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5922349A true JPS5922349A (en) | 1984-02-04 |
| JPH0345542B2 JPH0345542B2 (en) | 1991-07-11 |
Family
ID=15083973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57132553A Granted JPS5922349A (en) | 1982-07-29 | 1982-07-29 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5922349A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4777520A (en) * | 1986-03-27 | 1988-10-11 | Oki Electric Industry Co. Ltd. | Heat-resistant plastic semiconductor device |
| JPS63293955A (en) * | 1987-05-27 | 1988-11-30 | Hitachi Ltd | Resin sealed type semiconductor device |
| EP0433695A2 (en) * | 1989-12-22 | 1991-06-26 | Texas Instruments Incorporated | Integrated circuit device and method to prevent cracking during surface mount |
| EP0504821A3 (en) * | 1991-03-20 | 1994-11-02 | Hitachi Ltd | Packaged semiconductor device having stress absorbing film |
| US5725977A (en) * | 1995-01-18 | 1998-03-10 | Mitsubishi Denki Kabushiki Kaisha | Method of forming fluorescent screen for color cathode-ray tube and exposure system for forming same |
| US11443958B2 (en) | 2019-12-02 | 2022-09-13 | Stmicroelectronics S.R.L. | Semiconductor device and corresponding method |
| US12148628B2 (en) | 2019-12-02 | 2024-11-19 | Stmicroelectronics S.R.L. | Semiconductor device and corresponding method |
-
1982
- 1982-07-29 JP JP57132553A patent/JPS5922349A/en active Granted
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4777520A (en) * | 1986-03-27 | 1988-10-11 | Oki Electric Industry Co. Ltd. | Heat-resistant plastic semiconductor device |
| JPS63293955A (en) * | 1987-05-27 | 1988-11-30 | Hitachi Ltd | Resin sealed type semiconductor device |
| EP0433695A2 (en) * | 1989-12-22 | 1991-06-26 | Texas Instruments Incorporated | Integrated circuit device and method to prevent cracking during surface mount |
| EP0433695A3 (en) * | 1989-12-22 | 1991-10-02 | Texas Instruments Incorporated | Integrated circuit device and method to prevent cracking during surface mount |
| EP0504821A3 (en) * | 1991-03-20 | 1994-11-02 | Hitachi Ltd | Packaged semiconductor device having stress absorbing film |
| US5406028A (en) * | 1991-03-20 | 1995-04-11 | Hitachi, Ltd. | Packaged semiconductor device having stress absorbing film |
| US5725977A (en) * | 1995-01-18 | 1998-03-10 | Mitsubishi Denki Kabushiki Kaisha | Method of forming fluorescent screen for color cathode-ray tube and exposure system for forming same |
| US11443958B2 (en) | 2019-12-02 | 2022-09-13 | Stmicroelectronics S.R.L. | Semiconductor device and corresponding method |
| US12148628B2 (en) | 2019-12-02 | 2024-11-19 | Stmicroelectronics S.R.L. | Semiconductor device and corresponding method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0345542B2 (en) | 1991-07-11 |
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