JPS5921145A - Error sample sealing device for extracted video signal - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention relates] The present invention relates to a method for compensating for loss in a zumbling preview signal, and particularly to a method for determining the loss concealment method to be used depending on the degree of loss.

[Prior art]

U.S. Patent Application No. 2511, March 1983, '36180
The specification of No. 0 describes an adaptive omission compensation method for omissions that affect a portion of a display sample of a digital data/vision image that is less than the 3F line period.O Yet another 19
March 9, 1981 “U.S. Patent Application No. 241,925 with No. 1”
The book describes a method of arranging video signal components so that the omissions occur alternately.

Q with an actual digital video tape recorder (DVIR)
1, most of the gaps are less than 1 water period long and can be hidden using the adaptation method of the former US patent application. Longer gaps may also occur, but such gaps must not produce appreciable flashes in the Screen-LK. and C may occur when an adaptive method is used to conceal an error pixel that has been detected by using the information from error pixels in the vicinity of the error pixel to be concealed, and therefore this error concealment method may cause tape loss. It is important to match the degree of

High-quality obscuring and obscuring T1 is desirable for small errors that occur relatively frequently, but it is possible to lower the quality of obscuring T1 for large errors that occur relatively infrequently. For example, in the concealment calculation method that deals with defects over the water Y line period, there are not many effective adjacent pixels that can be used to obtain good replacement pixels;
, there are many small gaps.

This is so that it will remain.

Therefore, the concealment method depends on the degree of omission, and the mu-missage concealment method is preferable.

[Disclosure of the invention]

The device according to the present invention is for concealing an erroneous sample of an extracted video signal, and generates several estimated values of the erroneous sample using various methods using neighboring samples of the erroneous sample. a means for determining error samples, if any, in neighboring samples used for deriving this estimation and value; and a means for determining the error samples, if any, among the estimated values, using the best estimation method that did not use error samples when generating the estimated values. and means for selecting the generated ones.

[Embodiments of the invention]

First, looking at Figure 2, we see that the incorrect reference pixel vM(n) (x
) is surrounded by effective pixels (indicated by ○), but
This button is not necessary for the operation of this invention.

The subscript T%M%B indicates the upper, middle, and lower scanning lines, respectively.
:(7), /1ilJ, ka. , the column to the left of one sampling period, the column of reference pixels, and the column one sampling period to the right from the column of reference pixels represent pixels □.

, ,Figure 1 is a block diagram of the device according to the present invention, 8
A digitized 8-bit video signal component from a transmission channel, for example a DVTR, with a 1 ovc error is received at the bit input terminal. Other numbers of bits can also be used to digitize this video signal. The input number at the moment shown is the middle element VB (n4-1) 11 in Figure 2. represents 1
．． 8 bits are applied to the delay line 12 (8 delay lines for each bit) and the missing correction (DOC) arithmetic circuit 14 (described below with reference to FIG. 3). The delay line 12 delays its input signal by one sampling period (the reciprocal of the sampling frequency), and its output signal is expressed by pixel vB.
(n). This output signal is applied to circuit 14 and an 8-bit delay line 16 with one sampling period.

The output signal of delay line] 6 corresponds to pixel vB(n-1),
Circuit 14 and an 8-bit delay line 18 exhibiting a delay of one horizontal line period minus two sampling periods and represented by LH-2D.
is applied to.

The output of the delay line 18 is the pixel vM(n+1), which is the output of the circuit 14.
and an 8-bit delay line 20 showing a delay of one sampling period.
is applied to The output signal of the delay line 20 is the pixel vM(n)
That is, it consists of a central reference pixel that is assumed to be invalid, for example due to a dropout, and is applied to the circuit 14 and the 8-bit delay line 22. Since the delay of the delay line 22 is one sampling period,
Its output signal is pixel vM(n-1), which is applied to circuit 14 and 8-bit delay m24.

Since the delay of the delay line 24 is one horizontal line period minus two sampling periods, its output signal is equal to the pixel VT(n+1)
This signal is applied to circuit 14 and an 8-bit delay 826. Since the delay of the delay line 26 is 1/pulling period, its output consists of the pixel vT(y+), and the circuit 1
4 and 8 bit delay lines 28. The delay of the delay line 28 is one sampling period, and its output is equal to the pixel vT(n-
! ') and is applied to the circuit 14.

The DOC calculation circuit 14 generates five output signals.

The first signal is for the current pixel vM(n).

It's called VIDEO. This pixel is delay matched with the various underlying signal averages or estimates. What is delayed matching?DOC
[Arithmetic circuit] All the various estimated values from 4 are delayed appropriately so that the output signal at that time becomes the estimated value of the pixel in question, that is, vM(n). , EO is applied to the 8-bit contact 3o of the 8-bit double-throw switch 32 from the signal . The second signal from the DOC calculation circuit 14 is the adaptive estimate VA of the current error pixel and is applied to the 8-bit contact 36 of the 8-bit 4-throw switch 38. The third signal is the 4 pixel estimated value V, which is the 8-bit contact 4 of switch 38.
Applied to 0. The fourth signal has a vertical estimate of 7v and is applied to an 8-bit contact 42 of switch 38. Finally the fifth
The signal is applied to the 8-bit contact 44 of the switch 38 as a horizontal □ estimate.

It should be understood that all outputs of this DOC calculation circuit 14 are delay/delay matching signals.

Error detector 46 provides an error flag output signal. This error flag can be detected by several means, such as low amplitude information from the recording channel, information from the recording code used, or information from a special error detection code used with the video data. Error detector 46
The output of the DOO calculation circuit 14 is connected to a delay line], 5 in order to match the delay of the DOO calculation circuit 14. This is because the delay line array with the same delay time as described above for the video signal (except that the delay line is 1 bit wide instead of 8 bits wide) supplies an error flag signal when there is an error in the video pixel. The error flag delay line arrays are 12a, 16a, 18a, 20a, etc. with the same reference numbers and a subscript a.
22a, 24a.

26a and 28a. Also, like the video pixels, subscripts B, M, and T represent error flags for the lower, middle, and L scanning lines, respectively, and (n+1), (n), (n-1'
) represent error flags for pixels in each column to the right of the reference pixel, the reference pixel, and the left of the reference pixel, respectively. Therefore, the error flag at the input of delay line 1.2a is fB (n+1
') (~, the remaining error flags also follow along that delay line column in the same order as the video signal.

A fitted estimate is generated by first determining whether there is high frequency horizontal information in the upper and lower line portions adjacent to pixel vB (n). In this determination, the pixels VT (1
1-1), v)(n+1), vB(n-1'),
In addition to requiring vB (n+1) to be valid (no error), in order to actually calculate the estimated value according to the determination of the previous horizontal information, the pixels V B (n), v, (r+ 1) I VM ( n
+1. ') i "1, (11) must also be valid.

fT(n 1'), fT(n+1'), f
B(n ])1 fr3(n+1) is the error flag for the four corner pixels required by the fitted estimated value (, and ft et al. -Iq- or one (if there is an error, it may be possible to use 4-point average, vertical average, horizontal average, etc., but adaptive estimation cannot be used. The output signal of gate 50 is [Applied.-1 error Noranog fy, (n 4 ) and f, , (n+1.'
) It is related to the pixels required for u horizontal averaging, and its output (8 digits f
・:t ;4a>'-1. ,5ε3,And Gate! S
The inverting input of 4 is applied to A,/TOGETRO0.

Similarly, f T (n) and f B (n), which relate to the pixels required for vertical averaging, are combined into an OR gate 62, the output of which is applied to the remaining inputs of gate 5ε3.6o. The output signals of are combined in game 1-5s to generate error flags associated with all four pixels required for a four-point average. When the error signal rJ′i obtained in this way is 5, that is, when the four corner pixels that require the adaptive part of the estimation procedure contain an error, the gate 50 becomes 1 or 1′[
ADAPT becomes 1 when any pixel required for 4-point averaging contains an error. FOUR1 from gate 58; gate 6 becomes 1 when any pixel required for vertical averaging contains an error.
IRT from 2, HORIZ from gate 56 which becomes 1 when any of the pixels required for horizontal averaging contains an error, and delay line 20a which becomes 1 when the pixel at that time contains an error and needs to be replaced with an estimated value. fM(n) from .

Therefore, if both ADAPT and FOUR are O, the matching procedure can be used. At this time, all eight pixels required for C matching estimation are valid. When FOUR is O, a 4-point average can be used, when VERT is 0, a vertical average can be used, and when HORIZ is C), a horizontal average can be used.

i) The output signal of 52 and 54 is the control signal of switch 38 (
The bits (shown by dotted lines) are represented by Sl and so, respectively. The next number after contact 36.40.42.44 is the signal S□, So required for switch 38 to engage that contact.
indicate the control signal states of 00.0 and 1, respectively.
．． It is 0.1.1. Wrong error flag signal fM (r
+) ij switch: Applied as a control signal to 52, when the fM (r+) error flag is O, switches to the fd contact 30 to select the actual pixel, and when the fM (n) error flag is 1 is switched to contact 34 and switch 38
Select one of the estimated values selected by .

The following table shows the error signal states and required actions.

In the above table, x indicates that the error signal state is inappropriate because fM(n) is 0 and no replacement estimated value is required.

The output signal of the switch 32 is one line (In) memory 64.
is applied to The output signal of the gate 6Q indicates the origin of the abnormal omission. This output signal RmPEAT updates the memory 640 so that the last good vertical adjacent data is repeated during the abnormal omission until good data is obtained again. layered to control the The output signal of memory d4 is applied to a digital-to-analog (DA) converter (not shown) to convert it into an analog signal that can be displayed.

FIG. 3 is a block diagram of the DOC calculation circuit 14, and for easy understanding, the input terminal 1o and delay line x2Q 16.1 shown in FIG.
The total signals VB(n+1) and vB(n-1) shown as 8.20.22.24.26.28 are the 8-bit adder 7.
01C applied O The output signal of this adder 70 will be the average of the f input signals (using a hard-wired right shift to divide by 2), thus subtracting 8 bits as an estimate of the signal vB(n). 72.

The actual vB(n) signal is this subtractor 720 subtraction input and 8
applied to bit adder 74. The output signal of the subtractor 72 is a signal representing the difference between the actual value and the estimated value of vB(n),
A voltage is applied to the absolute straight circuit (ABS) 76. The output signal of this circuit 76 is applied to an amplitude comparator 78 together with a threshold signal T. This comparator 78 always generates a signal when the output of the absolute value circuit 76 has a smaller amplitude than the threshold signal, and applies the signal to an OR gate of 80 Vc. That is, when the difference □ between the actual value and the horizontal estimated value is smaller than the threshold value, "" is generated.

The signal vM(n+1)*vM(nl') is applied to an 8-bit adder 82 which provides a horizontal average signal, signal VH, to an 8-bit contact 84 of an 8-bit switch 86. Also, the signal vT(,,n+l'l,v,('n
-1) is applied to an 8-bit adder 88, which applies the 8-bit 1 subtracter 90VC output signal. This signal VT (n) is the subtraction input of the subtracter 9o and the adder 7
4. The output signal of adder 74 is the vertical average signal Vy, which is connected to 8-bit contact 92 of switch 86 and 8-bit adder 94 . It is marked υ]. The output signal of the adder 94 is a four-point average signal ■4.

The output signal of the subtracter 90 is sent to an absolute value circuit (ABS') 96.
1 representing the difference between the estimated and actual output signal (V,in) of circuit 96 is applied to amplitude comparator 98.

A threshold signal T is also applied to the comparator 98, and if the output of the circuit 96 is less than this threshold, a signal 1'f is supplied to the gate 8o. Therefore, if the line below has a horizontal estimate that is sufficiently different from the actual value, that is, if the line contains high frequency horizontal information, the gate 80 sends the signal l to the control switch 86. Estimates fitted to this by supplying &
Provides a flat □signal as an output signal for, otherwise vV. . If desired, gate 80 could be an AND gate, providing the output as an output only when both the upper and lower lines contain high frequency horizontal information, and providing the output otherwise.

It should be understood that various modifications can be made to this invention. For example, three matching estimates may be selected based on the occurrence of error-free pixels on two adjacent scan lines or on the scan line immediately above or below. It is also possible to use any combination of these conditions, e.g.
can be easily omitted. In addition, the DOO calculation circuit 14 in FIG.
It should be appreciated that while 1c provides an estimate for one channel of the component video scheme, the scheme of Figure 1 may be replicated for the other channel 1c. 1~ provides an estimate suitable for a tapped delay line and a composite video signal such as that described in U.S. Pat. By using the DOC calculation circuit, it can also be applied to composite video signals. In addition, the technical scope of this invention can be determined using information regarding the degree of omission.
This method is intended to be an error and difference management method that selects from among various error concealment methods.

[Brief explanation of the drawing]

1 is a block diagram of the method according to the present invention, FIG. 3 is a diagram showing an error pixel surrounded by good pixels, and FIG. 3 is a block diagram of the arithmetic circuit used in FIG. 1. 〜28... Generation means, 15.46... Determination means, 122-282.3 days, 50-62... Selection means, τN% '4% ``y17 wire... Estimated value. % Application Person RCNY Became a corporation Buried Person Tetsu Shimizu and 2 other talented persons 0O vB(n-l) we(n)271- vl(n+1) vB(n+1) Procedural amendment (spontaneous) 1. Patent application for indication of incident No. 1985-856'76 No. 2, Title of Invention: Device for Concealing Error Samples of Extracted Video Signals 3, Relationship with the Corrector Case Address of Patent Applicant: 1002, New York State, United States of America
0 New York Rock Fare 7-Brother 30 Name (757) RCSNY Corporation 4, Agent 5, “Claims”, “Detailed Description of the Invention” and “Brief Description of Drawings” of the specification subject to amendment Each column. 6. Contents of amendment (1) The scope of patent claims will be corrected in the attached circular. (2) The table on page 10 of the specification is corrected as follows. (3) We will correct the detailed statement according to the following errata. Supporting Documents Claims Above 2. Claims (1) Generating means for generating a plurality of estimated values of an error sample from samples neighboring the error sample using various methods, and a method for deriving the estimated values. a determining means for determining if there is an error sample among the samples neighboring the error sample used; and a selection means for selecting an estimated value generated by the best Shiiji method that does not use error samples to generate the estimated value. and an error sample concealment device for extracted video signals. -27:

Claims (1)

[Claims] (1) Generating means for generating multiple estimates of an error sample from samples close to the error sample due to differences in methods, and a sample close to the error sample used to derive the estimated value [even in April, there are error samples] and a selection means for selecting an estimated value generated by the best estimation method that does not use error samples to generate the estimated value. deep,
Covering device.