JPS59211335A - Level shift circuit - Google Patents

Abstract

PURPOSE:To attain stable equalizing operation and decoding by detecting zero level of a signal digital waveform multiplexed with an analog signal and subtracting this zero level from an input signal to attain level shift. CONSTITUTION:A signal is inputted to a timing circuit 14 via an AGC circuit 12 and an A/D converter 13 and the circuit 14 detects a multiplex position of a character signal and gives a timing signal 15 whose level is inverted during the period representing the multiplex position to a level shift circuit 16. A character signal 21 inputted from the converter 13 is supplied to a waveform memory 23 and a subtractor 22 in the circuit 16 and an operation processing circuit 24 detects a zero level of the character signal by reading the signal 21 from the memory 23 in the timing given by the signal 15. This zero level is stored in a memory 25 as a shift level, and this shift level 26 is subtracted from the signal 21 by the subtractor 22. Further, a character signal 27 whose level is shifted is subjected to distortion correction by a waveform equalizer 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a level shift circuit necessary for waveform equalization and decoding of digital signals such as television teletext signals.

[Technical background of the invention and its problems]

When a digital signal (text signal) is multiplexed into an analog signal (television signal), such as a television teletext signal, when the digital signal waveform is extracted,
The DC level is often uncertain. Therefore, when processing the extracted digital signal waveform, a level shift circuit is required to keep the DC level constant.

FIG. 1 is a block diagram of a level shift circuit used for this purpose. A television signal is input to an input terminal 1, and its amplitude is first made constant by an AGC circuit 2. Next, the pedestal level is clamped to a constant level by the pedestal clamp circuit 3 and then provided to the signal processing circuit 4.

However, in such a configuration, from the viewpoint of control accuracy of the AGC circuit 2 and operational stability against waveform distortion of the input of the pedestal clamp circuit 30, if the signal processing circuit 4 is a waveform equalizer, it is not possible to use it as a level shift circuit. performance is not sufficient. For example, as a waveform equalizer, one is known that inputs a signal to a transpersal filter and corrects the tap gain of the transpersal filter according to the result of a tu relation calculation between the output error signal waveform and the input signal waveform. However, in such a waveform equalizer, if a DC component exists in the input signal waveform, a large error will occur in the result of the calculation, making it impossible to obtain a good equalization operation. Since the level shift circuit as shown in FIG. 1 cannot sufficiently stabilize the DC level of the character signal portion, it cannot remove the DC component harmful to the operation of the waveform equalizer.

Further, even if the signal processing f#A circuit 4 is a character signal decoding circuit, there is a problem that if the DC component of the input signal is not constant, the level determination becomes uncertain and the error rate increases.

[Purpose of the invention]

An object of the present invention is to provide a level shift circuit that is useful when equalizing or decoding a digital signal waveform multiplexed with an analog signal.

[Summary of the invention]

The present invention detects the multiplex position of a digital signal multiplexed with an analog signal, extracts a digital signal waveform based on the position and holds it in a memory, constantly detects the zero level of this held digital signal waveform, and The level shift is performed by subtracting the zero level obtained from the input signal. Here, the level is the level at which the digital signal waveform should be zero, that is, the level at which the digital signal waveform should be zero.
In terms of value digital signal waveforms, it is the intermediate level between high level and low level.

Detection of this zero level is achieved, for example, by calculating the average value of the maximum value and minimum value of the digital signal waveform held in the memory.

〔Effect of the invention〕

According to the present invention, since the zero level of the digital signal waveform multiplexed with the analog signal can be kept constant,
Subsequent processing such as waveform equalization and decoding can be performed satisfactorily.

In other words, it is desirable for a waveform equalizer to have no DC component in the input signal, but if the zero level of the digital signal waveform is kept constant as in the present invention, that DC component will also disappear, so stable equalization operation can be achieved. can get.

Furthermore, when decoding a digital signal waveform, if the zero level is kept constant, stable decoding with a low error rate is possible by simply determining whether the signal is positive or negative.

[Embodiments of the invention]

An embodiment of the present invention will be described below by taking a level shift circuit for a television teletext signal as an example. FIG. 2 is a block diagram of one embodiment.

The television signal input to the input terminal 11 is made to have a substantially constant amplitude by the AGC circuit 12, and then sent to the A/D converter 13.
The signal is introduced into the signal generator, is converted into a several-bit digital signal, and is provided to the timing circuit 14. The timing circuit 14 detects the multiplex position of character signals and supplies the level shift circuit 16 with a timing signal 15 whose level is inverted for a period indicating the multiplex position.

An example of the configuration of the level shift circuit 16 is shown in FIG. A/
The digital character signal 2 input from the D converter 13 is supplied to a subtracter 22 and a waveform memory 23. The waveform memory 23 stores part or all of the character signal waveform according to the timing signal 15. The arithmetic processing circuit 24 reads this input character signal waveform from the memory 23 at the timing given by the timing signal 15, and
Detects the zero level of the character signal. Calculations for this detection can be easily performed using a microprocessor.

FIG. 4 is an example of a flowchart for this zero level detection. The level of the input data from the memory 23 is determined in step 31 based on a plurality of reference levels determined at regular intervals, and a level distribution table is created. This level distribution table is created until it is determined in step 32 that the number of input data has reached a certain value. When the number of data reaches a certain value, a distribution table with contents as shown in FIG. 5 is obtained. In FIG. 5, the horizontal axis represents the signal level, and the vertical axis represents the frequency of appearance of each level. Since the character signal is a binary digital signal, its level distribution has two most frequent levels centered around the high level PH and the low level PL. Therefore, in step 33, these two
If the two most frequent levels (maximum value and minimum value) are detected and their average value is determined in the next step 34, this becomes the zero level.

The zero level detected in this way is stored as a shift level in the level memory 25km of FIG. 3. This shift level 26 is then subtracted from the input character signal 21 by the subtracter 22.

The level-shifted character signal 27 is sent, for example, to a waveform etc. 17, as shown in Figure @2, and waveform distortion is corrected.

The waveform equalizer 17 is described in detail in, for example, Japanese Unexamined Patent Application Publication No. 166674/1983, ``Television Ghost Eliminator'' by the present applicant.

FIG. 6 shows another embodiment of the invention. The character signal code 21 that has passed through the AGC circuit 12 and the A/D converter 13 has a negative shift level added to it by an adder 41, and then is supplied to a waveform equalizer 17 and a waveform memory 43. The level-shifted character signal waveform written in the memory 43 is input to maximum value and minimum value detection circuits 44 and 45, and the maximum and minimum values detected thereby are input to an adder 46.
The signals are added together, and then halved by an arithmetic circuit 47 to obtain a zero level. This zero level is further multiplied by 11 and supplied to an adder 41 as a negative shift level 49 via a level memory 48. The maximum value, minimum value, and shift level are updated using the timing signal 15 generated by the timing circuit 14. Since the maximum and minimum values change every time the shift level is updated, these detections must also be updated.

The level shift circuit of this embodiment has the feature that it can be realized with only a small number of logic elements without using complicated hardware such as a microprocessor as shown in FIG. 3 in detecting the maximum value and minimum value. Its detection is addition 5
This shows that it can also be done using the output of 41.

By the way, the absolute values of the maximum and minimum values detected by the maximum value and minimum value detection circuits 44 and 45 in FIG. Alternatively, it is desirable to use a so-called leaky detection circuit that constantly decreases its absolute value little by little and compares it with a new signal value of the digital signal waveform.

FIG. 7 shows an example of the configuration of a maximum value detection circuit with leakage. The input character signal 5 is connected to the A input of the comparator 52 and the 2-man power 1
It is added to the output selector 54's A manual power. When the latch 53 that holds the maximum value receives an input that is larger than the previously held maximum value (A>B), it holds that input as the new maximum value. When the input is not greater than the previous maximum value, the adder 55 adds the leakage amount -Δ to the output of the latch 53 to obtain a value smaller by Δ, which is held in the latch 53 again via the selector 54.

In this way, maximum value detection is performed while waiting for leakage, and the maximum value detection output 5G is obtained at the output of the latch 53.

Note that the minimum value detection circuit with leakage is input 51 in FIG.
, can be realized by adding a sign inversion circuit to the output 56.

If you have a leak like this, the maximum for a certain period of time,
Compared to the method of initializing the minimum value detection circuit, this method has the advantage that the timing system can be simplified because it can be left in continuous operation.

The present invention is not limited to the above embodiment, and a similar level shift circuit may be installed at the output of a transversal filter in another waveform or the like.

In addition, when the input signal fluctuates greatly, the level shift may cause the arithmetic circuit system to overflow, but if an overflow is detected, measures such as resetting the level shift value or decreasing the absolute value may be taken. If it is added, the effects of the present invention will be more effectively exhibited.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a conventional level adjustment circuit, FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a block diagram of a level shift circuit according to the same embodiment, and FIG.
The figure is a flowchart to explain its operation, Figure 5 is a diagram showing a signal level distribution table, Figure 6 is a block diagram showing another embodiment of the present invention, and Figure 7 is maximum value detection with leakage. FIG. 2 is a block diagram of the circuit. 14...-timing circuit, 16.16'...level shift circuit, 23.43...waveform memory, 24...arithmetic processing circuit, 25.48...level memory, 22...
Subtractor, 41... Adder, 44... Maximum value detection circuit, 45... Minimum value detection circuit, 46... Adder, 47
...Arithmetic circuit. Applicant's representative Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Cone number ν bar

Claims (3)

[Claims] (1) Means for detecting the multiplexing position of a digital signal from an input signal in which a digital signal is multiplexed at a predetermined position of an analog signal, and controlling by this means to hold the waveform of the digital signal of the input signal. means and
A level shift circuit comprising: means for detecting the zero level of the held digital signal waveform; and means for subtracting the detected zero level from the input signal. (2) The zero level detection means detects the zero level by detecting the maximum value and minimum value of the digital signal waveform and calculating the average value thereof. Level shift circuit according to item 1. (3) The means for detecting the maximum and minimum values includes means for constantly decreasing the absolute values of the detected maximum and minimum values little by little, and comparing these maximum and minimum values with a new digital signal level. 3. The level shift circuit according to claim 2, further comprising means for updating the maximum value and the minimum value.