JPS59201287A - Cache memory control system - Google Patents

Abstract

PURPOSE:To execute a nullification of a cache memory at a high speed without increasing a hardware by providing plural V-bit memories, switching them and nulifying the cache memory. CONSTITUTION:A nullification of a cache memory in case a task is switched is executed by clearing a V-bit memory. As for plural V-bit memories 301A, 301B such as two pieces, etc., when one of them is executing a task, the other becomes a standby, the standby is cleared through an address counter 300, and the counter 300 outputs a high level overflow signal, and opens an AND gate 310. In this state, when a D type FF309 responds to a nullifying signal from a CPU following a task change, a switching signal outputted from a T type FF308 is varied, and one of the memories 301A, 301B, and the other are switched to a standby and a task execution, respectively. According to this constitution, a nullification of the cache memory is executed immediately at a high speed by a cleared V-bit memory without increasing a hardware, and without clearing the V-bit memory in accordance with a nullification request.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a cache memory control method, and particularly to a cache memory control method suitable for quickly invalidating all data stored in a cache memory. Regarding the method.

[Background of the invention]

In the information processing apparatus having the configuration shown in FIG. 1, the central processing unit (JOBP) 40 accesses the job memories 41 and 42 using virtual addresses (sometimes referred to as logical addresses), so task switching is possible. Sometimes it is necessary to invalidate the entire cache so that the data of the fortune-telling virtual space remaining in the cache memory is not misused. In the prior art, the operation of JOBP 40 was also stopped and invalidated.

Also, in order to increase the speed, it is possible to disable it by configuring and resetting a large number of invalid Viratra, but in either case, the overhead of switching each task increases, making it difficult to increase the speed. There are disadvantages such as an increase in f, height, or an increase in the amount of node hardware.

[Object of the Invention] An object of the present invention is to provide a cache memory control method that enables high-speed invalidation of all cache memories, which is necessary when switching tasks, and minimizes the increase in hardware amount. be.

[Invention 1. ! J:e:] Invalidation of the Gyaso/U memory is performed by clearing the ■ bit indicating whether the data of the accessed block is valid or invalid.

Therefore, performing multiple convolutions (cache capacity/block length) times when switching tasks increases the overhead when switching tasks. .0000
Focusing on the points that occur at intervals of 7 or more non-cycles, at least 2 V-bit memories indicating whether they are valid or invalid are set.
One V-bit memory is used to clear the remaining V-bit memory for standby use during task execution, and this V-bit memory is used to invalidate the cache memory required when switching tasks.
By changing the bit memory bj, high-speed processing is possible.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

In FIG. 1, 10 is a main memory device, 121-t main memory control unit (MCU) having a built-in address translation device, 22
is a secondary storage device, 2 (1: secondary storage control processor (F
CP), 30 is an input/output control processor (ioP), 40
is a central processing unit (J'OBP), 41 and 42 are cache memories for instructions and data, respectively, 43 is an instruction decoding unit, 44 is an instruction execution unit, 11 and 21 are each 10
and 12. Pass line connecting 22 and 20, 45, 46.
47 is an internal bus of JOBP 40, and 50 is a common bus connecting each processor.

The present invention is applied to the instruction cache 41 and data cache 42 in the first section.

Next, with reference to FIG. 2, the case of the command y/y will be explained.

FIG. 2 is a block diagram of a cache memory that employs an invalidation method based on directory duplication.

Reference numeral 210 denotes a data section of the main memory in which part of the data of the main memory 10 is stored. 20 ( ) is a directory in which the address of the data stored in the cache data section 210 is stored. 206 is an invalidation directory for invalidation processing and holds the same information as 210. There is.

Reference numeral 203 denotes a V-bit memory section which performs fd processing to determine whether each block of the data section is valid or invalid (75). Both 201 and 207 are comparators, which compare the contents of the directory (200, 206) with the contents of the atto Vs 91 or 99.
Compare with. Reference numeral 208 denotes an invalidity judgment circuit, which outputs the output of the comparator 207 and the information of the control section 53 of the same Jl'', and the output of the comparator 207.
Since address 1 is memory read d-IL, ■ also, no≧
, determines whether it is for memory writing (this process A-yazoyu needs to be invalidated). 209 is the instruction cache controller (2W) 'fi1' controls the entire instruction cache. The overall operation of such a cache memory is well known, but only the case of quickly invalidating all the data related to the present invention will be described here.

In the case of multiple virtual memories, in the configuration shown in FIG. 1, all caches must be temporarily activated each time a task is switched. Therefore, when the task switching port 1V is set, the all invalidation request signal 95 is set to V from the internal bus control unit 45.
Sent to the bit memory section. In response to this signal, the entire cache is invalidated in the V-bit memory section, and when the process is completed, a signal 94 indicating invalidation completion is returned. The central processing unit enters a waiting state after receiving 95 and until receiving 94.

Next, the V-bit memo IJff1 will be explained with reference to FIG.

301 and 301B are V bit memories that store V bits indicating whether cache data is valid or invalid. 3
00 is the address 103 when clearing the V pit memory.
This is an address counter that generates an address counter that is reset at 107 and counted up by the clock pulse of the information processing device supplied from 103. Output a signal. 302 is a No. gate, ORs the invalidating signal 97 and the validating signal 98, and outputs V.
Generates a combination of bits of memory.

308σ'r flip-flop, inverts outputs 104 and 105 every time the address counter is reset, and sends them to selector 304, 304B and 305A.

Invert the selection of 305B, 306A, and 306B. 3
09 is D Nori Rag Frog request for complete invalidation i=No. 9
Latch 5. 310 is an AND gate, 108
Controls whether or not the bit memory is switched based on the output of and 309.

Next, the operation shown in FIG. 3 will be explained. In the present invention, only one of the two V-bit memories operates as a normal V-bit memory, while the other is cleared in response to the address from the address counter and is used for standby. That is, 104
is HIG) (, 1o5 is LOW, then 301A is 1
03 f-7)"l/,'(,301.BU102
and the output 96 of the V bit memory section is 301
The output 109B of B is selected. Also at this time, 305A
selects all 111A, and 304A selects 110A, so unless 105 changes, O will be written to 301A according to 103. Also, at this time, 305B selects 111Bf, and 304B selects 110B, so 301B selects 9 for the part that can be addressed by 102.
Reading is performed according to 7 or 98, or writing of 0 and 1 is performed.

Next, the operation of the control section 350 of the V-bit memory section will be explained. Consider the case of 400 in FIG. υIjchi301B
has already been cleared, and the open low signal 108 has become HIGH. At this time, when the invalidation request signal 95 comes from the CPU, the signal 95 is latched by the 309, and then the 3
10 is ANDed with 108, the invalidation end signal 94 is immediately activated, the output of 308 is inverted and the V-bit memory is switched, and the address counter is reset to start the switching of the V-bit memory. The CPU side knows through 94 that all cache invalidation has been completed, and executes a new task 2? You can start. If the clearing of the V bit memory is completed during the execution of task 2, the next task switching will be in the same state as 400, and the knife can be started for 4 hours. However, if task switching occurs while task 3 is being executed and the V via and tomemory have not been cleared, the situation 401 will occur. In the case of 401, 108 is not HIGH even if a complete invalidation request is issued.
The output of 10 is H! It does not become GH and the CPU waits for the invalidation to complete. Then, at a time 402 when the invalidation is completed and 108 becomes HIGH, the state and story are the same as in 400, and the changeover of pinotome seven is performed and task 4 is started. As mentioned above, the bit memory has been cleared (
Disabling can be done instantly.

〔Effect of the invention〕

Pillar 1-i: During the execution of a certain task, one V-bit memory is cleared in parallel in preparation for switching to the next task. Therefore, if the interval between task switching is greater than or equal to the number of machine cycles of pits in the V-bit memory, this can be done by simply switching the invalidation IDs of all cache memories and the V-bit memory using the selector. It's much faster than clearing it. Also, compared to an example in which the V-bit memory is configured with many free-lag flops and cleared all at once by the reset pin, the V-bit memory can be used with regular memory, reducing the need for hardware. It can be less.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the overall configuration of an information processing device to which the present invention is applied, FIG. 2 is a diagram showing a general configuration example of an instruction-t-gino7u, and FIG. FIG. 4 is a diagram illustrating a timing chart of the control section 350 of FIG. 301A...V bit memory, 301B...V bit memory, 300...address counter, 308...
・T flip-flop, 309...D flip-flop, 303, 304A, 304B, 305A, 305B
. 306A, 306B---sector. Agent: Patent Attorney Akio Takahashi No. 1

Claims (1)

[Claims] 1. Whether the memory that stores part of the data stored in the main storage device and the data stored in the memory are valid;
In a cache memory consisting of a V-bit memory that stores bit information indicating invalidity, a plurality of V-bit memories are fixedly provided, one V-bit memory is fully used, and the remaining one is used.
A cache memory control method characterized in that the V-pit memory is placed on standby as a reserved memory, and when the cache memory is invalidated, the V-pit memory in use and the V-pit memory in standby are switched. 2. It has a processing device that performs all data loss information processing from the main storage device and cache memory, and the V-bit memory currently in use and the V-bit memory in standby are switched according to a command from the processing device. A cache memory control method according to claim 1. 3. When there is a switching command from the processing device, if there is no cleared V-bit memory, the processing device will wait for information processing to occur until the standby V-bit memory becomes cleared. ) vc 1. 7. A control system for controlling the position of the camera as set forth in claim 2.