JPS59183327A - System for stabilizing encoder detection signal - Google Patents

Abstract

PURPOSE:To stabilize the detection signal by providing a bias correction means for an encoder output signal depending on the difference between absolute values of the maximum and minimum values of the encoder output signal and a bias correction means for an encoder output signal depending on the sum of the maximum and minimum values. CONSTITUTION:An encoder comprising a linear scale with a lattice-like mark and a sensor block detects the position of a carriage with an light emitting element 13 and a light receiving element 14 arranged on the block facing to each other. Output signal through a preamplifier 21 and an amplifier 22 is outputted via a bias correction circuit 33 and an AGC circuit 39. Odd and even cycles are discriminated depending on outputs of a comparator 44 and a digital differentiation circuit 48 to detect maximum and minimum values for peak hold circuits 51-53 respectively. A subtraction circuit 59 determines the difference between absolute values of the maximum and minimum values and transmits a correction signal of the circuit 33 and an addition circuit 60 determines the sum of absolute values of the maximum and minimum values and transmits a signal to the circuit 39. This enables a stable detection regardless of fouling and error in the mounting of the encoder.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The FUJIJ-1 relates to a Nora type encoder detection signal stabilization system that stabilizes the output of an encoder used in optical tisf devices, printers, and the like.

(σC rice support e::j) There is a sensor that detects the sensor, and the method to correct the output fluctuation is to install a dummy sensor.σ) Position detection sensor θ) Corrects the output fluctuation using the sensor output. There is a method.

However, in this method, the first problem is that the characteristics of both sensors must be the same, and the characteristics of both sensors must be the same. The second problem is that the level of contamination on the scale and the mounting position must be aligned. There is a way to suppress the variation by using the ■-force/force θ) method, which requires the two to be placed close to each other due to the size of the semiconductor cell. Due to contamination caused by bumps, etc., the output signal becomes larger during fluctuations, which means that the S/N ratio is poor.

At most 5 problems will occur.

(Purpose) My brother Akira's encoder is contaminated by 1 scratch etc., -1
It is an object of the present invention to provide an encoder detection armature stabilizing force formula that can reduce fluctuations in the four-pronged path.

(A17+Construction) The present invention will be described below with reference to the drawings, with reference to the embodiments.

An example of an incremental linear encoder is not shown in m 11'Z, l.

This encoder 10 can be used to mark grid-like marks.
The first sensor block 12 is composed of the scale 11 and the sensor block 12, and the sensor block 12 has the light emitting element 16 and the light receiving element 1/i.
Facing each other through the slit of Cenoza Mask 15
It was ordained. This sensor block 12 is fixed to the ridge 16, and the carriage 16 is movably supported on a linear rod 17 by a linear bearing, and is driven by, for example, a linear motor. A linear movement is performed along the lot 17. The linear scale 11 is arranged parallel to the load 17, and the sensor block 12&'j
,'J Near School 11
A linear scale 11 is interposed between the sensor mask 15 and the sensor mask 15 . This sensor block 12 moves along with the linear speed movement of the carriage 16, and detects the position of the carriage 16 by detecting marks on the linear scale 11 with the light emitting cable 13, sensor mask 15, and light receiving element 1/l. conduct.

This encoder 10 is often used with the linear scale 11 protruding, and if there is dust on the linear scale 11. The output of the light receiving element 14 fluctuates.For example, the output of the light receiving element 14 may be waveform-shaped into a rectangular wave at zero level as shown in FIG. changes (
In FIG. 2, this is shown as a zero-level fluctuation), resulting in a position error of δ. Also Carino/16
Even when the output signal of the light-receiving element 14 is differentiated and used as a speed signal for position control, if the output amplitude of the light-receiving element 14 fluctuates, the speed signal will fluctuate too much (and the position control may not be performed normally (1st yo). There are some northern states.

FIG. 6 shows an embodiment of the present invention, and FIG. 4 (:J) is a time chart thereof. The output signal of 1 is amplified by a preamplifier 21 consisting of an operational amplifier 19 and a resistor 20, and is further amplified by the next stage amplifier 27 consisting of an operational amplifier 22 and resistors 26 to 26.The output signal of this amplifier 27 is A NA Under certain environmental conditions, the amplitude and bias of LQC are adjusted to normal values, and the maximum value and minimum value B are equal.This output signal ANALOG is output from the operational amplifier 28 and the resistor 29.
A bias correction circuit 33 consisting of ~62 and an operational amplifier 6
4. Photoelectric element (e.g. CDS optofisolator) 65
and an AGC (automatic gain adjustment) control circuit 69 consisting of resistors 36 to 68, and output f(, . The AGC circuit 69 constitutes an amplitude correction circuit.

When the carriage 16 is not moving, the start signal STA RT arrives (no), so the flip-flops 40 and 41 are reset Jl, switch SWE',
At the same time as SWF is turned off, switch SWD is turned on by the output of inverter 42. Therefore, the voltage of the DC power supply E is input to the AGC circuit 69 as an AGC signal, and the voltage of the DC power supply 43 is the sum of the absolute values of normal A and B IAI +
IBI is set. At this time, the output of the AGC circuit 69 (No. E SIG) becomes the same as the output signal ANALOC of the amplifier 27.

Next, when the carriage 16 moves and a start signal arrives, it operates according to time chart 1, not shown in FIG. In other words, the output signal A'NALOG of the amplifier 27 is set to a zero level by the comparator 44, and the ratio is 11 to the zero level.
SA K waveform shaping, D flip frog 45°46
The signal is differentiated by a clock pulse GLK from a Tehalus generating circuit 49 into a digital differentiating circuit 48 consisting of an AND circuit 47 and an AND circuit 47 . The flip-flop 41 is inverted from the output pulse DEF K of the digital differentiator 48 and sent to the J width divider 2.
It is determined whether the output signal ANALOG of 7 is a difference between an odd number cycle and an even number cycle, and a non-inverted output ODD is generated in the odd number cycle and an inverted output EVE is generated in the even number cycle.
N is generated. In odd-numbered cycles, the switch SWA is turned on by the non-inverting output DD of the flip-flop 41, and the peak hold circuits 50 and 51 detect the maximum value A and the maximum lh value B of the output signal ANALOG of the amplifier 27, respectively. In even cycles, the flip-flop 410 inverted output EVEN K turns on Suinochi SWB, and the peak hold circuits 52 and 53 output the amplifier 27 output signal ANALO.
The maximum value A and the minimum value B of C are respectively detected. - output D of the digital differentiation circuit 48 is output by the clock pulse GLK from the pulse generation circuit WJ49.
EF is latched, and the seventh gate 55 ANDs the non-inverted outputs of the flip-flops 41 and 54 to generate a gate pulse α.

This gate pulse α is differentiated by a differentiating circuit 56 and becomes a reset signal DEFa, which is output by a peak hold circuit 50.
, 51 after the end of the even cycle (at the beginning of the odd cycle). Furthermore, the seventh AND gate 57 generates a gate pulse β by ANDing the inverted output of the flip-frog 41 and the non-inverted output of the flip-frog 54.
The gate pulse β is divided by the differentiating circuit 58 and becomes the reset signal DEFβ by the peak hold circuit 52.
3 after the end of the odd cycle (at the beginning of the even cycle)
10 nods. Switches SWI and SWJ are activated in several cycles by the non-inverting output ODD of the flip-flop 41 (maximum 11C1 of peak hold circuit 50, 51, maximum
”・During value detection operation) turns on and switches SWG, SV/
H is output in even cycles (peak hold circuits 52, 53
Maximum value of ', maximum l' - 9 turns on during value detection operation -6 so,
By subtracting the output of the peak hold circuit 53 from the output of the peak yield circuit 52 in odd cycles, the subtraction circuit 59 obtains the maximum value A and the maximum /J% value B of the output signal ANALOG of the amplifier 27 in each even cycle. The absolute value of the maximum value A and the minimum value B of the output signal ANALOG of the amplifier 27 in each odd cycle is calculated by calculating the difference in absolute values and subtracting the output of the peak hold circuit 51 from the output of the peak hold circuit 50 in the even cycles. Find the difference between.

The output signal of the subtraction circuit 59 is sent as a bias correction signal to the bias correction circuit 66 via the switch SWF, and is added to the output signal of the amplifier 27 to correct its amplitude. Further, the adder circuit 60 freezes the absolute values of the maximum il&A and the minimum value B in each even cycle of the output signal ANALOG of the amplifier 27 by adding the outputs of the peak hold circuits 52 and 53 in fl-number cycles. In even cycles, the sum of the absolute values of the maximum value A and the maximum value B of the output signal ANALOG of the amplifier 27 in each odd cycle is determined by adding the outputs of the peak hold circuits 50 and 51. The output signal of the adder circuit 60 is sent as an AGO signal to the AGO circuit 69 via the switch SWE, and the amplitude of the output signal of the bias correction circuit 63 is corrected. Also, the flip-flop 40 is a flip-flop 41
After the first odd cycle is completed by the first non-inverted output ○DD of
The enable signal ENABLE is generated by setting λ1 at the beginning of the first even-numbered cycle, and this signal ABLE turns on the switches SWE and SWF.
turns off. Therefore, bias correction and amplitude correction for the output signal of the amplifier 27 are started after the peak hold cycle "#'J50.51" is operated in the first cycle after the carriage 16 starts moving (the sensor block 12 starts moving). In other words, it must not be done before the supplementary city information is issued.

One of the features of this embodiment is that the AGC circuit performs amplitude correction after bias correction.If this was reversed, a signal with a bias deviation was output from the amplifier 27. In the AGC circuit, the correction is offset by the amount of bias (-, the bias correction is shifted by that much, and the bias of the final output signal SIG ends up being off.Other characteristics of this embodiment The first is to perform bias correction and amplitude correction without using Deba S-G.If Deba SZC is fed back and bias correction and amplitude correction are performed in odd-numbered cycles and even-numbered cycles as described above,
For example, since the signal corrected in an even cycle becomes the target of detection of the correction amount to be corrected in the next odd cycle, even if the original signal ANALOG changes, it is determined that it has not changed due to the However, in the end, the outputs S and TG cannot be corrected.

Further, although the above embodiment is an embodiment for an encoder having an optical type sensor, the present invention can be similarly applied to an encoder having a sensor using other types, for example, a permeance change. . Furthermore, the present invention can be similarly applied to rotary encoders other than linear encoders.

(Effects) As described above, in the encoder detection signal stabilization method according to the present invention, the difference and phase between the absolute values of the maximum value and the minimum value of the encoder output signal are determined, and the bias and bias correction of the encoder output signal is performed. Since amplitude correction is performed, the encoder output fluctuation can be minimized even if the encoder is contaminated by dust, mechanical variations such as installation errors, changes due to temperature, or changes over time, and a dummy sensor is not required. Become.

[Brief explanation of the drawing]

Figures 1 (al to d) are a perspective view showing an example of an encoder, and an M-plane view and a front view showing valleys thereof; Figure 2 is a time chart for explaining output fluctuations of the encoder;
The figure is a block diagram showing one embodiment of the present invention, and FIG. 4 is a time chart of the same embodiment. 36... Bias correction circuit, 69... AGC circuit,
50 to 56...Peak hold circuit, 59...Subtraction circuit, 60...1 addition circuit.

Claims (1)

[Claims] A maximum value detection means for detecting the maximum value and minimum value of the output signal of the encoder and the absolute value difference between the maximum value and the minimum value detected by the maximum value and minimum value detection means are determined. Bias correction means for correcting the bias of the output signal of the encoder based on the difference, and N'll of the maximum value and minimum value detected by the maximum value and minimum value detection means, and the bias of the output signal of the encoder is determined by this phase. 4 types of encoder detection signal stability Kitakata equipped with bias correction means for correction.