JPS59187217U - mixed amplifier circuit - Google Patents
mixed amplifier circuitInfo
- Publication number
- JPS59187217U JPS59187217U JP8000083U JP8000083U JPS59187217U JP S59187217 U JPS59187217 U JP S59187217U JP 8000083 U JP8000083 U JP 8000083U JP 8000083 U JP8000083 U JP 8000083U JP S59187217 U JPS59187217 U JP S59187217U
- Authority
- JP
- Japan
- Prior art keywords
- operational amplifier
- terminal
- inverting input
- output terminal
- amplifier circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のミキシング回路の構成を示す回路図、第
２図はこの考案の一実施例の構成を示す回路図である。
４−１〜４−ｎ・・・・・・抵抗（入力抵抗）、５・・
・・・・第１の演算増幅器（演算増幅器）、６・・・・
・・第３の □抵抗（抵抗）、７・・・・・・第１
の抵抗（抵抗）、８・・・・・・第２の抵抗（抵抗）、
９・・・・・・第２の演算増幅器（演算増幅器）、Ｖｉ
、〜Ｖｉｎ・・・・・・入力電圧、■０１・・・・・・
混合出力電圧（出力端電圧）。FIG. 1 is a circuit diagram showing the configuration of a conventional mixing circuit, and FIG. 2 is a circuit diagram showing the configuration of an embodiment of this invention. 4-1 to 4-n...Resistance (input resistance), 5...
...First operational amplifier (operational amplifier), 6...
...Third □Resistance (resistance), 7...1st
resistance (resistance), 8... second resistance (resistance),
9...Second operational amplifier (operational amplifier), Vi
, ~Vin... Input voltage, ■01...
Mixed output voltage (output end voltage).
Claims (1)
抗値の等しい複数の入力抵抗と、前記第１の演算増幅器
の出力端と第２の演算増幅器の反転入力端との間に介挿
される第１の抵抗と、前記第２の演算増幅器の反転入力
端と出力端との間に介挿される第２の抵抗と、前記第１
の演算増幅器の非反転入力端と前記第２の演算増幅器の
出力端との間に介挿される第３の抵抗とを具備し、複数
の入力電圧を各々前記各入力抵抗の他端に供給するとと
もに、前記第１の演算増幅器の出力端から混合出力電圧
を取り出すことを特徴とする混合増幅回路。A plurality of input resistors having equal resistance values each having one end connected to the non-inverting input terminal of the first operational amplifier are interposed between the output terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier. a first resistor inserted between the inverting input terminal and the output terminal of the second operational amplifier;
a third resistor inserted between the non-inverting input terminal of the operational amplifier and the output terminal of the second operational amplifier, each supplying a plurality of input voltages to the other terminal of each of the input resistors. A mixing amplification circuit characterized in that a mixed output voltage is taken out from an output terminal of the first operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8000083U JPS59187217U (en) | 1983-05-27 | 1983-05-27 | mixed amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8000083U JPS59187217U (en) | 1983-05-27 | 1983-05-27 | mixed amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59187217U true JPS59187217U (en) | 1984-12-12 |
Family
ID=30209996
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8000083U Pending JPS59187217U (en) | 1983-05-27 | 1983-05-27 | mixed amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59187217U (en) |
-
1983
- 1983-05-27 JP JP8000083U patent/JPS59187217U/en active Pending
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