JPS59172739A - Semiconductor integrated circuit device and manufacture thereof - Google Patents
Semiconductor integrated circuit device and manufacture thereofInfo
- Publication number
- JPS59172739A JPS59172739A JP4752183A JP4752183A JPS59172739A JP S59172739 A JPS59172739 A JP S59172739A JP 4752183 A JP4752183 A JP 4752183A JP 4752183 A JP4752183 A JP 4752183A JP S59172739 A JPS59172739 A JP S59172739A
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- silicon
- circuit device
- region
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/7627—Vertical isolation by full isolation by porous oxide silicon, i.e. FIPOS techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electrodes Of Semiconductors (AREA)
- Element Separation (AREA)
- Bipolar Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、半導体集積回路装置とその製造方法に係るも
ので、誘電体層で素子が分離されるとともに素子間をシ
ールドする半導体集積回路装置とその製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device and a method for manufacturing the same, and more particularly to a semiconductor integrated circuit device in which elements are separated by a dielectric layer and shielded between the elements, and a method for manufacturing the same. be.
半導体集積回路装置における素子間の分離の方法は種々
ある。一般的な方法はＰＮ接合分離であるが、より完全
な分離を目的として誘電体分離が注目されている。これ
は、素子をシリコン酸化物で囲まれた単結晶シリコンの
島の中に形成し、素子間をシリコン酸化物の誘電体層で
分離するものである。この誘電体分離にも幾つかのタイ
プがあシ、最も一般的なものは異方性エツチングによっ
てＶ字形の溝を形成し、酸化膜、多結晶シリコン層を形
成し、研磨によって単結晶ンリコ／の島を形成するもの
である。しかし、このような誘電体分離基板を得るだめ
の工程が複雑となυ、歩留が低いことから、多孔質シリ
コンを利用して絶縁領域を形成することが考えられてい
る。There are various methods for separating elements in a semiconductor integrated circuit device. A common method is PN junction isolation, but dielectric isolation is attracting attention for the purpose of more complete isolation. In this method, devices are formed in single-crystal silicon islands surrounded by silicon oxide, and the devices are separated by a dielectric layer of silicon oxide. There are several types of dielectric separation, but the most common one is to form a V-shaped groove by anisotropic etching, form an oxide film and a polycrystalline silicon layer, and then polish it to form a single-crystalline silicon layer. It forms an island. However, since the process for obtaining such a dielectric isolation substrate is complicated and the yield is low, it has been considered to use porous silicon to form the insulating regions.
上記の多孔質シリコンを利用する方法においては、単結
晶シリコンを陽極化成処理して多孔質化し、これを酸化
してシリコン酸化物とすることによって誘電体層を形成
する。In the method using porous silicon described above, single crystal silicon is anodized to make it porous, and then oxidized to form silicon oxide to form a dielectric layer.
本発明は、この多孔質シリコンを陽極化成し、酸化する
ことによって誘電体の分離領域を形成する半導体集積回
路装置とその製造方法に関するものである。The present invention relates to a semiconductor integrated circuit device in which a dielectric isolation region is formed by anodizing and oxidizing this porous silicon, and a method for manufacturing the same.
半導体集積回路装置においては、素子間を分離するだけ
でなく、素子間を完全にシールドすることが望ましい。In a semiconductor integrated circuit device, it is desirable not only to isolate the elements, but also to completely shield the elements.
特に、高周波の信号を扱う半導体集積回路装置などにお
いては、特性の劣化を防止するためにシールドのための
手段が必要となることが多い。In particular, in semiconductor integrated circuit devices that handle high-frequency signals, shielding means are often required to prevent deterioration of characteristics.
本発明は、このシールド効果を有する半導体集積回路装
置を得るととを目的とする。An object of the present invention is to obtain a semiconductor integrated circuit device having this shielding effect.
まだ、分離領域の形成と同時にシールドのための領域を
形成できる半導体集積回路装置の製造方法を提供するこ
とを目的とする。Another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device that can form a shielding region at the same time as forming an isolation region.
本発明による半導体集積回路装置は、誘電体層の間に高
濃度に不純物がドープされた領域を形成してシールド効
果を持たせるものである。まだ、多孔質シリコンを酸化
するときに、そこに含まれる不純物が周囲のシリコン層
に拡散されることを利用して、その高濃度に不純物がド
ープされた領域を形成するものである。A semiconductor integrated circuit device according to the present invention has a shielding effect by forming a region doped with impurities at a high concentration between dielectric layers. However, when porous silicon is oxidized, the impurities contained therein are diffused into the surrounding silicon layer to form a region doped with impurities at a high concentration.
以下、図面に従って、本発明の実施例につき説明する。Embodiments of the present invention will be described below with reference to the drawings.
第１図は、本発明による半導体集積回路装置の一例の正
面断面図を示したもので、ＭＰＮ）ランジスタを複数具
えた列を示している。単結晶シリコンの島１０．１１は
多孔質シリコンを酸化して得られたシリコン酸化物１２
．１３によって分離され、それぞれの島の中にＮＰＮ）
ランジスタか形成されている。二つのクリコン酸化物１
２．１３の間にはＮ型の不純物を高濃度に含む領域１４
゜１５が形成されている。この二つの領域１４．１５は
基板表面では接するように形成されている。なお、シリ
コン酸化物１２．１３はその両側にＮ型の不純物を高濃
度に含む領域が形成されるので、単結晶シリコンの島内
に形成されたＮ型の不純物を高濃度に含む領域１６を埋
込層１７とコレクタ電極を接続する高導電層として利用
することができる。FIG. 1 shows a front cross-sectional view of an example of a semiconductor integrated circuit device according to the present invention, showing a row including a plurality of MPN transistors. Single-crystal silicon islands 10 and 11 are silicon oxide 12 obtained by oxidizing porous silicon.
．． separated by 13 NPN within each island)
A transistor is formed. two cricon oxides 1
Between 2.13 and 13, there is a region 14 containing a high concentration of N-type impurities.
15 is formed. These two regions 14 and 15 are formed so as to be in contact with each other on the substrate surface. Note that since regions containing a high concentration of N-type impurities are formed on both sides of the silicon oxide 12 and 13, the region 16 containing a high concentration of N-type impurities formed within the single-crystal silicon island is buried. It can be used as a highly conductive layer that connects the embedded layer 17 and the collector electrode.
単結晶シリコンの島１０．１１の間に形成される二つの
シリコン酸化物１２．１３は接触することのないように
形成されなければならないが、二つのＮ型の不純物を高
濃度に含む領域１４．１５は重なシ合うようにしなけれ
ばならない。したがって、二つのシリコン酸化物１２．
１３の間隔は、酸化の時間とその際の拡散の距離によっ
て決定される。なお、単結晶シリコン島１０．．１１は
シリコン窒化膜１８を介して多結晶シリコン１９に支持
された構造がこの例では示されている。The two silicon oxides 12.13 formed between the single-crystal silicon islands 10.11 must be formed so that they do not come into contact with each other, but the two regions 14 containing a high concentration of N-type impurities .15 must be made to overlap. Therefore, two silicon oxides 12.
The spacing of 13 is determined by the oxidation time and the diffusion distance during the oxidation. In addition, single crystal silicon island 10. ．． In this example, a structure in which 11 is supported by polycrystalline silicon 19 via a silicon nitride film 18 is shown.
上記の例では、バイポーラトランジスタを具えた半導体
集積回路装置を示したが、ＭＯ８）ランジスタ、接合型
電界効果トランジスタ等、単結晶の島にはいかなる素子
を形成しても良い。また、支持基板も多結晶シリコンに
限られず、どのような基板であっても同様に形成できる
。Although the above example shows a semiconductor integrated circuit device including a bipolar transistor, any element such as an MO8 transistor or a junction field effect transistor may be formed on the single crystal island. Further, the support substrate is not limited to polycrystalline silicon, and any substrate can be formed in the same manner.
第２図は本発明による半導体集積回路装置の製造方法の
一列を示す正面断面図であシ、分離のための絶縁領域の
形筬と菌濃度不純物拡散層の形成の工程を示したもので
ある。これらの工程は素子を形成する前に行われるのが
普通であるが、場合によっては後の工程としても良い。FIG. 2 is a front cross-sectional view showing one line of the method for manufacturing a semiconductor integrated circuit device according to the present invention, showing the shape of an insulating region for isolation and the steps of forming a germ-concentrated impurity diffusion layer. . These steps are normally performed before forming the element, but may be performed later in some cases.
Ｎ型の単結晶シリコン基板２０の一部にＰ型不純物をド
ープしてＰ型の不純物を含む領域２１を一定の間隔を置
いて形成する（Ａ）。このＰ型の領域２１は後に絶縁領
域となる部分に形成するもので、底面のシリコン窒化膜
２２に到達するように形成しなければならない。このＰ
型の不純物を含む領域の形成は、拡散イオン注入のいず
れによつても良い。A portion of an N-type single crystal silicon substrate 20 is doped with a P-type impurity to form regions 21 containing P-type impurities at regular intervals (A). This P-type region 21 is formed in a portion that will later become an insulating region, and must be formed so as to reach the silicon nitride film 22 on the bottom surface. This P
The region containing type impurities may be formed by any method of diffusion ion implantation.
なお、Ｐ型の不純物を含む領域２１を形成するのは、後
の陽極化成を容易にするためであシ、基板がＰ型である
場合、および光を轟ててＮ型のまま陽極化成する場合に
は形成する必要はない。Note that the reason for forming the region 21 containing P-type impurities is to facilitate the subsequent anodization.If the substrate is P-type, and if the substrate is anodized while remaining N-type by emitting light, In some cases, it is not necessary to form.
次に、Ｐ型の不純物を含む領域２１以外の部分をシリコ
ン窒化膜２３で覆って、陽極化成処理を行う（Ｂ）。陽
極化成処理はフッ化水素（ＨＦ）溶液中で行なうので、
シリコン窒化膜２３はシリコン酸化嘆や単結晶シリコン
が侵されることを防ぐだめに形成されたものである。フ
ッ化水素溶液中で陽極化成処理されたＰ型の単結晶シリ
コンは多孔質シリコ７２４となる。Next, a portion other than the region 21 containing P-type impurities is covered with a silicon nitride film 23, and anodization treatment is performed (B). Since anodization treatment is performed in a hydrogen fluoride (HF) solution,
The silicon nitride film 23 is formed to prevent silicon oxidation and single crystal silicon from being attacked. P-type single crystal silicon subjected to anodization treatment in a hydrogen fluoride solution becomes porous silicon 724.
多孔質シリコン２４にＮ型の不純物を高濃度にドープす
る（Ｃ）。このドープは通常は真空ドーピング法で行う
。Porous silicon 24 is doped with N-type impurities at a high concentration (C). This doping is usually done by vacuum doping.
多孔質シリコンは酸化され易い性質を有している。した
がって、酸素雰囲気中で高温で処理すると、多孔質シリ
コンは二酸化シリコン２５に変化する（Ｄ）。このとき
、多孔質シリコン内に高濃度にドープされていたＮ型の
不純物は周囲の単結晶シリコン２０内に拡散される。こ
の拡散によって二酸化シリコン２５の底面、上面を除く
周囲にＮ型の不純物を高濃度に含む領域２６．２’７が
形成される。単結晶シリコン内のＮ型の不純物を高濃度
に含む領域２６と二酸化シリコン２５＆、２５ｂ間の領
域２７とは同じ深さとＪ４度分布で拡散され ”る。Porous silicon has the property of being easily oxidized. Therefore, when processed at high temperature in an oxygen atmosphere, porous silicon changes to silicon dioxide 25 (D). At this time, the N-type impurity doped in the porous silicon at a high concentration is diffused into the surrounding single crystal silicon 20. This diffusion forms a region 26.2'7 containing a high concentration of N-type impurities around the silicon dioxide 25 except for the bottom and top surfaces. The region 26 containing a high concentration of N-type impurities in the single crystal silicon and the region 27 between the silicon dioxide 25&, 25b are diffused to the same depth and with a J4 degree distribution.
二酸化シリコン２５ａ、２Ｓｂ間に形成される二つのＮ
型の不純物を高濃度に含む領域２７ａ。Two N atoms formed between silicon dioxide 25a and 2Sb
A region 27a containing a high concentration of type impurities.
２７ｂは少くともその一部が当接し重なり合うように形
成される。そのために、二酸化シリコン２５ａ、２５ｂ
の間隔と酸化の時間（これによって拡散距離が決定され
る）を調整しておかなければならない。27b are formed so that at least a portion thereof abuts and overlaps. For that purpose, silicon dioxide 25a, 25b
and the oxidation time (which determines the diffusion distance) must be adjusted.
Ｎ型の不純物を高濃度に含む領域は、深さ方向に一足の
濃度分布を有している。したがって、どの部分において
も高導電率となっているので、単結晶シリコンの島はシ
リコン酸化物の誘電体層で囲まれるとともに導電層で囲
まれていることにもなる。このことから、Ｎ型の不純物
を高濃度に含む領域のうち、シリコン酸化物の間に存在
する部分に電極を形成し、この電極を第３図のように接
地電位に接続すれば、単結晶シリコンの島を取シ囲むシ
ールド層として利用することができる。The region containing a high concentration of N-type impurities has a concentration distribution in the depth direction. Therefore, since the conductivity is high in all parts, the island of single crystal silicon is surrounded by a dielectric layer of silicon oxide and also by a conductive layer. Therefore, if an electrode is formed between the silicon oxides in the region containing a high concentration of N-type impurities and this electrode is connected to the ground potential as shown in Figure 3, it is possible to form a single crystal. It can be used as a shield layer surrounding the silicon island.
なお、基板や不純物の導電型は上記の例に限られるもの
ではなく、池の組み合わせが可能であるのはいうまでも
ない。Note that the conductivity types of the substrate and impurities are not limited to the above examples, and it goes without saying that combinations of cells are possible.
本発明によれば、素子を形成１する単結晶シリコンの島
と島の間をシールドすることができ、素子の特性を大幅
に向上させることのできる半導体集積回路装置が得られ
る。According to the present invention, it is possible to provide a semiconductor integrated circuit device in which it is possible to shield between the islands of single crystal silicon forming the element 1, and the characteristics of the element can be significantly improved.
また、シールド層の形成は分離のだめの誘電体層の形成
と同時にできるので、特にシールド層の形成のための工
程を必要としない利点もある。Furthermore, since the shield layer can be formed at the same time as the separate dielectric layer, there is an advantage that no special process for forming the shield layer is required.
第１図は本発明による半導体集積回路装置の一例を示す
正面断面図、第２図は本発明による半導体集積回路装置
の製造方法の要部を示す正面断匍図、第３１図は本発明
による半導体集積回路装置の肋の例の一部を示す正面断
面図である。
１２・１３・・・・・・シリコン酸化物。
１４・１５・・・・・・Ｎ型高濃度領域。
２４・・・・・・多孔質シリコン。
２５・・・・・・二酸化シリコン。
２６．２７・・・・・・Ｎ型高濃度領域特許出願人
東光株式会社FIG. 1 is a front cross-sectional view showing an example of a semiconductor integrated circuit device according to the present invention, FIG. 2 is a front cross-sectional view showing main parts of a method for manufacturing a semiconductor integrated circuit device according to the present invention, and FIG. 31 is a front cross-sectional view showing an example of a semiconductor integrated circuit device according to the present invention. FIG. 2 is a front sectional view showing a part of an example of a rib of a semiconductor integrated circuit device. 12/13...Silicon oxide. 14・15...N-type high concentration region. 24...Porous silicon. 25...Silicon dioxide. 26.27・・・N-type high concentration region patent applicant Toko Co., Ltd.
Claims (4)
もに該回路素子部に分離領域を具えた半導集積回路装置
において、該分離領域が多孔質シリコンを酸化した近接
する二つの絶縁層から成シ、該二つの絶縁層の間に高濃
度に不純物を含むシールド層を具えだことを特徴とする
半導体集積回路装置。(1) In a semiconductor integrated circuit device in which a plurality of circuit elements are formed within a single substrate and a separation region is provided in the circuit element portion, the separation region is formed by oxidizing porous silicon between two adjacent insulators. What is claimed is: 1. A semiconductor integrated circuit device comprising a shield layer comprising a plurality of layers and comprising a shield layer containing impurities at a high concentration between the two insulating layers.
することを特徴とする特許請求の範囲第１項記載の半導
体集積回路装置。(2) The semiconductor integrated circuit device according to claim 1, wherein the wiring connected to the shield layer is connected to a ground potential.
所定の間隔を有する二つの領域を陽極化成処理によって
多孔質化し、該多孔質化された領域に不純物を高濃度に
ドープし、該多孔質化された領域を酸素雰囲気中で酸化
処理することによってシリコシ酸化物とするとともに該
シリコン酸化物の周囲に不純物を拡散してシールド層を
形成することを特徴とする特許請求の範囲第１項記載の
半導体集積回路装置の製造方法。(3) making two parallel regions at a predetermined distance apart from each other in a portion of the integrated circuit substrate that will become the separation region porous by anodization treatment, and doping the porous regions with impurities at a high concentration; Claim 1, characterized in that the porous region is oxidized in an oxygen atmosphere to form a silicon oxide, and an impurity is diffused around the silicon oxide to form a shield layer. A method for manufacturing a semiconductor integrated circuit device according to item 1.
てその間に形成される二つの拡散層の少くとも一部を当
接させることを特徴とする特許請求の範囲第６項記載の
半導体集積回路装置の製造方法。(4) The semiconductor according to claim 6, characterized in that the porous silicon is in contact with two insulating layers formed by oxidizing the porous silicon, and at least a portion of two diffusion layers formed therebetween are in contact with the two insulating layers. A method of manufacturing an integrated circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4752183A JPS59172739A (en) | 1983-03-22 | 1983-03-22 | Semiconductor integrated circuit device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4752183A JPS59172739A (en) | 1983-03-22 | 1983-03-22 | Semiconductor integrated circuit device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59172739A true JPS59172739A (en) | 1984-09-29 |
Family
ID=12777414
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4752183A Pending JPS59172739A (en) | 1983-03-22 | 1983-03-22 | Semiconductor integrated circuit device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59172739A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50120280A (en) * | 1974-03-05 | 1975-09-20 | ||
| JPS50120781A (en) * | 1974-03-08 | 1975-09-22 | ||
| JPS5199984A (en) * | 1975-02-28 | 1976-09-03 | Nippon Electric Co | Handotaisochi oyobi sonoseizohoho |
| JPS5263685A (en) * | 1975-11-20 | 1977-05-26 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS5353971A (en) * | 1976-10-26 | 1978-05-16 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS53127282A (en) * | 1977-04-13 | 1978-11-07 | Shindengen Electric Mfg | Semiconductor |
| JPS55111154A (en) * | 1979-02-21 | 1980-08-27 | Hitachi Ltd | Integrated insulated coupler |
| JPS5615141A (en) * | 1979-07-17 | 1981-02-13 | Tokyo Shibaura Electric Co | Large dc current power supply |
| JPS5615574A (en) * | 1979-07-06 | 1981-02-14 | Du Pont | Zero input type tottle link connector |
-
1983
- 1983-03-22 JP JP4752183A patent/JPS59172739A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50120280A (en) * | 1974-03-05 | 1975-09-20 | ||
| JPS50120781A (en) * | 1974-03-08 | 1975-09-22 | ||
| JPS5199984A (en) * | 1975-02-28 | 1976-09-03 | Nippon Electric Co | Handotaisochi oyobi sonoseizohoho |
| JPS5263685A (en) * | 1975-11-20 | 1977-05-26 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS5353971A (en) * | 1976-10-26 | 1978-05-16 | Matsushita Electric Ind Co Ltd | Production of semiconductor device |
| JPS53127282A (en) * | 1977-04-13 | 1978-11-07 | Shindengen Electric Mfg | Semiconductor |
| JPS55111154A (en) * | 1979-02-21 | 1980-08-27 | Hitachi Ltd | Integrated insulated coupler |
| JPS5615574A (en) * | 1979-07-06 | 1981-02-14 | Du Pont | Zero input type tottle link connector |
| JPS5615141A (en) * | 1979-07-17 | 1981-02-13 | Tokyo Shibaura Electric Co | Large dc current power supply |
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