JPS59163935A - Data communication equipment - Google Patents

Abstract

PURPOSE:To attain transmission/reception of a clock signal and a data on one communication line by using a data signal of signal form comprising a clock signal section, a data signal section and a return section formed sequentially in time series. CONSTITUTION:One signal line 13 is installed between a master device 11 and a slave device 12 and a data signal S3 is transmitted and received bidirectionally. The data section TB for one bit's share of the signal S3 is divided equally into three sections T1-T3. The section T1 is the clock signal section, where the level falls down to zero level at the start point of time of the data. The level at the section T2 being the data signal section goes to 1, 0 depending on the contents of the signal S3. The section T3 is the return section and the level is returned to 1 having the same level as the statiolary level in succession to the section T2. Thus, the level of the signal S3 falls down from the 1 level to 0 level at each start of new bit to transmit the clock signal and after the signal S3 falls down at the section T1, the contents of data are transmitted by the level of the signal S3 at a point time in the section T2.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data communication device, and in particular, to a data communication device that allows communication between two devices.
It is designed so that data communication can be performed in both directions using real signal lines.

[Background technology and its problems]

For example, when recording a video signal obtained by capturing an image with a camera on a video tape recorder (VTR), in order to operate these two devices in synchronization, the VTR is used as a mask device and the camera is used as a slave device to send control signals to and from each other.
For data signals including mode signals, answer signals, etc. You need to pay 7 yen. In such a case, conventionally, as shown in FIG. 1, two signal lines 3 and 4 are wired between the mask device 1 and the slave device 2, and the first signal line 3
A clock signal 81 (Fig. 2 (A)) is sent from the mask device 1 to the slave device 2 through the clock signal S1, and the data signal S2 (Fig. 2 (ω)) is sent in time sequence in synchronization with this clock signal S1.
) from mask device l to slave device 2 at time t.
The data signal DT12 from time 1 to t2 is transmitted, or the data signal DT21 from time t3 to t4 is transmitted in the opposite direction. In the case of FIG. 1, the signal line 3 of the clock signal S1 is always maintained at the logic "1" level, for example
During the period from t to t2 or from t3 to t4, when each bit of the data signal DT12 or DT21 consisting of bits is sent, it falls to the logic "0" level at a rate of duty cycle.

In order to reliably send and receive the data signal S2 between two devices without dropping it, it is necessary to operate the two devices with the common clock signal S1 while transmitting the data signal S2 in time m? It is important to exchange each bit one by one to avoid A.

However, according to the configuration shown in FIG. 1, two signal lines 3 and 4 must be provided, and therefore there is a limit to simplifying the configuration of the control system for the two devices as a whole.

[Purpose of the invention]

The present invention proposes a data communication device that can communicate clock signals and data signals through one signal line.

[Summary of the invention]

In order to achieve such an object, the present invention provides the following features in a 1-bit interval:
A signal format in which a clock signal section with a first logic level, a data signal section with a logic level representing the data to be transmitted, and a return section with a second logic level that is the same as the steady level are formed in time sequence. data signals are exchanged through one signal line wired between two devices.

〔Example〕

An embodiment of the present invention will be described in detail below with reference to the drawings.

In FIG. 3, 11 is a mask device, 12 is a slave device, and a single signal line 13 is wired between these two devices, and a data signal S3 is transmitted bidirectionally through this signal line 13.
is exchanged.

The data signal S3 has the signal format shown in the 41st case. In other words, the data section TB for 1 bit is divided into three sections T□,
It is equally divided into T2 and T3, and the first section T□ is a clock signal section, which falls to the logic "0" level at the data start time t11. The second interval T2 is a data signal interval, and becomes logic rlJ or "0" depending on the content of the data signal s3 of the bit. Furthermore, the third section T3 is a return section, and the second section T3 is a return section.
2, it returns to the logic "1" level, which is the same as the steady level.

Therefore, the logic level of the data signal S30 falls from the logic "L" level to the logic "0" level every time a new bit starts, so that a clock signal can be transmitted by this fall, and this data signal S3 The content of the data can be transmitted by the logic level of the data signal S3 at, for example, the approximately central time position (-!-position) t of the time point in the interval T2 of the second part 2 where the signal S2 falls in the interval Te.

The mask device 11 is under the control of the controller 21 and receives the signal &
! The slave device 12 also has a shift register n which sends out a 4-bit data signal S3 in time series to 3 and receives the data signal S3 which also arrives in time series. The shift register n is supplied with a clock pulse φ, as shown in FIG. Output to the output circuit of the circuit configuration. The clock pulse φ1 is a rectangular wave with a sufficient period TB as shown in FIG.

A clock pulse φ is applied to the clock input terminal CP of the output circuit Sae.
□ is given a clock pulse φ2 (FIG. 4(C)) whose logic level is inverted by the inverter 26,
The falling edge causes the output of the shift register 22 to change to the logic "
When the output of the shift register 22 is logic "0", it is set to set the Q output to "1" and set the Q output to "0", making this Q output S4 It is given to the switch circuit 27 of the data output circuit 5 as a logic level setting command signal.

The data output circuit 5 has a 1-bit section TB (Fig. 4(A)).
A time-limited operating quantum T having a length of the clock signal interval T1 of
A second mono-multivibrator 29 has a time-limited operating quantum TB of the length of the sum of the clock signal section T and the data signal section 1 and 2. These mono-multi-by-breaks 4 and 29 provide outputs S5 and S6, which fall upon the rising edge of the clock pulse φ1 of the clock pulse generation circuit B, to the switch circuit 270rlJ and the "0" switching terminals a1 and aO, respectively. When the logic level setting command signal S4 is logic "1", the switch circuit 27 connects the output S5 of the vibrator 4 from the "1" switching terminal a1 to the NPN signal line drive circuit side.
The logic level setting command signal S4 is applied to the base of the transistor 310 via the inverter 32, and the logic level setting command signal S4 is
0", the output S6 of the vibrator 4 is similarly applied from the "0" switching terminal aO to the base of the transistor 31 via the inverter 32.

The signal line driving circuit wr30 connects the signal line 13 to a voltage source V at a logic "1" level via a load resistor 33. C, and the connection point P1 between the signal &13 and the load resistor 33 can be grounded via the transistor 31, thereby turning on the transistor 31 when the output of the switch circuit 27 is at the logic "0" level. As a result, the communication line 13 is brought to the ground level (i.e., logic "
Conversely, when the output of the switch circuit 27 is at the logical "1" level, the transistor 31 is turned off, thereby causing the communication line 13 to become an electric voltage V through the resistor 33.

0 voltage level (ie, logic "1" level).

Thus, when the logic "1" data is set in the output circuit, the first multivibrator 4 operates for a limited time due to the fall of the clock signal φ1 because the switch circuit 27 is switched to the rlJ switching terminal a1. A logic "0" output is given to the inverter 32 during the first clock signal interval T1, and soon the time-limited operation of the first multivibrator signal is completed and the second data signal interval T1 is started.
2, the output of the first multivibrator becomes logic "1", which is applied to the inverter 32, and this state is maintained even after entering the third return period T3, thus the signal line 13 The logic level of i2 is the logic rOJ during the first clock signal interval T1 in the 1-bit interval TB, and the data signal interval T2 of i2.
logic "1" during the third return interval T3, logic rl during the third return interval T3
Become J.

On the other hand, when the output circuit U is set to logic "0", the switch circuit 2?・ is switched to "0" cut-off terminal aO, so that the second multivibrator 29 operates for a limited time when the clock signal φ□ falls.
A logic "0" output is given to the inverter 32 during the clock signal interval T1 and the second data 1g interval T2, and soon the time-limited operation of the second multivibrator 29 ends and the third return interval T3 begins. When the output of the second multivibrator 29 becomes logic "1", this is applied to the inverter 32, and thus the signal line 1
The logic level of 3 becomes logic "0" during the first clock signal section T1 and second data signal section T2 in the 1-bit section TB, and becomes logic "1" during the third return section T3.

The controller 21 of the mask device 11 confirmed that the data signal 531 (FIG. 5(A)) loaded into the shift register 22 in this manner was sent to the signal line 13 via the data output circuit 6. Then, after the time of Iyf has passed, all 4 bits are logic "l" (all [
-1'') is loaded into the shift register B, and in the same way, the data output circuit 5 sequentially
It is further sent to the signal line 13 via the output terminal 34.

The slave device 12 responds to the data signal S3 arriving at the input terminal 35 via the signal line 13 in 4-bit increments. That is, the controller 41 of the slave device 12 uses the signal line 13
1, which performs a current operation each time falls to the logic "0" level.
Every time 4 bits of data are received in response to the output of the frequency-divided clock counter 42, a receive-transmit mode signal S8 is generated to switch the slave device 12 between the receive mode and the transmit mode. This receiving and transmitting mode signal S8 is all "1".
When the data signal S3 which is not "" is sent from the master device 11 and is "0", it becomes logic "0" and commands that the next 4-bit data signal S3 should be handled in the send mode. In this transmission mode, the controller 4j transmits 4-bit data to the mask device fi1j+1! However, when it is confirmed that the transmission of this data has been completed, the reception-transmission mode signal S8 is switched to logic "1" level and the next four
Regarding the bit data signal S3, a command is given to respond in the reception mode.

The reception-transmission mode signal S8 whose logic level has been switched to "1" in this manner is given as a set signal to the transmission/reception control circuit 43 made of a flip-flop circuit. The transmission/reception control circuit 43 changes the reception-transmission mode signal S8 from logic "0" to "
1" (which means switching from transmission mode to reception mode), the set operation is forcibly performed, and at this time, the Q output which becomes logic "1" is sent to the first NPN) Run raster 450 based control signal S9
Make this work by giving as: transistor 45
The collector and emitter of the transistor 46 are connected to the base and emitter of a second (7) NPN transistor 46, respectively, and the collector of the transistor 46 is connected to the signal line 13 and the emitter is grounded. Therefore transistor 45
When the transistor 46 is turned on, the base of the transistor 46 becomes grounded, and the transistor 46 turns off, thereby causing the signal line]3 to be connected to the logic given by the signal line J#A operating circuit 44 of the master device 11. This is done to maintain the level.

At this time, a falling portion of the data signal S3 arriving at the input terminal 35 is given as a trigger signal to a clock signal regeneration circuit formed by a third mono-multivibrator 48 via an inverter 47. This vibrator 48 is shown in Fig. 4 (
As shown in 4), the time-limited operation time −! -T
A reproduced clock signal φ11 having the same signal format as the first clock signal φ□ (shown in FIG. 4) generated by the master device 11 is sent out from the Q output terminal. The falling edge of the reproduced clock signal φ□1 is given to the shift register 50 as a shift drive signal, and thus, at the time td of Σ in the 1-bit interval TB (in other words, the data (time Σ of the S interval T2)), the signal is input to the input terminal. The logic level of the data signal section T2 given to the input end of the shift register 5° is input to the lowest digit of the shift register, and then the second digit, the third digit, and the highest digit. digits are shifted sequentially.

In this way, when the 4-bit data signal 531 (FIG. 5) is taken into the shift register 50, the controller 41
transfers this data signal S31 internally, thereby allowing the controller 41 to confirm that the transmission of 4-bit data from the master device 11 to the slave device 12 has been completed. This 6t1. Mackerel result controller 4
1 switches the receive-transmit mode No. 16 S8 to logic "0" level and releases the transmit/receive control circuit 43 to the enable state. At this time, the transmission/reception control circuit 43 transmits the reproduced clock signal φ1□ transmitted from the vibrator 48 to the inverter 5.
The second regenerated clock signal φ2 inverted by 1 is received at the clock input terminal, and the data sent from the output terminal of the shift register 50 is received at the D input terminal. The data on the D input end is included.

On the other hand, when the controller 41 confirms that the transmission of 4-bit data from the mask device 11 to the slave device 12 has been completed as described above, it transfers the 4-bit data signal 533 ( Fifth
Load )) in the figure. However, the data signal S33 of this shift register group is the reproduced clock signal φ1□ (fourth
1 bit interval TB start point t1□
(FIG. 4(A)), the most significant digit is sent out one bit at a time from the output end, and the content of this most significant digit is 1 at a point t. It is read into the transmission/reception control circuit 43 by the second regenerated clock signal φ1° (FIG. 4(C)) which falls at the (41st prisoner), and when its logic level is "1" or "0", it becomes logic "1". Alternatively, the Q output S9 of "0" is given to the transistor 45 of the signal line drive circuit 44. The transistor 45 of the signal line driving circuit w-44 has a fourth monomultivibrator 52. This multivibrator 52 is triggered by the falling edge of 1 bin and maintains a logic "1" from t□1 to t until it reaches the one time axis.
A Q output S10 is connected to the collector of transistor 45.

Therefore, a logic "1" bit is sent from the shift register blade, and the transmission/reception control circuit 43 sends a logic "1" control signal S9.
When the transistor 45 is being transmitted, the transistor 45 is turned on and the base of the transistor 46 is grounded, thereby turning off the transistor 46, disconnecting the signal line 13 from the ground, and setting the logic "1" to the all "1" signal 832. In response to this, when the bit of logic rOJ is sent from the shift register 50 and the transmission/reception control circuit 43 is sending out the control signal s9 of logic rOJ, the transistor 45 is turned off and the vibrator 5 is connected to the base of the transistor 46.
By applying the Q output 810 of logic "1" of 2, the transistor 46 is turned on and the signal 1IiI111
3 is grounded to make it a logic "0".

In this way, the slave device 12 receives the 4-bit data signal 533 (Figure i5 (B) loaded into the shift register blade).
)) is transmitted bit by bit to the mask device 11 via the signal line 13.
However, the operation of sending each bit from the shift register blade to the signal line 13 is based on the all "1" signal 532 (the fifth one) of the data signal S3 transmitted from the master device 11.
The slave device 12 is synchronized with the clock signal φ1 generated by the master device 11. It will work.

The mask device 11 receives the transmitted data signal S33.
The bits are taken into the shift register 22 starting from the least significant digit, and thus the 4-bit data is transferred to the shift register 22.
2, the controller 21 transfers this data internally, thereby allowing the controller 21 to confirm that the transmission of 4-bit data from the master device 11 to the slave device 12 has been completed.

After performing such confirmation, the mask device 11 loads the data signals 831 and S32 from the controller 21 to the shift register n as described above in order to further transmit data signals to the slave device 12 as necessary.

In the above configuration, the mask device 11 is connected to the controller 2.
Data signal 531 to be transmitted to register 4 from 1 to 7 feet
(51st prisoner), each bit of which is applied to the first clock signal φ1 generated in the clock signal generation circuit.
and a second clock signal φ2 which is an inverted signal thereof, the data output circuit 5 converts the data signal S3 into a data signal S3 having the signal format shown in FIG.

The slave device 12 receives the clock signal φ□ at the falling edge of the first clock signal section T1 of the data signal S3.
A regenerated clock signal φ1□ is generated in synchronization with the clock signal φ□, and the logic level of the second data signal section T2, which is sequentially transmitted at the timing of the clock signal φ, is taken into the shift register blade as a data signal by this regenerated clock signal φ□. After that, the data is transferred to the controller 41 for processing.

In this way, when the data transmission from the mask device 11 to the slave device 12 is completed, the mask device 11 similarly synchronizes with the clock signal φ
32 (51st prisoner), and the slave device 12 receives the clock signal section T□ of this all “1” data signal 832.
The first regenerated clock signal φ generated in synchronization with the falling edge of
1 and its inverted signal φ
. The data signal 533 (FIG. 5 (Peng)) loaded from the controller 41 to the shift register blade is converted to a data signal 833 in the signal format of the 41st signal and transmitted to the mask device 1.

At this time, the mask device 11 transmits the data signal 8.
33 is taken into the shift register 22 and then transferred to the controller 11 for processing.

Therefore, according to the above configuration, it is possible to realize a data communication device that can reliably exchange the clock I1 and the data signal S3 (FIG. 5(C)) accompanied by data through a single signal line.

In the above description, the signal format of the data signal S3 is the 41st signal format.
Like a prisoner, logic “0” occurs in the clock signal interval T1.
” level and the logic “1” in the return interval T3.
” level, data signal S30 logic “1
Although the clock signal is transmitted using the fall from the logic rOJ level to the logic rOJ level, the same effect as described above can be obtained even if this logic level relationship is reversed.

Furthermore, although the case has been described in which the clock signal section T□, the data signal section T2, and the return section T3 are divided into three equal parts of the 1-bit section TB, this can be divided at any ratio as necessary.

〔Effect of the invention〕

As described above, according to the present invention, the clock signal section T□ of the first logic level (H-filled "OJ" or "1") and the data signal section T2 that generates the logic level representing the data to be transmitted. and a second logic level (logic "1" or "0"
By using a data signal in a signal format formed by sequentially forming the return interval T3 of ") in time series, data communication is possible that allows clock signals and data to be reliably exchanged between two devices using a single wire. A device can be obtained, which allows the number of communication lines to be halved compared to the conventional case.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional data communication device;
The figure shows the signal waveform diagram, Figure 3 is a systematic connection diagram showing one embodiment of the data communication device according to the present invention, and Figures 4 and 5 show the signals of each part. It is a No. 6 waveform diagram. 11...Mask device, 12...Slave device, 13
...signal i, 2], 41...-controller, o...
・Clock signal generation circuit, z4... Output circuit, 5...
・Data output circuit, n...switch circuit, 30...
Signal line drive circuit, 42...1 minute clock counter,
43... Transmission/reception control circuit, 44... Signal line drive circuit. Applicant's agent 1) Motobe Bei

Claims (1)

[Claims] In one bit interval, a clock signal interval of a first logic level, a data signal interval having a logic level representing data to be transmitted, and a return interval having a 20th logic level that is the same as the steady level are formed in time order. A data signal in the form of a signal is exchanged through a single signal line wired between two devices, and the clock signal is transmitted by a change in logic level that occurs at the start of the clock signal section, and the data ( 1. A data communication device characterized in that data is transmitted by a bell using an m-th interval logic.