JPS59152633A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS59152633A JPS59152633A JP58026285A JP2628583A JPS59152633A JP S59152633 A JPS59152633 A JP S59152633A JP 58026285 A JP58026285 A JP 58026285A JP 2628583 A JP2628583 A JP 2628583A JP S59152633 A JPS59152633 A JP S59152633A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- passg
- nitride film
- heat treatment
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims abstract description 37
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- 150000001875 compounds Chemical class 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 17
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 17
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 5
- ZVWKZXLXHLZXLS-UHFFFAOYSA-N zirconium nitride Chemical compound [Zr]#N ZVWKZXLXHLZXLS-UHFFFAOYSA-N 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 238000000034 method Methods 0.000 abstract description 29
- 238000000137 annealing Methods 0.000 abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 10
- 150000004767 nitrides Chemical class 0.000 abstract description 9
- 229910001218 Gallium arsenide Inorganic materials 0.000 abstract description 6
- 229910052681 coesite Inorganic materials 0.000 abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 abstract description 5
- 238000005468 ion implantation Methods 0.000 abstract description 4
- 150000002500 ions Chemical class 0.000 abstract description 4
- 239000000377 silicon dioxide Substances 0.000 abstract description 4
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 4
- 238000002161 passivation Methods 0.000 abstract description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract 1
- 230000003213 activating effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000003475 lamination Methods 0.000 abstract 1
- 238000001704 evaporation Methods 0.000 description 13
- 230000008020 evaporation Effects 0.000 description 12
- 238000005204 segregation Methods 0.000 description 7
- 229910052785 arsenic Inorganic materials 0.000 description 6
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 5
- 229910052733 gallium Inorganic materials 0.000 description 5
- 230000002265 prevention Effects 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- CWNLQDWRSCZYHS-UHFFFAOYSA-N O[Si](O)(O)O.[AsH3] Chemical compound O[Si](O)(O)O.[AsH3] CWNLQDWRSCZYHS-UHFFFAOYSA-N 0.000 description 1
- -1 PAs Chemical class 0.000 description 1
- 229910020489 SiO3 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 208000002564 X-linked cardiac valvular dysplasia Diseases 0.000 description 1
- CTNCAPKYOBYQCX-UHFFFAOYSA-N [P].[As] Chemical compound [P].[As] CTNCAPKYOBYQCX-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical class [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、Ａｓ（ヒ素〕化合物の半導体装置の化学的
な構成比）の変化のない開管熱処理を可能にする半導体
装置の製造方法に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a method for manufacturing a semiconductor device that enables open-tube heat treatment without changing the chemical composition ratio of As (arsenic) compounds in the semiconductor device. It is.
ＧａＡｓ（ガリウム・ヒ素）などのＡｓ化合物の半導体
装置を製造するには、ＧａＡＳ基板にイオン注入された
導電形決定原子を活性化させるために行う７００〜９５
０℃という高温のアニール工程など、多くの高温熱処理
工程が行われている。To manufacture semiconductor devices using As compounds such as GaAs (gallium arsenide), 700 to 95 steps are performed to activate conductivity type determining atoms ion-implanted into the GaAS substrate.
Many high temperature heat treatment processes are performed, such as an annealing process at temperatures as high as 0°C.
ところが、ＧａＡｓなとのＡｓ化合物基板に高温熱処理
をすると、蒸気圧の高いＡｓが蒸発し、基板内 。However, when an As compound substrate such as GaAs is subjected to high-temperature heat treatment, As, which has a high vapor pressure, evaporates and becomes trapped inside the substrate.
のストイキオメトリ−が変化してヴアカンンイ・コンプ
レックス（’Ｖａｃａｎｃｙ Ｃｏｒｎｐｌｅｘ、空格
子点結合〕の発生を招くため電気的特性が不安定になる
ことが知られている。このＡｓの蒸発を阻止するために
、従来Ａｓ化合物半導体基板のアニール工程では、キャ
ップレス−アニール法とキャップ・アニール法とが用い
られていた。It is known that the electrical properties become unstable because the stoichiometry of As changes and the vacancy complex (vacancy bonding) occurs.In order to prevent this evaporation of As, In the conventional annealing process for As compound semiconductor substrates, a capless annealing method and a cap annealing method have been used.
キャップレス書アニール法ハ、アニール、管中にＡｓ馬
ガスを流して熱処理中基板から蒸発するＡｓ蒸気の分圧
とほぼ同程度のＡｓ蒸気の平衡状態を作り出し、これに
より基板からのＡｓ蒸発を防止する熱処理方法である。Capless annealing method C. During annealing, As gas is flowed through the tube to create an equilibrium state of As vapor that is approximately the same partial pressure as the As vapor that evaporates from the substrate during heat treatment, thereby preventing As vapor from evaporating from the substrate. This is a heat treatment method that prevents
一方、キャップ・アニール法は、予じめＡｓ化合物基板
上に窒化ケイ素膜のような蒸発阻止膜（キャップ）を形
成して熱処理を行う方法である。On the other hand, the cap annealing method is a method in which an evaporation prevention film (cap) such as a silicon nitride film is formed on an As compound substrate in advance and heat treatment is performed.
前記のキャップレス・アニール法は、アニール管中のＡ
ｓ分圧の制御が難しいことやＡｓガスの排気処理を要す
ることのために、生産性・再現性・安全性の面で十分で
ない等の問題点があった。In the capless annealing method described above, A
Because it is difficult to control the s partial pressure and the As gas must be exhausted, there are problems in terms of productivity, reproducibility, and safety.
一方、キャップ・アニール法においては、窒化ケイ素膜
の膜厚が１５００Å以上となるとＡｓ化合物基板との熱
膨張などのためアニール中に膜のクラックが生じてＡｓ
及びＧａの蒸発阻止効果が失われ、逆に膜厚が６００λ
以下となるとピンホールが発生し、この場合もＡｓ及び
Ｇａの蒸発阻止効果がなくなるという問題点があった。On the other hand, in the cap annealing method, when the thickness of the silicon nitride film exceeds 1500 Å, cracks occur in the film during annealing due to thermal expansion with the As compound substrate.
And the evaporation prevention effect of Ga is lost, and on the contrary, the film thickness becomes 600λ.
If it is less than that, pinholes will occur, and in this case as well, there is a problem that the effect of inhibiting the evaporation of As and Ga is lost.
！！た、Ｇａのアウトディツー−ジョンについては、窒
化ケイ素膜の生成過程でわずかでも窒化ケイ素膜中に酸
素が入ってしまうと、アウトディフュージョンが促進さ
れこ“の点からも基板のストイキオメトリ−が保てない
という欠点があった。! ! Regarding Ga outdiffusion, if even a small amount of oxygen enters the silicon nitride film during the formation process, outdiffusion will be promoted. The disadvantage was that it could not be maintained.
そこで従来にも、キャップ・アニール法における窒化ケ
イ素膜のクラックやピンポーンの問題点を解決する方法
として、ＧａＡＳ基板の表面に酸化ケイ素膜（Ｓ１０２
膜）を下地膜として形成し、その５ｉ０２膜の上に窒化
ケイ素膜を形成して熱膨張差を緩和するという広義のキ
ャップ・アニール法の試みがなされた。しかしこの従来
の広義のキャップ・アニール法によって、クラックやピ
ンボールの発生は防止できるものの、下地膜として形成
したＳｉＯ２膜中に基板表面のＡｓが偏析移行し、この
点から基板表面（７）Ａｓ化合物のストイキオメ） Ｉ
Ｊ−は十分改善されたものとはならなかった。Conventionally, a silicon oxide film (S102
Attempts have been made to use a broadly defined cap annealing method in which a silicon nitride film is formed on the 5i02 film as a base film to alleviate the difference in thermal expansion. However, although this conventional cap annealing method in a broad sense can prevent the occurrence of cracks and pinballs, As on the substrate surface segregates and migrates into the SiO2 film formed as the base film. Compound Stoichiome) I
J- was not sufficiently improved.
この発明の目的は、前記のとときＡｓ化合物基板のアニ
ール工程における従来技術の欠点及び問題点を生ずるこ
とのないＡｓ化合物半導体装置の製造方法を提供するこ
とである。す々わち、この発明の目的は、従来のキャッ
プ・アニール法や広義のキャップ・アニール法と異なる
新規な拡散阻止膜構成の広義のキャップ・アニール法を
提供することであり、さらに従来キャップ・アニール法
におけるようにＡｓ及びＱａの蒸発やアウトディフュー
ジョンを起こさないこと、及び従来広義のキャップ・ア
ニール法における下地厚のＳｉＯ２膜のようにＡｓ偏析
を起こさないことを図り、その供するとと′である、１
〔発明の概要〕
この発明の製造方法は、Ａｓ化合物の半導体基板表面に
下地膜としてＰＡｓ ＳＧ膜（りん−ヒ素シリケートガ
ラス膜）を形成し、この下地膜の上に窒化シリコン膜、
窒化アルミニウム（ＡＩＮ）膜、窒化チタン（ＴＩＮ、
）膜、窒化ジルコニウム（ＺｎＮ）膜又は炭化シリコン
（ＳｉＣ）膜を形成し、しかる後に所望の熱処理を行う
ことにより半導体装置を製造することを特徴とするもの
であるＬ１熱処理を終えたＰＡＳ ＳＧ膜と窒化物膜は
、次の製造工程のために除去する場合もあり、そのまま
残して最終パッシベーション膜としてもよい。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an As compound semiconductor device that does not suffer from the drawbacks and problems of the prior art in the step of annealing an As compound substrate. In short, the purpose of the present invention is to provide a cap annealing method in a broad sense with a novel diffusion-blocking film structure that is different from the conventional cap annealing method or cap annealing method in a broad sense. We aim to prevent evaporation and outdiffusion of As and Qa as in the annealing method, and to prevent As segregation as in the base-thick SiO2 film in the conventional cap annealing method. Yes, 1 [Summary of the Invention] The manufacturing method of the present invention is to form a PAs SG film (phosphorus-arsenic silicate glass film) as a base film on the surface of an As compound semiconductor substrate, and to form a silicon nitride film, a silicon nitride film, on the base film.
Aluminum nitride (AIN) film, titanium nitride (TIN),
) film, zirconium nitride (ZnN) film, or silicon carbide (SiC) film, and then performs a desired heat treatment to manufacture a semiconductor device. A PAS SG film that has undergone L1 heat treatment. The nitride film may be removed for the next manufacturing process, or may be left as is to serve as the final passivation film.
本発明が適用される半導体基板は、ＧａＡＳのほかＧａ
ＰＡｓ 、 ＧａＡｌＡｓ 、 ＧａＡＩＰＡｓなどの
Ａｓ化合物の半導体基板である。Semiconductor substrates to which the present invention is applied include GaAS as well as GaAs.
This is a semiconductor substrate made of an As compound such as PAs, GaAlAs, or GaAIPAs.
本発明における基板表面に下地膜として形成する°’Ｐ
ＡｓＳＧ膜は、上層の窒化物質の膜に対して熱膨張差の
ストレスを緩和してクラック・ピンホール発生を防止す
るとともに、基板からのＡｓ偏析を少なくするために形
成するものである。前記した従来の広義のキャップ・ア
ニール法におけるＳｉＯ３膜はＡｓ偏析を防止すること
ができず、またＡｓ偏析を防止するだけならばＡｓ５Ｇ
膜（ヒ素−シリケードガラス膜９も考えられるが、Ａｓ
５Ｇ膜は高温アニールの際窒化ケイ素膜と溶融して窒化
ケイ本発明のＰＡｓＳＧ膜は窒化ケイ素膜などの溶融が
△
な〈従来の問題点を一挙に解決できる下地膜なのである
。本発明におけるＰＡｓＳ−Ｇ膜の形成は、熱分解ＣＶ
Ｄ法、プラズマＣＶＤ法あるいは光Ｃ’ＶＤ法によって
形成することができるが、ＰＡｓＳＧ膜形成過程でＡｓ
蒸発が起こらないように加熱の少ないブラ女マＣＶＤ１
及び光Ｃ’ＶＤ法によることが好寸しい。ＰＡＳＳＧ膜
の組成は、ＡＳ偏析量や膜質。°'P formed as a base film on the substrate surface in the present invention
The AsSG film is formed to alleviate the stress caused by the difference in thermal expansion with respect to the upper layer nitride film to prevent the occurrence of cracks and pinholes, and to reduce As segregation from the substrate. The SiO3 film in the conventional cap annealing method described above cannot prevent As segregation, and if only to prevent As segregation, As5G
film (Although an arsenic-silicate glass film 9 is also considered,
The 5G film melts with the silicon nitride film during high-temperature annealing.The PAsSG film of the present invention does not melt the silicon nitride film, etc. (It is a base film that can solve all the problems of the conventional film at once. The formation of the PAsS-G film in the present invention is carried out by thermal decomposition CV
Although it can be formed by the D method, plasma CVD method, or photoC'VD method, As
Bra woman massager CVD1 with low heating to prevent evaporation
It is also preferable to use a photoC'VD method. The composition of PASSG film depends on the amount of AS segregation and film quality.
膜応力を考慮して適宜決定すればよい１）次に本発明に
おいてＰＡｓＳＧ膜に積層される窒化物質膜々どは、Ａ
ｓ及びＧａの拡散阻止膜であるが、特にＧａの アウト
ディフュージョンを阻止するために窒化シリコン膜、窒
化アルミニウム膜、窒化チタン膜、窒化ジルコニウム膜
又は炭化シリコン膜のように窒化シリコン膜と同等以上
のＧ、ａの拡散阻止能を有する膜が必要である。The nitride films to be laminated on the PAsSG film in the present invention may be appropriately determined in consideration of the film stress.
This is a diffusion prevention film for s and Ga, but in particular, to prevent outdiffusion of Ga, a film that is equivalent to or higher than a silicon nitride film, such as a silicon nitride film, aluminum nitride film, titanium nitride film, zirconium nitride film, or silicon carbide film, is used. A membrane having the ability to inhibit the diffusion of G and a is required.
形成するＰＡｓＳに膜厚は少なくとも３００Å以上とす
ることまた窒化物質膜は６００Å以上とするが７００〜
９５０℃のアニールには好ましかった。The thickness of the PAsS to be formed should be at least 300 Å or more, and the thickness of the nitride film should be 600 Å or more, but it should be 700 Å or more.
It was preferable for annealing at 950°C.
以上説明したＰＡｓＳＧ膜と窒化物質膜とを積層シタ場
合に基板のストイキオメトリ−が保持される機構をＧａ
とＡｓとの両元素について次に説明する。先ず、Ｇａに
ついて、ＰＡＳＳＧ膜中のＧａの拡散速度は速いが偏析
係数が小さいことさらに前記したように０．ａのアウト
ディツー−ジョンの小さい窒化物質膜が上層に形成され
ていることによって、基板Ｇａの濃度平衡が保たれ、一
方Ａｓについて、ＰＡｓＳＧ膜が基板表面にあるために
新たに基板からのＡｓの偏析がなく、°窒化物質膜はＰ
ＡｓＳＧ膜上に形成されるのでクラック・ピンホールに
よる蒸発が防止され、結局基板Ａｓが失われることはな
い。Ga
Both elements, As and As, will be explained next. First, regarding Ga, the diffusion rate of Ga in the PASSG film is fast, but the segregation coefficient is small, and as mentioned above, 0. The concentration equilibrium of the substrate Ga is maintained by forming a nitride film with a small out-dissemination on the upper layer, while as for As, since the PAsSG film is on the substrate surface, new As from the substrate is formed. There is no segregation, and the nitride film is P.
Since it is formed on the AsSG film, evaporation due to cracks and pinholes is prevented, and the substrate As is not lost after all.
このように基板のＡＳ及びＧａの両方の蒸発及びアウト
ディソー−ジョンが阻止されるのでストイキオメトリ−
は良好に保持されるのである。In this way, evaporation and out-dissociation of both AS and Ga in the substrate are prevented, resulting in improved stoichiometry.
is well preserved.
以下に第１図乃至第４図を参照して本発明の半導体装置
製造方法の一実施例について説明する。An embodiment of the method for manufacturing a semiconductor device of the present invention will be described below with reference to FIGS. 1 to 4.
この半導体装置製造の熱処理工程は、ホール素子におけ
るＮ−抵抗の形成のためになされるものである。This heat treatment step for manufacturing a semiconductor device is performed to form an N-resistance in a Hall element.
まず、第１図に示すようにＧａＡＳ基板１上にＣ’ＶＤ
法によって５ＩＯ２膜２を厚さ３０００ Ａになるよう
に形成した後、ＳｉＯ□膜２上にレジスト３を塗布、現
像し、さらにＳｉＯ□膜２を選択的にエツチングして、
ＳｉＯ２膜２を開口させ、イオン注入のためにそこにＧ
ａＡＳ基板１の表面を露出させた、。First, as shown in FIG.
After forming the 5IO2 film 2 to a thickness of 3000 A by the method, a resist 3 is applied and developed on the SiO□ film 2, and the SiO□ film 2 is selectively etched.
Open the SiO2 film 2 and inject G into it for ion implantation.
The surface of the aAS substrate 1 is exposed.
次に第２図に示すように、該開口内のＧａＡＳ基板１に
、加速電圧１５０ｋｅＶ、ドーズ量１：Ｘ１０ ＋ｏ
ｎｓ／ｃｉ （Ｄ条件で３ｉイオンを注入してイオン注
入層４を形成した後、基板１上のレジスト６と５１０２
膜２とを全面剥離する。Next, as shown in FIG. 2, an acceleration voltage of 150 keV and a dose of 1:
ns/ci (After forming the ion implantation layer 4 by implanting 3i ions under D conditions, the resist 6 and 5102 on the substrate 1 are
The entire surface of the film 2 is peeled off.
次に第６図に示すように、該基板１上にＰＡＳＳＧ膜５
を厚さ１０００人となるようにプラズマＣ’ＶＤ法によ
って形成した後、その４ｎじプラズマＣ’ＶＤ法によっ
て厚さ１０００λの窒化ケイ素膜６を積層形成した。こ
のＰＡｓＳＧ膜５Ｓ金膜ケイ素膜６とは広義のキャップ
・アニール法のキャップであり、キャップは基板１の少
なくともイオン注入面に°層成すればよいが、イオン注
入面のみならず基板両面に形成するのがより効果的であ
る。Next, as shown in FIG. 6, a PASSG film 5 is placed on the substrate 1.
was formed to a thickness of 1000 λ by plasma C'VD, and then a silicon nitride film 6 having a thickness of 1000 λ was laminated by the 4n plasma C'VD. This PAsSG film 5S gold film silicon film 6 is a cap of the cap annealing method in a broad sense, and the cap may be formed as a layer on at least the ion-implanted surface of the substrate 1, but it can be formed not only on the ion-implanted surface but also on both surfaces of the substrate. It is more effective to do so.
次に前記のごときキャップを施した基板１を８００℃の
Ｎ２雰囲気中１５分間開管熱処理をしてイオン注入層４
を活性化した。Next, the capped substrate 1 as described above was subjected to an open tube heat treatment for 15 minutes in a N2 atmosphere at 800°C to form an ion-implanted layer 4.
activated.
熱処理後、第４図に示すごとく、窒化ケイ素膜６とＰＡ
ｓＳＧ膜５Ｓ金膜択的に開口し、その開口内にＡＩ等か
らなる電極７を形成し、残部の窒化ケイ素膜とＰＡ ｓ
ＳＧ膜は最終的にパッシベーション膜として残した。After the heat treatment, as shown in FIG. 4, the silicon nitride film 6 and the PA
The sSG film 5S gold film is selectively opened, an electrode 7 made of AI or the like is formed in the opening, and the remaining silicon nitride film and PA s
The SG film was ultimately left as a passivation film.
以上のように製造された半導体装置について各種の試験
を行った結果、基板表面のＧａ及びＡｓのストイキオメ
トリ−は全く変化していなかったこと、及び窒化ケイ素
膜６とＰＡｓＳＧ膜５Ｓ金膜ラックやピンホールが全く
生じていなかったこと等が確認された、またＧａ及びＡ
ｓの蒸発アウトティツー−ジョンも生じていなかった。As a result of performing various tests on the semiconductor device manufactured as described above, it was found that the stoichiometry of Ga and As on the substrate surface did not change at all, and that the silicon nitride film 6 and the PAsSG film 5S gold film rack It was confirmed that there were no pinholes or pinholes at all, and that Ga and A
There was no evaporation outtitsu- tion of s.
上記の実施例は、蒸発阻止膜として窒化ケイ素膜を使用
したものであるが、窒化チタン膜、窒化ジルコニウム膜
、窒化アルミニウム膜、炭化ケイ素膜をそれぞれ用いて
上記実施例と同じ製作工程で熱処理を行ったところ、同
様な結果が得られた。The above example uses a silicon nitride film as the evaporation prevention film, but a titanium nitride film, a zirconium nitride film, an aluminum nitride film, and a silicon carbide film were each used and heat-treated in the same manufacturing process as the above example. When I did this, I got similar results.
以上記載したように、この発明の製造方法によれば、熱
処理工程においてＡｓ化合物の半導体基板表面のＧａ及
びＡｓのストイキオメトリ−が保たれるとともに、Ｇａ
及びＡｓの蒸発やアウトディツー−ジョンが生ぜず、ま
た基板上の蒸発阻止膜にクラックやピンホール等の欠陥
のない半導体装置を得ることができる。As described above, according to the manufacturing method of the present invention, the stoichiometry of Ga and As on the surface of the As compound semiconductor substrate is maintained in the heat treatment step, and the Ga
It is also possible to obtain a semiconductor device in which no evaporation of As or out-distraction occurs, and no defects such as cracks or pinholes in the evaporation prevention film on the substrate.
第１図乃至第４図は本発明の製造方法の一実施例におけ
る各工程毎の素子断面図である。
１・・・ＧａＡｓ半導体基板、４・・イオン注入層、５
・・・ＰＡｓＳＧ膜、６・・・窒化ケイ素膜、７・・・
電極。
特許出願人 東京芝浦電気株式会社
代理人 弁理士諸田英二
第１図
第２図
第３図
第４図FIGS. 1 to 4 are cross-sectional views of elements at each step in an embodiment of the manufacturing method of the present invention. 1... GaAs semiconductor substrate, 4... ion implantation layer, 5
...PAsSG film, 6...Silicon nitride film, 7...
electrode. Patent applicant Tokyo Shibaura Electric Co., Ltd. Agent Patent attorney Eiji Morota Figure 1 Figure 2 Figure 3 Figure 4
Claims (1)
形成し、該ＰＡｓＳＧ膜の上に窒化シリコン膜、窒化ア
ルミニウム膜、窒化チタニウム膜、窒化ジルコニウム膜
又は炭化シリコン膜を積層形成し、しかる後に所望の熱
処理をすることを特徴とする半導体装置の製造方法。A PAsSG film is formed on the surface of a semiconductor substrate made of an IAs compound, and a silicon nitride film, an aluminum nitride film, a titanium nitride film, a zirconium nitride film, or a silicon carbide film is laminated on the PAsSG film, and then a desired heat treatment is performed. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58026285A JPS59152633A (en) | 1983-02-21 | 1983-02-21 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58026285A JPS59152633A (en) | 1983-02-21 | 1983-02-21 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59152633A true JPS59152633A (en) | 1984-08-31 |
Family
ID=12189017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58026285A Pending JPS59152633A (en) | 1983-02-21 | 1983-02-21 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59152633A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61140139A (en) * | 1984-12-13 | 1986-06-27 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
-
1983
- 1983-02-21 JP JP58026285A patent/JPS59152633A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61140139A (en) * | 1984-12-13 | 1986-06-27 | Semiconductor Energy Lab Co Ltd | Semiconductor device |
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