JPS59150467A - Manufacture of complementary type semiconductor device - Google Patents

Abstract

PURPOSE:To form a well diffused layer of small substrate effect by reducing impurity concentration and thus contrive to increase the operating speed by ion- implanting an impurity through an oxidation resistant film in addition to an oxide film. CONSTITUTION:An Si oxide film 22 is formed by thermally oxidizing the surface of an n type Si substrate 21, and then an Si nitride film pattern 23' covering an n type active region scheduled part and a p type one is formed. The substrate surface at the part for forming a field oxide film is exposed by forming an SiO2 film 25 and a resist pattern 26 and then etching them, boron is ion-implanted, and thermal oxidation treatment is performed, and accordingly a p-well 27 is formed. Boron concentration is low and diffusion depth is shallow in the p type active region scheduled part covered with said pattern 23', and a field oxide film forming scheduled part in the periphery is formed with a high boron concentration and a deep diffusion depth. Since said concentration in the active region is small, the substrate effect of an n-MOSFET formed in the p-well 27 can be reduced.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a complementary semiconductor device, and particularly relates to an improvement in a method for forming a well diffusion layer. [Technical Background of the Invention] A complementary semiconductor device ( (hereinafter referred to as C-MO8) is a p-channel insulation group) 14 rising effect transistor (hereinafter referred to as p-M
A structure in which an n-channel insulated gate field effect transistor (hereinafter referred to as an n-MOS FET) and an n-channel insulated gate field effect transistor (hereinafter referred to as an n-MOS FET) are formed on the same semiconductor substrate is being developed.

FIG. 1 is an explanatory diagram showing an example of the above-mentioned C-MO8, in which l represents an n-type silicon substrate. The silicon substrate 1 has a p-type well diffusion layer (hereinafter referred to as p-well) 2.
is formed. On the surface of the silicon substrate I, the n
A field oxide film 3 is formed at the boundary between the type region and the p-well 2, and the field oxide film 3 forms an n-type active region for the p-MO8FjW and an n-type active region for the p-MO8FjW.
- The p-type active region for the MOSFET is separated. A p-type source region 4 and a p-type drain region 5 are formed on the surface layer of the n-type active region, and a gate electrode 7 is formed on the channel region with a gate oxide film 6 interposed therebetween. It consists of On the other hand, a source region 4' and a drain region 5' of 11+W are formed in the surface layer of the p-type active region, and a gate voltage @A7' is formed on the channel region through a gate oxide film 6'. n-M, 08FE'l' was created.

Note that 8.8' is a channel stopper area.

As can be understood from the example shown in FIG. 1 above, in order to form C-MO8 on an electrocardiogram type semicircular substrate, a well diffusion layer of the opposite conductivity type is formed on the substrate.1. c. The conventional method for forming this well diffusion layer will be explained below using a p-well as an example.

(1) By heating the surface of the n-type silicon substrate 11 at a high temperature, a heat oxide film 12 is formed that absorbs the entire surface of the silicon substrate 11 (as shown in FIG. 2 (5)). )
(11) Next, a resist pattern 13 is formed to form an opening on the planned p-well portion (as shown in FIG.
Through the process, ions of p-type impurity such as boron are selectively implanted into the planned p-well area (as shown in FIG. 2(C'')).

At this time, it acts as a buffer film to protect the surface of the silicon substrate 11 from the impact of thermally oxidized %H2+i and mefon implantation.

(111) Next, the thermal oxide film 12 is etched using the resist pattern 13 as a mask to expose the surface of the silicon substrate in the planned p-well area (as shown in FIG. 2 (IJ)).

Subsequently, after removing the resist nozzle 13 and the thermal oxide film 12, the silicon substrate 1 is heat-treated at high temperature to drive-in the ion-implanted p-type impurities, thereby forming the p-well 14. 1-ru. As a result of this heat treatment, the surface of the silicon base &
(Second ward 1 (illustrated by Ayan).

In addition, as shown in FIG. 2(C), only the thermal oxide film 12 on the planned p-well portion is first formed into I&J? Therefore, when etching the curdled jJ1tz, traces of the Kpp-fer 4 remain on the surface of the silicon substrate 11, and this trace is used as a reference for mask alignment, etc. in the subsequent C-MO8 manufacturing process.

[Problems with background technology]

By the way, one of the factors that affects the characteristics of the C-MUS shown in FIG. (J
In S i”Ell+, N1 diffusion 4′ and p-
A nine-position difference occurs between well 2 and p-MUSi'E.
When i' is turned on, there is a problem that the channel region between 4 and 5 changes with the phase difference, and therefore the respective 1μ (1 value voltage) changes. This is due to the substrate effect and the
, I-4, and the impurity concentration of 1 unit & regions 1 and 2 is I
MI <7L Runido WJ fill' t [L pressure rises and on-resistance increases. A large trench in the on-resistance causes a decrease in the operating speed. Therefore, in order to improve the operating speed of C-MO8, it is important to reduce the substrate effect by lowering the surface area of the well diffusion layer as much as possible. desirable.

On the other hand, the p-well 14 formed by the conventional method is formed with a relatively high impurity concentration because the amount of ions implanted at the stage shown in FIG. 2(C) is large. Therefore, when the first C-fvfOS is manufactured thereafter, p-
There was a problem that the substrate effect of the n-MOSFET formed in the well 14 was thick (and high-speed operation characteristics could not be obtained).Also, since there were many ion implantations at the stage shown in Fig. 2 <IJ), In the subsequent drive-in process, the expansion 1j becomes thicker (the 1p well 14 has a deeper junction depth and a larger lateral spread.
When MUS is manufactured using the conventional method, p −M (J81
Will the distance between 'E'l' and n-MO811''ET become larger? v1, there was also a problem from the viewpoint of high volume accumulation.

Note that the same situation as described above occurs also when an n-type well diffusion layer is formed in a p-type root.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a method for manufacturing a semiconductor device that can form a well diffusion layer with a small substrate effect, thereby increasing the operating speed.

[Summary of the invention]

Ai 4111 current half-row body construction by ``Main ψ'' 1. The manufacturing method includes the steps of forming an oxide film on the surface of the semi-circular substrate used to mold -4, and further laminating an antioxidizing film thereon, and then forming the side 1 by photolithography. A step of selectively removing the mossifying film, and a step of removing conductive type impurities to the substrate at a rate of 1%. The C region is directly on the substrate, and the remaining region of the oxidation-resistant film is selectively implanted into the well diffusion foot portion through the 4A layer of oxide film and anti-oxidation film, and heat treatment is performed. and activating the ion-implanted impurities to form a well diffusion layer.

As the oxidation-resistant film in the present invention, for example, a silicon nitride film can be used.

In the present invention, the impurity for forming the shell diffusion layer is lj
Because ions are implanted with an antioxidizing film formed outside the dioxide film, the ion range is smaller than in the past, and fewer impurities are introduced into the substrate. Therefore, the impurity concentration of the formed well diffusion layer is reduced, and the substrate effect of the insulated gate field effect transistor formed on the well diffusion layer is reduced, thereby increasing the operating speed.

On the other hand, in the present invention, since a well diffusion layer with a lower degree of impurity is formed, the withstand voltage between the well diffusion layer and the substrate is lower than that of the conventional method.

However, since ion implantation is performed by forming an opening in the 11Ij desensitizing film (and in some cases, the underlying desensitizing film) surrounding the periphery of the well diffusion layer pre-rectangular area, the ion implantation is performed in the peripheral area in contact with the substrate region. Impure! It can form a shell diffusion layer of lq, v's melon, suppressing the breakdown voltage drop.
I can do -4.

[Embodiments of the invention]

Hereinafter, the present invention σ used in the production of C-1vlO8 shown in S Figure 1
] Next to an example, FIG. 3 (5) to (,lJ) are #Il
l;j, expound].

(1) First, by thermally oxidizing the surface of the n-type silicon substrate 21, a silicon removal film 22 with a thickness of about 900A is formed.
was formed, and then a film with a thickness of 120 mm was deposited on it by the CVLI method.
A silicon nitride film 23 of about 0A is formed. Then,
p-1 ~ restrained S1 by PEP! 'Type 11 active region planned area for ET and n-LS4USII'l! , p for T
A resist pattern 24 is formed on the intended area of the pattern and song area (as shown in FIG. 3 (5)).

(11) Next, by patterning the silicon nitride film 23 using the resist pattern 24 as a mask, the n
A silicon evaporation film pattern 23' is formed over the area where the mold is to be occupied and the area where the p-type active area is to be formed. Next, after removing Renst Baku 724, JIMk'3 was applied to the entire surface.
Deposit film 25 of 000^y4H% CVU-8in. Next, a resist pattern 26 is formed using PEP to form an opening on the planned p-well portion (&'v
Figure 3 (B) shown).

(iii) Next, CVJJ=Si02J conversion 25 and υ silicon oxide film 22 are firstly etched as one mask on the resist pattern 26, and the field r'' (8) in the planned p-Ugol area is etched once. The surface of the substrate where Hb is formed is exposed. (With Kl, the resist pattern 26 is used as a flowering mask, and the acceleration pressure is 100.
Boron (131) is ion-implanted into the planned p-well under the conditions of keV and a dose of 5×10 12 AWL2 (as shown in Figure 31 (C)).

At this time, the silicon oxide 11K 22 j'6 and the silicon thickening gland pattern 23' deposit holons at low ω and degrees in the planned p-type active region, and on the other hand, the substrate surface Then, in the area where the field oxide film is to be formed, holons are deposited in the high area.
' is C:VLl-8in formed by etching.

It is a membrane pattern.

(1v) Next, after removing the resist pattern 26,
30 hours at 1200°C? The p-well 27 is also formed by thermal aggregation treatment, and the p-well 27 is first formed by ion implantation and a CC poron drive-in. As a result of this thermal modification treatment, the surface of the silicon substrate, which had previously been exposed, is covered with a monolithic silicon film 22 that has grown into a new layer (
Figure 3 (LJ) and 1).

At this point, as shown in the figure, p-Uni/I/2'7 has a low holon concentration (surface concentration of 3.6
XlO'5 is also formed (8) and has a shallow diffusion depth (formed (5,
7μ), and on the other hand, in the surrounding area where the field enemy film is to be formed, the boron concentration is high and the expanded flk depth is also excluded. This is because, as explained in FIG. 3(C), the deposit of the ion-implanted boron is absorbed.

qv) After that, according to the usual method, the more C-M (
JS can be manufactured. In that case, the field t7 in FIG.
Impurity ion implantation is performed at 111 of the field oxide film formation to form a channel region I<8.8' in the figure.

In this example, as shown in FIG.
Using the -8i02 film 25/ as a mask, ion implantation 28 for p-channel filling is performed on the p-well 27, and after etching the CVD-8itJ2 [z s', the base I
Ion implantation 29 for an N-channel stopper is performed at the FILN exit portion (7'). After that, a field ridged film is formed according to a conventional method.

In the C-MUS manufactured according to the above embodiment, first of all, the boron 1fA in the active region of the p-well 27 is
Since a is smaller than the conventional one, it is possible to reduce the substrate effect of the N-MO8FI (T) formed in the p-well 27 compared to the conventional one.In general, the magnitude of the substrate effect is 1'41 pressure. Since it changes depending on the value, in order to reduce the effect of reducing the substrate effect by 61r+, fix the back gate voltage 111j and set its threshold ↑fL.
However, in C-MUS, the back gate voltage cannot be fixed at a predetermined value because no poles are normally formed on the substrate i+J. Therefore, calculating the effect of reducing the substrate effect by calculation is a second step.

Generally, 1 of the 81 (JS) transistor is the J1 direct pressure (Vt).
h) is given by the following equation.

φ旙; Difference in number between gate electrode and silicon φF; Built-in potential Cox; Capacitance of gate 1 fatigued film Qss;
Charge εsi in the gate cell; Tlj rate ε of silicon. ; Vacuum; Sieve box in the empty state, rate q; Charge of one fitter N5ub: Impurity concentration on the left plate surface From this equation, C MUS iM obtained in the above example and c obtained by the conventional manufacturing method. -Mus, n-■JSi'l,' formed on the p-well
The results of dividing the threshold voltage of l' by 61 are shown in Table 1. When the bank gate voltage value is ov, 2.5v, 5. The reason for reciting the values at OV is that the rule n is C-M S is 5■↑L
Since a source is used, f
li! This is because it is thought that there will be four works.

Note that among the buff meters other than the back gate voltage, φM
Regarding S, φF I Cox *Qss, an n-MO8FET with a general l-engineered polycrystalline silicon gate electrode was used in both the blown example and the conventional example. Also,
For the actual MM example l'Js city, the trace described in the example is 3.6 X I O7cm, and the conventional example N Su
For b, the most common value is 6 X l g 1
5A'yr? -5).

Table 1 This result shows that, according to the above example, p -! 7 x n M, U S formed in Le 27
The surrender effect of I+'+1;'1 is significantly reduced, and +j
'L' can be achieved by trying to improve the speed. Since the range of change in the primary voltage due to changes in the bank gate electrons becomes smaller,・To C-4
(JS production) can be done.

Furthermore, in the example above, the p-soel 27 is formed at its periphery, that is, at the part where the field 1'1 (chemical formation) is formed, since the boron concentration is high (and the diffusion depth can be increased by 1 field). This layer acts as a card ring to prevent a drop in pressure across the surface between the p-well 27 and the substrate 2.

〔Effect of the invention〕

As described in detail above, according to the present invention, the well diffusion layer in the active region where the 8KJSFET is formed is formed with a low temperature to reduce the substrate effect of the insulated gate field effect transistor formed in the well diffusion layer. 11. Remarkable effects include the ability to manufacture complementary semiconductor devices with high speed operation characteristics and reliability. ).

[Brief explanation of the drawing]

Figure 1 is a top view of the i-node showing an example of C-MOS, and the second
'Figures (5) to (E) show the C-MOS manufacturing method'6
Figure 3 (5) to C'f-) are cross-sectional views showing the p-well formation process according to an embodiment of the present invention. It is. 21- n-type silicon substrate, 22... silicon nitride film, 23... silicon nitride film, 23'... 71 electrode electrified film pattern, 24.26... resist pattern, 2 s 1 ．． CVD-8in, IQ, 25/01
．． CVD-8iO2 film pattern, 27...p-well, 28...94712 layer, 29...N 4712 layer.

Claims (1)

[Claims] An oxide film is formed on the surface of a semiconductor substrate that has one conductivity type,
Furthermore, there is a step of laminating an oxidation-resistant film thereon, a step of selectively removing the oxidation-resistant group by photolithography, and a step of adding impurities of the opposite conductivity type to the substrate in areas where there is no oxide film. This is done by selectively implanting ions directly onto the substrate, and by selectively implanting ions into the planned well diffusion layer area through the laminated film of the oxide film and the lf1 eye-supporting film in the remaining region of the oxidation-resistant group, and by heat treatment. 1. A method for manufacturing a complementary semiconductor device 1tffi, which comprises the step of activating ion-implanted impurities to form a well diffusion layer.