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JPS59158127A - Gate driving circuit of gate turn-off thyristor - Google Patents

Gate driving circuit of gate turn-off thyristor

Info

Publication number
JPS59158127A
JPS59158127A JP58030769A JP3076983A JPS59158127A JP S59158127 A JPS59158127 A JP S59158127A JP 58030769 A JP58030769 A JP 58030769A JP 3076983 A JP3076983 A JP 3076983A JP S59158127 A JPS59158127 A JP S59158127A
Authority
JP
Japan
Prior art keywords
gate
thyristor
current
wide
turns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58030769A
Other languages
Japanese (ja)
Other versions
JPH0324817B2 (en
Inventor
Katsuji Iida
克二 飯田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyo Denki Seizo KK
Toyo Electric Manufacturing Ltd
Original Assignee
Toyo Denki Seizo KK
Toyo Electric Manufacturing Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyo Denki Seizo KK, Toyo Electric Manufacturing Ltd filed Critical Toyo Denki Seizo KK
Priority to JP58030769A priority Critical patent/JPS59158127A/en
Publication of JPS59158127A publication Critical patent/JPS59158127A/en
Publication of JPH0324817B2 publication Critical patent/JPH0324817B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/72Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region
    • H03K17/73Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices having more than two PN junctions; having more than three electrodes; having more than one electrode connected to the same conductivity region for dc voltages or currents
    • H03K17/732Measures for enabling turn-off

Landscapes

  • Protection Of Static Devices (AREA)
  • Power Conversion In General (AREA)
  • Thyristor Switches And Gates (AREA)

Abstract

PURPOSE:To allow a simple circuit to perform overdriving and wide-width gating with a narrow-width signal and to eliminate interference between circuits by providing a wide-width on gate circuit, and turning a control thyristor for it on by an on gate transformer and off by an off gate transformer. CONSTITUTION:An on control signal turns on a TRTON at time t1 and the on gate transformer PTON turns on a thyristor SON for prevention against on/off interference to turn on a gate turn-off thyristor GTO. At this time, even the control thyristor SW is turned on to flow a current through a loop including the SW and GTO from a DC power source E, obtaining a wide-width on gate current (figure (b)). The on control signal is ceased at time t2 and the thyristor SON turns off, but the thyristor SW turns on to flow the wide-width on gate current continuously (figure (b)). An off control signal turns off an off TRTOFF at time t3 as shown in a figure (c) to apply a voltage to the off gate transformer PTOFF, and the current of a route shown by a solid line turns off the GTO (figure (d)) to turn on a TRSOFF for turning off the SW. Therefore, the current of the power source E, SOFF, and PTOFF power source E turns off the thyristor SW.

Description

【発明の詳細な説明】 本発明はゲート電流によってオン、オフ動作するゲート
ターンオフサイリスタのゲート駆動回路Iこ関する0 ゲートターンオフサイリスタ(以下GTOと略称する)
は自己消弧能力が有り、機能的に優れた電力用半導体素
子である。しかし、サイリスタに比較しターンオンゲイ
ンは低く、ターンオン時にはオーバードライブが必要と
なる。また保持電流が大きく、オン期間中、サイリスタ
に比較しかなり大きなゲート電流を流さなければならな
い。さらにターンオフ時には、ゲートに非常に大きなオ
フ電流を流さねばならず、100OAの主電流をしゃ断
するには200A以上のオフ電流となる0このため、ゲ
ート回路が複雑で、かなり高価になる傾向がある0これ
は電車用インバータのように主回路電圧が高く、半導体
素子数が多い用途においては、ゲ−ト制御回路との絶縁
の問題もあり顕著となる0第1図は従来のGTOのゲー
ト駆動回路例を示す図で、第2図はその動作説明図であ
るO第1図においてPは直流電源正極端子、Nは直流電
源負極端子% TONはオン用トランジスタ、8ONは
オン/オフ干渉防止用サイリスタs R1# R2は抵
抗、p’roNはオン用絶縁パルストランス(以下オン
用ゲートトランスと称す)で、幅狭のオンゲート回路を
構成する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a gate drive circuit for a gate turn-off thyristor that is turned on and off by a gate current.
has a self-extinguishing ability and is a functionally superior power semiconductor element. However, the turn-on gain is lower than that of a thyristor, and overdrive is required when turning on. In addition, the holding current is large, and during the on period, a considerably larger gate current must flow than in a thyristor. Furthermore, at turn-off, a very large off-state current must flow through the gate, and in order to cut off the main current of 100A, the off-state current is more than 200A.For this reason, the gate circuit tends to be complex and quite expensive. 0 This becomes noticeable in applications such as inverters for trains, where the main circuit voltage is high and the number of semiconductor elements is large, due to the problem of insulation from the gate control circuit. 0 Figure 1 shows the gate drive of a conventional GTO. This is a diagram showing an example of the circuit. Figure 2 is a diagram explaining its operation. In Figure 1, P is the positive terminal of the DC power supply, N is the negative terminal of the DC power supply, TON is the ON transistor, and 8ON is for preventing ON/OFF interference. Thyristor s R1# R2 is a resistor, p'roN is an on-insulation pulse transformer (hereinafter referred to as an on-gate gate transformer), and constitutes a narrow on-gate circuit.

TOFFはオフ用トランジスタ、DPはオンゲート電流
のオフ回路への流入を阻止するダイオード、FTOFF
はオフ用絶縁パルストランス(以下オフ用ゲートトラン
スき称す)で、オフ回路を構成する。
TOFF is a transistor for turning off, DP is a diode that prevents on-gate current from flowing into the off-circuit, and FTOFF
is an OFF insulating pulse transformer (hereinafter referred to as an OFF gate transformer), which constitutes an OFF circuit.

TWI p TW2は高周波で交互にオン、オフする幅
広ゲートパルス発生用トランジスタ、PTwは幅広用絶
縁パルストランス(以下幅広−用ゲートトランスと称す
)、Dwl、Dw2はこの幅広用ゲートトランスPTW
の2次電圧を全波整流するためのダイオード、R3は抵
抗で、幅広オンゲート回路を構成する。
TWI p TW2 is a wide gate pulse generation transistor that turns on and off alternately at high frequency, PTW is a wide insulating pulse transformer (hereinafter referred to as wide gate transformer), and Dwl and Dw2 are wide gate transformers PTW.
A diode for full-wave rectification of the secondary voltage, R3 is a resistor, and constitutes a wide on-gate circuit.

各々のトランジスタの制御信号は第2図(,1)〜(C
)に示すように与えられ、GTOのゲート電流は第2図
(d)に示すよう番こ時間tiでオーバードライブ電流
が流れ始め、時間t2でオーバードライブ電流がなくな
り、幅広ゲート電流として図示のように高周波を全波整
流した電流となる。さらに時間t3でオフゲート電流が
流れGTOをターンオフさせ、時間t4でオフ電流が零
となる。
The control signals for each transistor are shown in Figure 2 (,1) to (C
), and the gate current of the GTO is as shown in Fig. 2(d). At time ti, the overdrive current starts to flow, and at time t2, the overdrive current disappears, and the gate current becomes wide as shown in the figure. The current is a full-wave rectified high-frequency wave. Further, at time t3, an off-gate current flows to turn off the GTO, and at time t4, the off-gate current becomes zero.

この従来例では制御信号が3種類必要となり、回路が非
常ζこ複雑となるOさらに具合が悪いのは、第1図に示
すようにオフ回路電流として実線に示すGTOのカソー
ドからゲートに流れるオフ電流の外に、点線で示すよう
に幅広オンゲート回路にも分流する。特にGTOの主電
流がしゃ断されカソード、ゲート間に電圧を持つように
なると、第1図の点線のみの電流となる。この電流は、
抵抗R3がサイリスタの場合lζ比較しかなり低抵抗(
幅広オン電流として2〜3A以上必要とするのが普通で
ある)であるため、無視できない値となる0この電流は
オフ電流の利用率が低下するばかりではなく、オフゲー
トパルスが消滅する時に、幅広オンゲート回路に流れる
電流も消滅しようとするが、幅広用ゲートトランスPT
wの巻線のインダクタンスおよび回路の配線インダクタ
ンス番こより継続して第1図点線に示す電流を流そうと
する。
In this conventional example, three types of control signals are required, making the circuit extremely complex. What is even worse is that as shown in Figure 1, off-circuit current flows from the cathode of the GTO to the gate, as shown by the solid line. In addition to the current, it is also shunted to a wide on-gate circuit as shown by the dotted line. In particular, when the main current of the GTO is cut off and a voltage is maintained between the cathode and the gate, the current only appears as shown by the dotted line in FIG. This current is
If the resistor R3 is a thyristor, the resistance is quite low compared to lζ (
(2 to 3 A or more is normally required as a wide on-current), so this current is a non-negligible value.0 This current not only reduces the utilization rate of off-current, but also when the off-gate pulse disappears, The current flowing in the wide on-gate circuit also tries to disappear, but the wide gate transformer PT
The current indicated by the dotted line in Figure 1 is attempted to flow continuously due to the inductance of the winding w and the wiring inductance of the circuit.

一方、オフ用ゲートトランスFTOFFはオフ用トラン
ジスタTOFFのしゃ断により逆誘起電圧を発生し、2
次巻線電流を阻止するように動作する0このため上述し
た幅広オンゲート回路の電流は、第2図(d)のゲート
電流波形に時間t4で点線で示すようにGTOのゲート
、カソードに流れ、 GTOをターンオフするおそれが
ある0 したがって幅広オンゲート回路に必ずスイッチ素子が必
要となり、このスイッチ素子を制御する絶縁された制御
信号を発生する回路を併せて考えると非常に複雑な回路
となる。
On the other hand, the OFF gate transformer FTOFF generates a reverse induced voltage due to the interruption of the OFF transistor TOFF, and 2
Therefore, the current in the wide on-gate circuit described above flows to the gate and cathode of the GTO at time t4 in the gate current waveform of FIG. 2(d), as shown by the dotted line. There is a risk of turning off the GTO. Therefore, a switch element is always required in a wide on-gate circuit, and if a circuit for generating an isolated control signal to control this switch element is also considered, the circuit becomes extremely complicated.

さらに幅広オンゲート信号として第2図(d)のゲート
電流に示すように、高周波を全波していることに起因す
るゲート電流の不連続が必ず発生し、GTOの動作に極
めて恕い影響を与える0本発明は上述したような従来の
欠点に鑑みなされたもので、以下本発明を実施例図面に
もとづいて説明する◎第3図は本発明の一実施例を示す
GTOのゲート駆動回路図で、第1図と同一機能をする
ものについては同一符号を付して示しであるOEは幅広
オンゲート電源で、これは絶縁された直流電源であれば
どのようなものでもよい(以下直流電源Bという)。8
wは幅広オンゲート電流をオン・オフする制御用サイリ
スタ、R4は制御用サイリスタSwを制限する抵抗% 
801Fは制御用サイリスタ8wをオフするための8w
オフ用トランジスタ、R5はこのスイッチ素子(8OF
F)をオン・オフする電流を制限する抵抗である。
Furthermore, as shown in the gate current in Figure 2(d), as a wide on-gate signal, discontinuity in the gate current due to the full high frequency is always generated, which has an extremely detrimental effect on the operation of the GTO. 0 The present invention was developed in view of the above-mentioned drawbacks of the conventional technology, and the present invention will be explained below based on the drawings of an embodiment. ◎Figure 3 is a gate drive circuit diagram of a GTO showing an embodiment of the present invention. , OE is a wide on-gate power supply, and any insulated DC power supply may be used (hereinafter referred to as DC power supply B). ). 8
w is the control thyristor that turns on and off the wide on-gate current, and R4 is the resistance % that limits the control thyristor Sw.
801F is 8w for turning off the control thyristor 8w
The off transistor, R5, is this switch element (8OF
F) is a resistor that limits the current that turns on and off.

第3図において、オン制御信号が与えられる幅狭のオン
ゲート回路と、オフ制御信号が与えられるオフ回路の構
成は第1図と同様であるが、本考案においては図示のよ
うに前記直流電源Eを、抵抗R3と制御用サイリスタ8
Wの直列回路を介してGTOのゲートとカソードに接続
した幅広オンゲート回路を備え、この幅広オンゲート回
路の制御用サイリスタ8wの点弧をオン用ゲートトラン
スFTONの2次電圧で行い、オフ用ゲートトランスP
TOFFの2次巻線に接続されたダイオードD、を介し
て8wオフ用トランジスタ5OFFにて制御用サイリス
タSwを短絡するように接続し、この8wオフ用トラン
ジスタ801Fをオフ用ゲートトランスFTOFFの2
次電圧で導通させ、制御用サイリスタSwの消弧を行う
ようlこ構成する。
In FIG. 3, the configurations of the narrow ON gate circuit to which the ON control signal is applied and the OFF circuit to which the OFF control signal is applied are the same as in FIG. , resistor R3 and control thyristor 8
The wide on-gate circuit is connected to the gate and cathode of the GTO through a series circuit of W, and the thyristor 8w for controlling this wide on-gate circuit is fired by the secondary voltage of the on gate transformer FTON, and the off gate transformer is activated by the secondary voltage of the on gate transformer FTON. P
The control thyristor Sw is connected to the 8W off transistor 5OFF via the diode D connected to the secondary winding of TOFF, and this 8W off transistor 801F is connected to the 8W off transistor 5OFF to connect the control thyristor Sw to the 8W off transistor 5OFF.
The control thyristor Sw is configured to conduct at the next voltage and extinguish the arc of the control thyristor Sw.

次に、本発明による第3図実施例回路の動作説明を第4
図を用いて説明する。時間tlにおいて第4図(a)に
示すオン制御信号がオン用トランジスタTONに印加さ
れ、オン用トランジスタTONをオンさせる◎これによ
りオン用ゲートトランスPTONに電圧が加わり、オン
/オフ干渉防止用サイリスタSONがオンするこきによ
って、FTON 2次巻線→抵抗几2→GTOゲート→
GTOカソード→Son→p’r(、N2次巻線の経路
で電流が流れ、GTOをオンさせる。
Next, the operation of the embodiment circuit of FIG. 3 according to the present invention will be explained in the fourth section.
This will be explained using figures. At time tl, the on control signal shown in Fig. 4(a) is applied to the on transistor TON, turning on the on transistor TON.◎This applies voltage to the on gate transformer PTON, and the thyristor for preventing on/off interference When SON turns on, FTON secondary winding → resistor 2 → GTO gate →
GTO cathode → Son → p'r (, N current flows through the path of the secondary winding, turning on the GTO.

この時、抵抗几2の並列回路である抵抗几4→8wカソ
ードの経路にも電流が流れ、制御用サイリスタSwをオ
ンさせる。したがって直流電源Bからも抵抗R)1−)
Sy−+GTOゲート→GTOカソード→直流電直流電
源路で電流が流れ、幅広オンゲート電流(第4図(b)
)となる。
At this time, current also flows through the path of the resistor 4→8w cathode, which is a parallel circuit of the resistor 2, turning on the control thyristor Sw. Therefore, the resistance R)1-) from the DC power supply B is also
Current flows through the Sy-+GTO gate → GTO cathode → DC power supply path, resulting in a wide on-gate current (Figure 4 (b)
).

第4図(、)に示すように時間t2でオン制御信号がな
くなり、オン/オフ干渉防止用サイリスタ8ONがオフ
するが、制御用サイリスタSwは引続きオンして直流電
源Eから幅広オンゲート電流を流し続ける(第4図(b
))。
As shown in FIG. 4(,), at time t2, the on control signal disappears and the on/off interference prevention thyristor 8ON turns off, but the control thyristor Sw remains on and a wide on-gate current flows from the DC power supply E. Continue (Figure 4 (b)
)).

時間t3において第4図(C)に示すようにオフ制御信
号がオフ用トランジスタTOFFに印加され、オフ用ト
ランジスタTOFFをオンする0これによりオフ用ゲー
トトランスFTOF Fに電圧が加わり、第3図に実線
で示した経路にオフ電流が流れ、GTOをオフさせる(
第4図(d))。GTOがしゃ断するとオフ用ゲートト
ランスPTOFFの2次電圧により、8wオフ用トラン
ジスタ8 OFFに第3図に点線で示・す経路に電流が
流れ、 8wオフ用トランジスタ8OFFをオンさせる
。8wオフ用トランジスタ5OFFがオンすることによ
り、制御用サイリスタ8wに流れて、いた電流が8wオ
フ用トランジスタ5OFFに転流し、直流電源E→低抵
抗3→8OFF−+PTOFF 2次巻線→直流電源B
の経路に電流が流れるようになる。この動作により制御
用サイリスタSWがオフし、幅広オンゲート電流が流れ
なくなる(第4図(b))。時間t4でオフ電流は零と
なる。
At time t3, the off control signal is applied to the off transistor TOFF as shown in FIG. The off-state current flows through the path shown by the solid line, turning off the GTO (
Figure 4(d)). When GTO is cut off, current flows through the 8W off transistor 8OFF through the path shown by the dotted line in FIG. 3 due to the secondary voltage of the off gate transformer PTOFF, turning on the 8W off transistor 8OFF. When the 8w off transistor 5OFF turns on, the current flowing through the control thyristor 8w is commutated to the 8w off transistor 5OFF, DC power supply E → Low resistance 3 → 8OFF-+PTOFF Secondary winding → DC power supply B
Current begins to flow through the path. This operation turns off the control thyristor SW, and the wide on-gate current no longer flows (FIG. 4(b)). At time t4, the off-state current becomes zero.

以上述べたように本発明によれば、比較的に簡単な回路
構成で、オン用、オフ用の2つの幅狭の信号でGTOの
オーバードライブ、幅広オンゲート。
As described above, according to the present invention, with a relatively simple circuit configuration, two narrow signals for ON and OFF can be used to overdrive the GTO and provide a wide ON gate.

オフゲートを可能とするばかりでなく、各々の回路間の
干渉を全くなくし、さらに幅広オンゲート電流は完全な
直流電流とすることができるようになり、 GTOの確
実な動作をさせることが可能となる。
This not only makes it possible to turn off the gate, but also completely eliminates interference between each circuit, making it possible to turn the wide on-gate current into a complete direct current, making it possible to operate the GTO reliably.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のゲートターンオフサイリスタのゲート駆
動回路図、第2図は第1図回路の動作説明図、第3図は
本発明の一実施例を示すゲートターンオフサイリスタの
ゲート駆動回路図、第4図は第3図回路の動作説明図で
ある。 TON・・・・・・オン用トランジスタ% TOFF・
・・・オフ用トランジスタ、Twl、Twz・山・幅広
ゲートパルス発生用トランジスタ、FTON・・・・・
オン用絶縁パルストランス、PTOFF・・・・・・オ
フ用絶縁パルストランス、PTw・・・・・・幅広用絶
縁パルストランス、DWI s DW2 tD、・・・
・・・ダイオード、SoN・−・・・・オン/オフ干渉
防止用サイリスタ、 Sw・・・・・・制御用サイリス
タ、8OFF・・・・・・8wオフ用トランジスタ、G
TO・・−ゲートターンオフサイリスタ、R1’=R5
・・・・・抵抗。 特許出願人 東洋電機製造株式会社 代表者 土 井   厚 第 1 図 1.尤z         Z3 力4NF43図 第41児 (OA才J″iき74名81 力!  t4
FIG. 1 is a gate drive circuit diagram of a conventional gate turn-off thyristor, FIG. 2 is an explanatory diagram of the operation of the circuit shown in FIG. 1, and FIG. 3 is a gate drive circuit diagram of a gate turn-off thyristor showing an embodiment of the present invention. FIG. 4 is an explanatory diagram of the operation of the circuit shown in FIG. TON・・・・・・Transistor for ON % TOFF・
...Transistor for off, Twl, Twz/mountain/wide gate pulse generation transistor, FTON...
Isolation pulse transformer for ON, PTOFF...Isolation pulse transformer for OFF, PTw...Isolation pulse transformer for wide width, DWI s DW2 tD,...
...Diode, SoN...Thyristor for preventing on/off interference, Sw...Control thyristor, 8OFF...8W off transistor, G
TO...-gate turn-off thyristor, R1'=R5
·····resistance. Patent applicant Toyo Denki Manufacturing Co., Ltd. Representative Atsushi Doi 1 Figure 1.尤z Z3 Power 4 NF43 Figure 41st child (OA talent J″iki 74 people 81 Power! t4

Claims (1)

【特許請求の範囲】[Claims] 2次巻線に制限抵抗を介してゲートターンオフサイリス
タのゲートとカソードが接続されオン時オーバードライ
ブデートするオン用ゲートトランス、2次巻線にダイオ
ードを介して前記ゲートターンオフサイリスタのカソー
ドとゲートが接続されるオフ用ゲートトランス、直流電
源を制限抵抗と制御用サイリスタの直列回路を介して前
記ゲートターンオフサイリスタのゲートとカソードに接
続した幅広オンゲート回路を備えたゲートターンオフサ
イリスタのゲート回路において、前記幅広オンゲート回
路の制御用サイリスタの点弧を前記オン用ゲートトラン
スの2次電圧で行い、前記オフ用ゲートトランスの2次
巻線に接続された前記ダイオードを介してトランジスタ
にて前記制御用させ、前記制御用サイリスタの消弧を行
うことを特徴としたゲートターンオフサイリスクのゲー
ト駆動回路。
The gate and cathode of the gate turn-off thyristor are connected to the secondary winding through a limiting resistor, and the gate transformer for turning on overdrives when turned on.The cathode and gate of the gate turn-off thyristor are connected to the secondary winding through a diode. In the gate circuit of a gate turn-off thyristor, the gate turn-off thyristor is equipped with a wide on-gate circuit in which a DC power source is connected to the gate and cathode of the gate turn-off thyristor through a series circuit of a limiting resistor and a control thyristor. The control thyristor of the circuit is ignited by the secondary voltage of the ON gate transformer, and the transistor is used for the control via the diode connected to the secondary winding of the OFF gate transformer. A gate drive circuit for a gate turn-off thyristor, which is characterized by extinguishing the arc of a thyristor.
JP58030769A 1983-02-28 1983-02-28 Gate driving circuit of gate turn-off thyristor Granted JPS59158127A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58030769A JPS59158127A (en) 1983-02-28 1983-02-28 Gate driving circuit of gate turn-off thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58030769A JPS59158127A (en) 1983-02-28 1983-02-28 Gate driving circuit of gate turn-off thyristor

Publications (2)

Publication Number Publication Date
JPS59158127A true JPS59158127A (en) 1984-09-07
JPH0324817B2 JPH0324817B2 (en) 1991-04-04

Family

ID=12312883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58030769A Granted JPS59158127A (en) 1983-02-28 1983-02-28 Gate driving circuit of gate turn-off thyristor

Country Status (1)

Country Link
JP (1) JPS59158127A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018074619A (en) * 2016-10-24 2018-05-10 ニチコン株式会社 Gate pulse generating circuit and pulse power supply device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018074619A (en) * 2016-10-24 2018-05-10 ニチコン株式会社 Gate pulse generating circuit and pulse power supply device

Also Published As

Publication number Publication date
JPH0324817B2 (en) 1991-04-04

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