JPS59154836A - Interleaving circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit constitution by using most of write address counters for both write and read in common to produce a remaining read address bit by some arithmetic. CONSTITUTION:An AND gate 240 is closed by a read/write switching signal 206 at data write and an output of a write address counter 211 is selected and appears at the output of a data selector 231. The AND gate 240 is opened at data read and an output of a read address counter 221 is applied to a low-order P1 bit of an RAM address, and then the result of addition between a high-order p1 bit of a write address counter 213 and a p1 bit of the read address counter 221 is applied to the high-order p1 bit of the RAM address, resulting that each bit of n-bit code word written is read at intervals of M-bit allowing to attain the result of interleaving the same as a conventional device.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to the Interleave
Related to circuits, especially RAM (random access memory)
This relates to an interleave circuit using .

[Prior art]

Transmission path (represents a communication system or recording/reproducing system).

(hereinafter the same applies), various errors may occur depending on the characteristics of the transmission path, and the correct information may not be transmitted as is. Therefore, a transmission system is configured to encode and transmit information using an error υ correction code according to the error characteristics of the transmission path, and correct the error υ that occurs during transmission by a decoding operation to restore correct information. is well known in the past.

By the way, if the code errors in the transmission path are random, the errors can be effectively corrected using a simple error correction code with a relatively short code length. If this occurs, the error correction code that corrects this error has low coding efficiency or has a long code word length.
In either case, the configurations of the encoder and decoder become complicated.

Therefore, it is well known to disperse burst errors using an interleave method so that they can be seen as random errors, and to perform correction using a simple random error correction code.

There are roughly two methods for performing interleaving.

One is MxN bits (M is an integer smaller than the number of bits corresponding to the burst error length assumed for the transmission path, N is an integer equal to or larger than the codeword length n) as shown in Figure 1. Prepare two RAMs, set Al to the first key, A2.・
..., AN, Bl, B2. ..., BN, ....

Ml, M2. ..., MN, and at the same time, from the second SI, AI, Bl, CI,
..., Ml, A2゜B2, ...2M2.・
. . , AN, BN, . . . , MN.

When reading and writing are completed for all bits, the first and second RAMs switch roles and read the first key.

At the same time as reading data from the second RAM, new data is written to the second RAM, and such operations are repeated thereafter.

Another method is to use an error correction encoder (
Each bit of the code word output in n-bit parallel from 1) is input to an interleave circuit (21), and shift registers (21) and (22) each having a different delay time.

...(2(n-1)). Delay time τ4 (1, ff
14n-1), the relationship τi=i×τ1 is given, and τ is N
Set it to a value corresponding to the un bit length. In the following explanation, n = N for simplicity, and a 01st order shift register (2υ).

(22), ... (2(n-1)) are assumed to be shifted at a speed of 1/n of the bit rate (with the period to).

Bit O, bit 1, ・ of error correction encoder tll
..., the data output from the terminal indicated by bitn-1 at time t are (bitO) and (bit
l)t,...

When expressed as (bit n-1)t, the times at which these data appear at the output of the interleaving circuit (2) are as follows.

(b 1 t O) Time when t appears = time t (bi
tl) Time at which t appears = time t + τ1 = t + Mt.

(bit 2), the time at which it appears = time t + τ2 = t + 2
Mt.

Time at which (bitn-1) appears = time t+7
=rl-1t+(n-1)Mt.

Conversely, the i-th data biti input to the parallel-to-serial conversion circuit (3) at time t is the data output from the error correction encoder (1) at time t-τ1. Then, the transmission signal train (41) output from the parallel-serial conversion circuit (3)
is...p (b 1 t O,) t, (bl tl
) t-r, (b t t 2 ) t, r...

2 (bttn-t)ti...

n-1゜In this way, the n-bit data that makes up one code word is transmitted M bits apart from each other, so even if a burst error of less than M bits occurs, this burst will The number of bits of the codeword affected is only one bit, and the purpose of random errorization is achieved.

When actually configuring a circuit, if the codeword length is extremely short, shift registers may be arranged in the same manner as shown in Figure 2, but if the codeword length is long or the interleaving length M is large. Since this would increase the number of elements and be uneconomical, the shift register group (21) in FIG. 2 is used in combination with a RAM and a counter.

(22) , . . . , (2(n-1)) is often constructed.

Of the two methods described above, in the first method explained with reference to Figure 1, synchronization of the block composed of MXN bits at the transmitting end and the receiving end is important. In other words, at the receiving end (playing end)
When performing block synchronization (eave), if block synchronization is lost, dinterleaving becomes impossible, so reception cannot be started from the middle of the block.

On the other hand, in the second method explained with reference to FIG. 2, as long as each code word is synchronized, reception is possible from any time by configuring a dinterleave circuit (6) as shown in FIG. That is, the concept of blocks in the first method does not exist in the second method. The interleague circuit (61) in FIG. 3 is the inverse circuit of the interleague circuit (2) in FIG. 2, and since the structure and operation can be easily inferred, a redundant explanation will be avoided.

In the following, a conventional example in which a RAM and a counter are used in place of a shift register to configure an equally constrained circuit for interleaving in the second method described above, and an example according to the present invention that improves this will be described.

Prior to the explanation, let us clarify the size relationship of the symbols used.

(a) N is an integer equal to or greater than the code word length n (b) p is an integer equal to or greater than log N 1 2 Therefore, (a), (b) Yoshin n l N l 2 ”
There is a degree of freedom in choosing ON, but in general it is advantageous to choose an integer that is MAN and M = 2 pl'' p2 (p is an integer).By doing this, the RAM This makes it easier to determine the address location of the address.

Now, FIG. 4 is a block diagram showing an example of a conventional interleague circuit, and in the figure (201) is N x M
R with a capacity of (', 2"pi" p2 ) bits
It is AM. The address position of RAM (201) is p=2
It is specified by p+p 2 address bits, and these address bits are considered to be divided into three units: lower p1 bit, middle p2 bit, and upper p1 bit. In FIG. 4, (231), (232), and (233) are data selectors each having a p□+ p2 y P□ bit parallel output, and select the lower, middle, and upper address bits of the RAM (201) mentioned above. They are divided into three units. (211), (212), (2
13) if: p□ bit n-ary, p2 bit -
An N-ary, p□-bit n-ary counter that is sequentially incremented (Incr) by a write clock (204).
Read clock (205)
is sequentially incremented by

The output data of the write address counters (211) to (213) are applied to the pledge address side input terminals of the data selectors (231) to (233), respectively.
The read address side input terminal has lower p? cut, middle p
2 bits are read address counter (221),
The outputs of (222) are respectively applied, and for the upper p bits, the upper p1 bit counter (
223) and the lower p□ bit counter (221).
od, 2p1) is applied.

In the figure, p□=4. That is, although the case of 8 < n l 16 is shown, the code length is not limited to this range.

Furthermore, the write clock (204) and the read clock (205) do not necessarily have to have the same cycle, but
It is configured such that the number of data looked at and the number of data read out match each other in units of M integers.

By the way, when the burst length becomes dog, the value of M becomes large.
The counters (212), (222) and data selector (232) are large in scale, increasing the number of elements and at the same time, the wiring becomes complicated.

[Summary of the invention]

This invention was made in order to eliminate the above-mentioned drawbacks of the conventional circuit. Most of the write address counter is used for both writing and reading, and the remaining read address bits are generated by a few operations. This provides an interleave circuit with a simplified circuit.

[Embodiments of the invention]

The configuration of the present invention will be explained in detail below using the drawings.

FIG. 5 is a block diagram of an interleague circuit according to the present invention. In the figure, the RAM (201) and write address counters (211) to (213) have the same configuration as in the conventional device shown in FIG. 4, but the read address counter (221) is only one n-ary counter. The p0 bit of the output of the counter is applied through an AND gate (240) to a p0 bit data selector (231) and a p□ bit full adder (250).

Lower p□ of address bits of RAM (201)
The bit is connected to the output of the data selector (231), the upper p□ bit is connected to the output of all 71I multipliers (250), and the middle p2 bit is connected to the output of the p2 bit of the write address counter (212). Part 1
Yes, it is applied. When writing data, read/write switching signal (
20 closes the AND gate (240), and at the same time, the output of the write address counter (211) is selected and appears at the output of the data selector (231).

When reading data, the AND gate (240) is opened and the output of the read address counter (221) is output as the output of the data selector (231) to the lower p0 of the RAM address.
As the bit is added, the upper p0 of the damaged address
The bits include the upper p□ bit of the write address counter (213) and the read address counter (221).
The result of addition with p bits is applied, and as a result, each bit of the written n-bit code word is read out at an interval of M pits, as in the case of FIG.
Interleaving effects equivalent to those of conventional devices can be obtained.

Furthermore, in the circuit of the present invention, even if the value of M becomes large, the amount of RAM g and the write address counter (212
) only increases the number of bits, and the configuration does not become complicated.The above explanation describes the interleaving circuit configuration for a binary code, but it can also be used for a multi-component code on a 2m Galois field. This can be easily handled by using a RAM with m-bit parallel input/output. FIG. 6 shows an example of the configuration when m=4. Since the operation is almost the same as in the case of Fig. 5, I will not explain it in detail, but in the case of Fig. 6, the pledge data (2o2) and the read data (203) are each m-bit parallel, so all of them are Bit serial transmission signal string (4
) is shown using an m-line → 1-line data selector (260). Of course, in parallel →
A similar circuit can be constructed using a serial conversion shift register. [Effects of the Invention] As detailed above, the effect of the present invention is that it is possible to obtain the same increment effect as the conventional circuit with a simple configuration. It is possible to easily cope with the increase in the increment length when the burst error length assumed in the transmission path becomes large. Its practical effects are impressive, such as the ability to easily extend the above multidimensional code.

Note that the gain interleave circuit can be constructed by exchanging the read address counter and the write address counter, and the effect remains the same even if the interleave circuit and the dinterleave circuit are reversed.

[Brief explanation of drawings]

Figure 1 is a key address map in one of the conventional interleave methods, Figure 2 is a circuit configuration diagram using a shift register in another conventional interleave method, and Figure 3 is a digital address map using a shift register. A block diagram of an interleave circuit. Figure 4 is a diagram of a conventional circuit consisting of the interleave circuit shown in Figure 2 and a counter.
FIG. 6 is a circuit diagram showing one embodiment of the present invention, and FIG. 6 is a circuit diagram showing another embodiment of the present invention. 12)...Interleave circuit, (41...Transmission signal train, (201)...RAM, (202)...R
Data written to AM, (203)...Data read from RAM, (204)...Old clock, (205)...Read clock, (2]1.
(212), (213)... write address counter, (220), (221)... read address counter, (231)... data selector, (
240)...AND gate, (250)...Full adder. In addition, the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) Interleaving circuit used to disperse burst errors 9 that occur on the transmission path and convert them into random errors In one path, when the code word length is eN bits and the bit interval to be interleaved is eM bits, at least N-M bits are used. A write clock is input to the RAM with a capacity of (N...
r'N) base write address counter and the corresponding RA
An N-ary read address counter into which the read tally from M is input, and when pl is the smallest integer greater than or equal to log2N, two p1 bit parallel input terminals, one p□ bit output terminal, and a selection signal input terminal are connected. a data selector that applies the lower p0 bit of the write address counter to one input terminal and the p bit of the read address counter to the other input terminal, and outputs either input signal to the output terminal according to a selection signal. and a full adder that adds up the upper p bits of the write address counter and the p pits of the read address counter, excludes carries, and outputs the fcp□ bit; and an input to the read address side input terminal of the full adder. As an address signal to the RAM, all bits of the write address counter are stamped as 1 when writing data, and when reading data, the read address is set to the lower p bits of the W address. The p bit of the counter is set to the upper p□ bit as the total addition result (mod,
1. An interleave circuit characterized in that the interleave circuit is configured such that 2p signal is applied to each. +21 RAM has a capacity of at least m-N'M bits, stores m bits of multi-component code on a 2m Galois field in the same address signal, and has at least N-M address positions. An interleave circuit according to claim 1.