JPS59145569A - Multicollector vertical p-n-p transistor - Google Patents
Multicollector vertical p-n-p transistorInfo
- Publication number
- JPS59145569A JPS59145569A JP2003583A JP2003583A JPS59145569A JP S59145569 A JPS59145569 A JP S59145569A JP 2003583 A JP2003583 A JP 2003583A JP 2003583 A JP2003583 A JP 2003583A JP S59145569 A JPS59145569 A JP S59145569A
- Authority
- JP
- Japan
- Prior art keywords
- type
- layer
- diffusion
- region
- epitaxial layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009792 diffusion process Methods 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 9
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 230000008961 swelling Effects 0.000 claims description 3
- 230000003321 amplification Effects 0.000 abstract description 5
- 238000003199 nucleic acid amplification method Methods 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000004519 manufacturing process Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000926 separation method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000001681 protective effect Effects 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 102000008817 Trefoil Factor-1 Human genes 0.000 description 1
- 108010088412 Trefoil Factor-1 Proteins 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 239000006185 dispersion Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Bipolar Transistors (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は単一のエミッタおよびベースに結合されて複数
のコレクタを有する縦型ＰＮＰ トランジスタ、いわゆ
るマルチコレクタ縦型ＰＮＰ ）７ンジスタに関するも
のである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a vertical PNP transistor having multiple collectors coupled to a single emitter and base, a so-called multi-collector vertical PNP transistor.
従来例の構成とその問題点
マ／Ｌ、 −１−＝ＩレクタｐＮＰ ）ランジスタは、
たとえば電流ミラー結合による電流源回路などに広く用
いられるが、従来、高集積化に有利な構造であるために
、横型構造のものが多く実用されている。The configuration of the conventional example and its problems MA/L, -1-=Irector pNP) The transistor is
For example, they are widely used in current source circuits based on current mirror coupling, and conventionally, many horizontal structures have been put into practical use because they are advantageous for high integration.
しかしながら、従来のマルチコレクタ横型ＰＮＰトラン
ジスタでは、一般に数ミクロン（μｍ）から十数ミクロ
ン（μｍ）に設定されるベース幅の精度が拡散用のマス
ク精度に左右され、この結果、トランジスタ特性のばら
つきが犬であるという問題点があるとともに、通常のバ
イポーラ集積回路内に組み込まれる縦型のＰＮＰ ）ラ
ンジスタにくらべて、電流増幅率ならびにコレクタ遮断
周波数などの特性が劣っているという知１点を有する。However, in conventional multi-collector lateral PNP transistors, the accuracy of the base width, which is generally set from a few microns (μm) to more than ten microns (μm), depends on the accuracy of the diffusion mask, and as a result, variations in transistor characteristics occur. In addition to the problem that it is similar to conventional bipolar integrated circuits, it also has the disadvantage that it has inferior characteristics such as current amplification factor and collector cutoff frequency compared to vertical PNP transistors incorporated in ordinary bipolar integrated circuits.
発明の目的
本発明は縦型構造によって高集積化にも適するマルチコ
レクタＰＮＰ）ランジスタを提供するものである。OBJECTS OF THE INVENTION The present invention provides a multi-collector PNP transistor which is suitable for high integration due to its vertical structure.
発明の構成
本発明は、要約するに、Ｐ形半導体基板上にｎ形埋込み
分離層および多分割されたＰ形埋込み層をｌｅｔ層して
有し、かつ、前記ｎ形およびＰ形の各埋込み層をおおっ
て前記Ｐ形半導体基板上にｎ形エピタキシャル層をそな
え、さらに、前記ｎ形エピタキシャル層内に浅いＰ膨拡
散層、前記多分割イ されたＰ形埋込みｊ
−に達するＰ形多分割拡散領域および前記Ｐ形半導体基
板に達して前記ｎ形エピタキシ斗ル層を島状に分離する
Ｐ形拡散分離領域をそなえだマルチコレクタ縦型ＰＮＰ
）ランジスタであシ、これによれば、電流増幅率、高周
波特性、さらには電流バランスのすぐれたマルチコレク
タトランジスタが得られる。Structure of the Invention To summarize, the present invention has an n-type buried separation layer and a multi-divided P-type buried layer as a let layer on a P-type semiconductor substrate, and each of the n-type and P-type buried an n-type epitaxial layer is provided on the p-type semiconductor substrate, and a shallow p-swelling diffusion layer is provided in the n-type epitaxial layer;
- a multi-collector vertical PNP comprising a P-type multi-divided diffusion region reaching the P-type semiconductor substrate and a P-type diffusion separation region reaching the P-type semiconductor substrate and separating the N-type epitaxial layer into islands;
) According to this transistor, a multi-collector transistor with excellent current amplification factor, high frequency characteristics, and current balance can be obtained.
実施例の説明
第１図および第２図は本発明実施例のマルチコレクタ縦
型ＰＮＰ）う／ジスタの平面パターン図およびそのＡ
−ｋ’断面を現わす一部断面斜視図である。この半導体
装置は、Ｐ形シリコン基板１の表面部に予めｎ形の埋込
み層２および多分割されたＰ形の埋込み層３を形成して
おき、この上にｎ形エピタキシャル層４を形成し、つい
で、Ｐ形拡散分離領域５．Ｐ形多分割払散領域６．浅い
Ｐ膨拡散層７．ならびにｎ形コンタクト層８をそれぞれ
形成した構造である。このとき、Ｐ形拡散分離領域５は
、予め、基板１の表面部に不純物層を設けておき、それ
がｎ形エピタキシャル層４の成長過程で表面側に拡散さ
れる領域と結合されて、結果としてＰ形基板１に達する
ように形成され、同領域５が環状に形成されてｎ形エピ
タキシャル層４を島状に分離する。まだ、多分割された
Ｐ形埋込み層３とＰ形多分割拡散領域６との結合も前述
のＰ形拡散分離領域５の形成方法に準じて行なわれる。DESCRIPTION OF THE EMBODIMENTS FIGS. 1 and 2 are planar pattern diagrams of a multi-collector vertical PNP (U/D) according to an embodiment of the present invention and its A.
It is a partially sectional perspective view showing a -k' cross section. In this semiconductor device, an n-type buried layer 2 and a multi-divided P-type buried layer 3 are formed in advance on the surface of a P-type silicon substrate 1, and an n-type epitaxial layer 4 is formed thereon. Then, the P-type diffusion separation region 5. P-type multi-split dispersion area6. Shallow P swelling diffusion layer7. In this structure, an n-type contact layer 8 and an n-type contact layer 8 are respectively formed. At this time, the P-type diffusion isolation region 5 is formed by providing an impurity layer on the surface of the substrate 1 in advance, and combining it with the region diffused to the surface side during the growth process of the n-type epitaxial layer 4. The region 5 is formed in an annular shape to separate the n-type epitaxial layer 4 into islands. The multi-divided P-type buried layer 3 and the P-type multi-divided diffusion region 6 are also coupled in accordance with the method for forming the P-type diffusion isolation region 5 described above.
これにより、ベース幅がＰ形埋込み層３と浅いＰ膨拡散
層７との間のｎ形エピタキシャル層４の厚みになり、拡
散工程でよく制御されたものになる。なお、この実施例
では、Ｐ形埋込み層３とＰ形拡散領域６とを環状のＰ形
拡散分離領域５の内側に沿って８等分に分割したが、こ
の分割数および形状は比較的自由な設計が可能である。Thereby, the base width becomes the thickness of the n-type epitaxial layer 4 between the P-type buried layer 3 and the shallow P-swelled diffusion layer 7, and the diffusion process is well controlled. In this example, the P-type buried layer 3 and the P-type diffusion region 6 are divided into eight equal parts along the inside of the annular P-type diffusion isolation region 5, but the number of divisions and the shape are relatively free. design is possible.
そして、この装置の最表部には二酸化シリコン膜による
保護絶縁膜９およびこれに開孔されたコンタクト窓を通
じて各部に接触された電極層１０゜１１．１２が設けら
れ、これらは、それぞれ、ユミノタ電極層１０．ベース
電極層１１および多分割の各コレクタ電極層１２となる
。A protective insulating film 9 made of a silicon dioxide film and electrode layers 10, 11, and 12 that are in contact with each part through contact windows formed in the protective insulating film 9 are provided on the outermost part of the device, and these are connected to the Umi-No. Electrode layer 10. A base electrode layer 11 and each multi-divided collector electrode layer 12 are formed.
以上にのべた実施例構造は、コレクタ電極が８分割され
たマルチコレクタ縦型ＰＮＰ トランジスタであり、通
常のバイポーラ集積回路の製造技術ともよく適合してお
り、また、ベース幅も拡散工程で１俺実に割部１される
ので、トランジスタとしての性能も、集積回路要素中の
バイポーラトランジスタと同等に高電流増幅率、かつ、
同波数特性、電流バランスのよいものＫなる。The structure of the embodiment described above is a multi-collector vertical PNP transistor in which the collector electrode is divided into eight parts, and is well suited to the manufacturing technology of ordinary bipolar integrated circuits. In fact, since the performance as a transistor is as high as a bipolar transistor in an integrated circuit element, it has a high current amplification factor and
K has the same wave number characteristics and good current balance.
発明の効果
本発明によれば、マルチコレクタ構造で縦型のＰＮＰ）
ランジスタが容易に実現できる。まだ、本発明のマルチ
コレクタ縦型ＰＮＰ トランジスタは電流増幅率、周波
数特性ならびに電流バランスのいずれの特性面でも高特
性かつ安定性がすぐれており、集積回路の特性向上に寄
与するものである。Effects of the Invention According to the present invention, a vertical PNP with a multi-collector structure
A transistor can be easily realized. Furthermore, the multi-collector vertical PNP transistor of the present invention has high characteristics and excellent stability in terms of current amplification factor, frequency characteristics, and current balance, and contributes to improving the characteristics of integrated circuits.
第１図および第２図は本発明実施例装置の平面パターン
図およびその一部断面斜視図である。
１・・・・・・Ｐ形シリコン基板、２・・・・・・ｎ形
埋込み層、３・・・・・・Ｐ形（多分割）埋込み層、４
・・・・・・ｎ形エピタキシャル層、５・・・・・・Ｐ
形拡散分離領域、６９１．・・Ｐ形（多分割）拡散領域
、７・・・・・・Ｐ膨拡散層、８・・・・・・ｎ＋形拡
散層、８・・・・・ｎ＋形コンタクト領域、９・・・・
・・二酸化シリコン膜、１０・・・・・エミッタ電極層
、１１・・・・・・ヘースｔｆｆ１層、１２・・・・・
・コレクタ（マルチ）電極層。1 and 2 are a plan pattern diagram and a partially sectional perspective view of an apparatus according to an embodiment of the present invention. 1... P-type silicon substrate, 2... N-type buried layer, 3... P-type (multi-division) buried layer, 4
......n-type epitaxial layer, 5...P
shape diffusion separation region, 691. ...P type (multi-division) diffusion region, 7...P swelling diffusion layer, 8...n+ type diffusion layer, 8...n+ type contact region, 9...・
...Silicon dioxide film, 10...Emitter electrode layer, 11...Heas TFF1 layer, 12...
・Collector (multi) electrode layer.
Claims (1)
たＰ形埋込み層を積層して有し、かつ、前記ｎ形および
Ｐ形の各埋込み層をおおって前記Ｐ形半導体基板」二に
ｎ形エピタキシャル層をそなえ、さらに、前記ｎ形エピ
タキシャル層内に浅いＰ膨拡散層、前記多分割されだＰ
形埋込み層に達するＰ形多分割拡散領域および前記Ｐ形
半導体基板に達して前記ｎ形エヒリキシャル層を島状に
分離するＰ形拡散分離領域をそなえだマルチコレクタ縦
型ＰＮＰ）ランジスタ。An n-type buried isolation layer and a multi-divided P-type buried layer are stacked on a P-type semiconductor substrate, and each of the n-type and P-type buried layers is covered with the P-type semiconductor substrate. an n-type epitaxial layer, a shallow P swelling diffusion layer in the n-type epitaxial layer, and a shallow P expansion layer in the n-type epitaxial layer;
A multi-collector vertical PNP transistor comprising a P-type multi-divided diffusion region reaching the P-type buried layer and a P-type diffusion isolation region reaching the P-type semiconductor substrate and separating the N-type epitaxial layer into islands.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003583A JPS59145569A (en) | 1983-02-09 | 1983-02-09 | Multicollector vertical p-n-p transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003583A JPS59145569A (en) | 1983-02-09 | 1983-02-09 | Multicollector vertical p-n-p transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59145569A true JPS59145569A (en) | 1984-08-21 |
Family
ID=12015805
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003583A Pending JPS59145569A (en) | 1983-02-09 | 1983-02-09 | Multicollector vertical p-n-p transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59145569A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH025532A (en) * | 1988-02-04 | 1990-01-10 | Sgs Thomson Microelettronica Spa | P-m-p vertical isolated collector transistor |
| US5032234A (en) * | 1988-12-20 | 1991-07-16 | Minolta Camera Kabushiki Kaisha | Process for plating a printed circuit board |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4879584A (en) * | 1972-01-25 | 1973-10-25 |
-
1983
- 1983-02-09 JP JP2003583A patent/JPS59145569A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4879584A (en) * | 1972-01-25 | 1973-10-25 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH025532A (en) * | 1988-02-04 | 1990-01-10 | Sgs Thomson Microelettronica Spa | P-m-p vertical isolated collector transistor |
| US5032234A (en) * | 1988-12-20 | 1991-07-16 | Minolta Camera Kabushiki Kaisha | Process for plating a printed circuit board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3411051A (en) | Transistor with an isolated region having a p-n junction extending from the isolation wall to a surface | |
| US3702428A (en) | Monolithic ic with complementary transistors and plural buried layers | |
| US3547716A (en) | Isolation in epitaxially grown monolithic devices | |
| US3990102A (en) | Semiconductor integrated circuits and method of manufacturing the same | |
| JPH05175537A (en) | Photo diode array and manufacture thereof | |
| JPH01166560A (en) | Manufacture of complementary semiconductor device with pedestal structure | |
| US4751561A (en) | Dielectrically isolated PMOS, NMOS, PNP and NPN transistors on a silicon wafer | |
| US3390022A (en) | Semiconductor device and process for producing same | |
| GB1260977A (en) | Improvements in semiconductor devices | |
| US3755722A (en) | Resistor isolation for double mesa transistors | |
| JPS59145569A (en) | Multicollector vertical p-n-p transistor | |
| US3797102A (en) | Method of making semiconductor devices | |
| US4144106A (en) | Manufacture of an I2 device utilizing staged selective diffusion thru a polycrystalline mask | |
| JPS59188935A (en) | Dielectric isolation type semiconductor device and manufacture thereof | |
| JPS61172346A (en) | Semiconductor integrated circuit device | |
| JPS5928056B2 (en) | Manufacturing method of semiconductor integrated circuit | |
| JPS63199454A (en) | Semiconductor device | |
| JPH065793A (en) | Fabrication of semiconductor device | |
| JPH03284850A (en) | Semiconductor device | |
| JPS61115345A (en) | Integrated capacitor | |
| JPH02114645A (en) | Bipolar transistor | |
| JPS6134971A (en) | Semiconductor device | |
| JPS6089970A (en) | Semiconductor device | |
| JPS5911660A (en) | Semiconductor integrated circuit device | |
| JPS639667B2 (en) |