JPS59135783A - Josephson memory device - Google Patents

Abstract

PURPOSE:To increase density and the degree of integration while reducing inductance, and to accelerate working speed further by forming a return wire for currents in three-dimensional wiring structure arranged under a base section electrode layer while widening the wiring width of the return wire. CONSTITUTION:An insulating film OX1 is formed on a ground-plane GP, which is disposed on a substrate and consists of a superconductor, and a return wire wiring layer 31' for a bias wire consisting of a superconductor and a wiring 33' for control currents are formed on the insulating film OX1. The layer 31' and the wiring 33' are coated with an insulating film OX2, a base section electrode EB is formed, and two tunnel insulating films OXt are formed separated mutually on the electrode EB. An opposite electrode EC consisting of a superconductor is disposed on the two tunnel insulating films OXt in a cross-linking manner. A plurality of control wires 33 consisting of a superconductor are arranged on the opposite electrode EC through an insulating film. The width of the return wire 31' is windened in order to reduce its inductance.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to Josephson memory foil fabrication, and more particularly to borrowing of Josephson memory cell arrays.

(b) Prior art and problems When arranging memory cells in an array in a memory device, the problem is as shown in Figure 1.
The first control line (X-ray i2) placed in the input direction is different from the opposing memory cell in the adjacent memory cell array in order to increase the operating margin. A second control line (d line) 13 extending diagonally to the memory cells located between the memory cell arrays, and a third control line CI for setting the operating point.
c off seven soto wires) 14 are connected in series.

17. The Josephson element operates by passing a current through the line of the cell j. ) Uζ sot
An α-flow return line for the tl line is required, especially for the bias line 11 and the control line 3 (return line 11' and wiring #IA' are required for each element row in the y-direction 4).
.

Conventionally, Josephson memory circuits have adopted the -plane wiring method, and therefore the above-mentioned return line 1
1; and the wiring 13' is the base electrode (base!L pole) E++
The same electrode layer was used, and the electrode layer was arranged in a plane between the element rows in the X direction. In the same figure, Gp is a ground brain or superconducting substrate, OXI.

OX2. Although OX3 l-i insulating film, Jt and J2 are Joffson junctions, and EC is a counter electrode (counter electrode), the area occupied by one memory cell in the conventional structure is as shown in Figure 2 (→). As shown, the width of the memory cell (
Ax) to return line 11' wiring 13' and second control line 13
The width of the area (-) is the sum of the width (dx+) of the area where
The area ([XIXAy) was the sum of the memory brush length (gxx) and the length of the memory brush - gy).

Here, the width (dx) of the region where the return lines 1.1', 13' and the second control line 13 are arranged is limited by the pattern width that can be formed in the process, so a large reduction is not possible. I can't wait.

Therefore, when miniaturizing memory cells and achieving high-density and high-integration of cell arrays in the conventional structure of the grip-plane wiring method, the large area occupied by the return line wiring area
A problem has arisen in which the high degree of integration is hindered.

In addition, in the course of 75), the bias current flowing into the barrier line of the memory cell MO+ through the counter electrode IDc, the bias current flowing into the barrier line of the memory cell MO+, and the base z1b through the Josephson junctions J1 and J2 in the memory cell MCi. Telephone 11
Flows to memory cell MO2 (flows to memory cell MO2).
C(''1 from the base or pole EB to the note IJ, cell [~
(+7 in 02) It flows to the counter electrode EC through the Josephson junctions J1 and 12, and flows to the memory cell (C3 (t″ in the figure)) arranged in the extension of the counter electrode Frc.

(C) Purpose of the Invention The purpose of the present invention is to realize high-density integration of a Josephnon memory device by using a three-dimensional wiring structure in which a first-stream return line is placed below a base quadrupole layer. At the same time, by widening the wiring width of the return line, the /noduct noise can be reduced, resulting in faster operation speed.
The goal is to provide a hood.

(d) The groove of the invention, that is, the present invention is a memory device having a substrate, a ground plane made of a superconductor disposed on the substrate, and a ground plane on the ground plane. A return line wiring layer and a control line wiring layer of the bias line made of a superconductor arranged therein, an insulating film arranged on the return line, a return line wiring layer of the bias line and a control line wiring layer disposed on the insulating film. a base electrode disposed along the control line wiring layer; a second tunnel insulating film disposed on the base electrode at a distance from each other; a counter electrode made of a superconductor disposed in a bridging manner on a tunnel insulating film and a second tunnel insulating film; and a counter electrode made of a superconductor disposed on the counter electrode with an insulating film interposed therebetween. It is characterized by comprising a memory element having a plurality of control lines.

(e) Embodiments of the Invention Regarding one embodiment of the present invention, a layout diagram of a memory cell array shown in FIG. 3, a perspective top view (A) of a memory cell structure shown in FIG. 4, and a cross section taken along the line A-& This will be explained in detail using diagrams.

In the present invention, the strength of the magnetic field created in the vicinity of a thin film layer wiring is inversely proportional to the width of the wiring, that is, the value of inductance is inversely proportional to the wiring width. The first superconducting wire (the second superconducting wire having the same width as the wire) is narrowed between the first superconducting wire (the ground plane of The superconducting wiring is the same as when a current of 131 ul is applied to this 7'L.
'i: takes advantage of the unique property of superconductors that almost no magnetic field is formed, and connects the bias 1, 1 current return line to the memory cell and the adjacent memory without affecting the characteristics of the memory element. A return line of a control line extending diagonally between cell arrays is installed between the base core layer and the ground brain (')1. ,)1. It was made by sea urchin.

FIG. 3 is a schematic perspective view showing only the essential parts of a memory cell array in an embodiment of the present invention, in which Me is a memory cell, 31 is a bias line (y-line input 32 is an X-direction 1
1ilJ control line, 33 is the control line for the printing direction, 33 is the control line for the diagonal direction, 34 is the control line for operating point 4 and sinking (DC offset line), 31' is the bias 4th flow. return line, 33' is diagonal control/ML wiring (return line), C is wiring connection part, 1yFj Biame lft style, I
df represents four diagonal control flows.

One memory cell area in the memory cell array is shown in the transparent top view (A) of FIG. 4 and its A-
A' arrow sectional view P).

In the same figure, (): P (q ground 9 planes or (1 superconducting substrate), B is base + 1 pole (base - base Tu pole), F
rC is an opposing viewing electrode (counter electrode) 31 is a bias line, 3
2 is a control line in the X direction, 33 is a diagonal control line 34 is a control line (DC offset line) for setting the operating point, 3
1' is a bias current return line, and 33° is a control current line C that flows through a control line extending diagonally between adjacent memory cell arrays. TI, J2 are Josephson junctions, OX t , OX2°OX3. OX4 represents the insulation 11g, and oxt represents the oxide film.

Then, the ground plane (2) is formed using the Pl-I vapor deposition method, for example, a niobium (3000 (A, ))
Nb) consists of a superconducting film, with base polarization EB and counter electrode F.
rC, bias gland 31. Control line in the X direction 32° Control line in the diagonal direction 33. DC O7 seso l-keep, 34° return line 31
．． The wiring 33 is made using the Izunoshi vapor deposition method and has a thickness of 2.
It consists of a superconducting alloy layer such as a lead (,P)t)-indium (In)-gold (-Au) alloy with a degree of conductivity of 500 to 5o++o(X)4. Insulating film (→XI.

OX2. OX3. In case of OX4, both are formed by vapor deposition method71
The tunnel oxide film OXt is formed by high-frequency plasma oxidation on the electrode EB surface. Thickness 50 ('A) rod 1W formed using the method
lead/indium oxide film (PbO/In203) 2%
From 1. (Note that the surface protection insulating film and the like are omitted in this figure.

As is clear from the figure L, in the structure on the main shoulder side, the return line 31' of the bias α flow, the control 1F, and the diversion wiring 3
Σf1. Otsu. Therefore, the distance dx between adjacent cells, which was the conventional return line casting area
2i, for example, the wiring width and phase rj interval are each 3 (,
m) compared to the conventional case, +2-(71111:l
Reduced tI, ro. The cell area of 1 cell area surrounded by the two-dot chain line in the figure is reduced to 7, and the space is reduced to 7.
The product ratio can be calculated to 1 density.

Also, the return line 31' and the wiring 3; width Wy/ and wti'
(base ii pole EB regardless of the expansion of z cell spacing + 1x
You can make a wide shape as shown in the figure by using the lower part of the f, so
The inductance of these return lines is reduced, making memory operation faster.

(1) As described in detail, according to the present invention, when Josephson memory cells are arranged face down in an array α, a portion of the ξ bias line and control line (III line) is placed under the 4th part and the 5th pole. 3-dimensional wiring by arranging the VC, the wiring inductance can be reduced by δt+, jl.

Therefore, the present invention provides high-density high-density high-41S storage devices.
It is extremely effective for debt consolidation and speeding up.

It should be noted that the present invention can be applied to things other than lay shifts.

[Brief explanation of the drawing]

1'fr I L: N1r A schematic half-view showing the layout of the conventional Jean-9 Sefson memory cell array, 1st self-diagram QL Toru γ brother-sen10 of the Josephson fist memory cell of the Congo and Song Dynasty.
Figures 1 (a), 7 to 7-A, / 1-point view (b), and Figure 3 show the memory cell array 1 of the Josephson Society memory cell array 1 in which the present invention is installed. A schematic plan view showing the state of initiation, Figure 4 shows the transparent inkstone ten-sided section 1 (1) &
and A-lV Yaho 1 further view (b). In the figure, MO is a memory cell,] 1, :3115
1st line, 12,32ijx, IN direction: til
l
14, 34・1 Set the cropping point r loop control f, Iu line, 31'lj: Bias, current hood wire, 3: A is 1lilJ I+ttl mixed flow line/gland Q ( is 1 wiring connection part, G p is graph/dope plane, EB is early 2 parts 11 enemies] C is interpolation 4 poles, Jl, J2 are Joseph Soft possible, (,) Xt. OX2.OX3,0X4F, f, insulating film, oxtv:
r, ) y Nell oxide film, ri, no. Patent applicant: Makoto Ishiita, Ltd.

Claims (1)

[Scope of Claims] A substrate, a Guerlain dope made of a conductor disposed on the substrate, and a return line of a bias line made of a superconductor disposed on the ground plane. The wiring layer, the control line wiring layer, the insulating film disposed on the return line, and the return line wiring layer of the bias line and the control line wiring layer. The base electrodes and the other base electrodes were arranged spaced apart from each other on the base and E poles: T! a counter electrode made of a superconductor disposed in a bridging manner between the first tunnel insulating film and the second tunnel insulating film; A Josephson memory device comprising: a memory element having a plurality of control lines made of a superconductor disposed via insulation jjq.