JPS59129438A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a field oxide film by a method wherein a part of the narrow groove provided on a semiconductor substrate is filled up using poly Si, and it is converted to a thermally oxidized film. CONSTITUTION:A recessed part is provided on the surface (100) of a p type Si substrate 21 by superposing an SiO2 film 22 and Si3N4 film 23 using Al 24 as a mask, and B-ion implanted layer 25 is formed. Then, an SiO2 film 26 is buried leaving a narrow groove on the circumference of the recessed part by performing a sputtering method, for example. The above is processed in O2 at 1,000 deg.C and an SiO2 film 27 is covered thereon. Poly Si 28 is deposited approximately one half of the depth of the groove or thereabout, an anisotropic dry etching is performed, and poly Si 29 is left on the side face of the groove alone. When a wet oxidation is performed at a high temperature, the poly Si 29 is converted to SiO2, and the narrow groove is filled up making a flat surface. The Si3N4 23 is removed, a gate oxide film 31 and a gate electrode 32 are attached as usual, and an MOS device is completed. According to this constitution, a relatively thick insulating film can be buried in a field region in such a manner that the surface will be made flat.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device in which a relatively thick field insulating film is embedded in a field region so that the surface thereof is flat.

[Prior art and its problems]

Semiconductor devices using silicon as a semiconductor, especially MO8
In a type semiconductor device, a thick insulating film is formed in a so-called field region between elements in order to eliminate insulation defects due to parasitic channels and to reduce parasitic capacitance.

A selective oxidation method has been well known as a conventional method for such oxidation. This is a technique in which the element formation region is covered with an oxidation-resistant mask, typically a silicon nitride film, and a thick oxide film is selectively formed in the field region by performing high-temperature IF heating. However, in such a selective oxidation method, during the above-mentioned high temperature oxidation.

The field oxide film is embedded in the shape of a bird's beak from the bottom edge of the silicon nitride film. This causes dimensional errors in the element formation region, and further impedes higher integration of integrated circuits.

On the other hand, as a method of eliminating the bird's beak and forming a thick oxide film for isolation between elements, a technique is known in which a field region is etched to form a groove and a field oxide film is buried in the groove.

The steps of this conventional method will be briefly explained below with reference to FIG. As shown in FIG. 1+a+, for example, a thermal oxide film 12 is formed on a silicon substrate 1, an A/film I3 is deposited thereon, and an element forming area is formed with a resist film 14 using a normal photolithography process. Hey, Al! The film 13 and thermal oxide film 12 are patterned. And AI! Using the film 13 as a mask (after etching the silicon substrate 11 by reactive ion etching to a depth corresponding to the desired field insulating film thickness as shown in BL), the field is etched using the Al film 3 as a mask. To prevent reversal, the silicon substrate 11
The inversion prevention layer 15 is formed by ion-implanting an impurity of the same conductivity type as, for example, boron in the case of a P-type substrate. then te
As shown in 1, plasma CVD is applied to the entire surface to a thickness greater than the depth of the groove.
5. Deposit 16+ fotll and etch it with ammonium fluoride solution for about 1 minute. At this time, plasma CVl) S i deposited on the side wall around the element formation region
Since the Ox film is etched more rapidly than the S tO film in other parts, the Sio film on the sidewalls is selectively removed and narrow grooves are formed. After that, when the Al film 13 on the element formation region is removed, the plasma CVD 5 deposited thereon is removed.
iO* is lifted off, resulting in the structure shown in (d). Next, as shown in (e), CVD5 i O! is applied to the entire surface so as to fill the narrow grooves. depositing W 16 t;
Furthermore, in order to flatten the surface by hammering in the four parts of the surface, the etching process (described later) is performed using a 5i
For example, a resist film 17 having the same etching speed as 0211-16+ and 16□ is coated and formed.

After that, as shown in +f), resist) 17 and CVD
SiOtHa l 6. , I6z is uniformly etched to form four element forming regions. fgl is this Φ element formation region' or gate city 1 storm through gate oxide film 18.
9 is shown.

In this conventional method, by using reactive ion etching for etching the silicon substrate, the dimensions of the element area are defined by the dimensions of the mask formed in the photolithography process, and the difference in dimension variation of the element area is zero. It can be done.

However, in the conventional method described above, CVD S is used to fill the narrow groove formed around the field region.
i O! Although the waist is buried, cvns like this
;Since the etching rate of the OT film is faster than that of a thermally oxidized film, the wafer processing process including the dilute hydrofluoric acid process etches more than the normal thermal oxidation film.

Therefore, CVD is applied at the boundary between the element region and the field region.
5 io, the film becomes thinner, and a partial step is formed between the element region and the surface of the semiconductor substrate. This surface step causes a decrease in lithography accuracy after the element isolation process and a decrease in reliability of metal wiring at the surface step. Further, in such a stepped portion, a portion of the side surface of the semiconductor substrate in the element region is exposed. After that, when a transistor (for example, MOS) is manufactured, a parasitic channel is formed on the exposed side surface covered with the gate electrode through the gate oxide film, and the transistor becomes
This causes leakage current in the FF state, leading to deterioration of device characteristics.

Therefore, in the conventional method, it is preferable that the insulating film buried in the above-mentioned narrow groove be a thermal oxide film formed by oxidizing the substrate silicon or polycrystalline silicon rather than the CVD5iO film.

[Purpose of the invention]

The present invention has been made in view of the problems of the conventional method, and includes embedding polycrystalline silicon in at least a portion of the narrow groove,
Next, this is converted into a thermal oxide film by thermal oxidation, and a method for manufacturing a semiconductor device is provided in which 43p of the thermal oxide film is inlaid on the upper d-pi.

[Summary of the invention]

In the method of the present invention, first, the outside of the isolation region on the surface of the semiconductor substrate is covered with a mask material, and the semiconductor substrate is etched using the mask material to form a recess in the isolation region.The recess is then first filled with a first filling pattern. Deposit thin crystalline silicon around the periphery,
4. By performing unilateral etching, the polycrystalline silicon is left in at least a portion of the narrow groove. Thereafter, thermal oxidation treatment is performed to convert the polycrystalline silicon into a silicon oxide film, thereby burying the narrow groove with the silicon oxide film and forming a field oxide film together with the oxide film formed by the first buried ray ♦.

〔Effect of the invention〕

In the method of the present invention, since the narrow grooves can be filled with a film made by thermally oxidizing polycrystalline silicon, the drowsy reliability of the oxide film is significantly lower than that of the conventional method in which CVD SiO*@ is filled. ing. This improves the reliability of the device characteristics.

Furthermore, since the etching speed with hydrofluoric acid is slow, the reduction in oxide film caused by the wafer processing step using hydrofluoric acid is small. Therefore, surface flatness can be obtained. As described above, this is effective in improving the accuracy of subsequent lithography and the reliability of metal wiring. Furthermore, the small thickness of the oxide film is effective in suppressing the formation of parasitic channels in the above-mentioned MOS transistors.A method for inventing device characteristics will be explained in detail with reference to the embodiment shown in FIG.

First, a P-type (100) silicon substrate 21 with a resistivity of about 5-50 pcm is prepared, and after forming a silicon oxide film 22, a silicon nitride film 23, and a mask material such as an AI film 24 on the surface of a region where an element is to be formed, a tat As shown in the figure, the silicon substrate 21 in the isolation region is etched to form a recess. Furthermore, using the same mask, boron ions are implanted into the silicon substrate inside the recess to prevent field reversal 76
25=.

Next, (as shown in Figure b1), a first silicon oxidizing force P26 is first embedded in the periphery of the recessed part by a first embedding process, leaving a γ groove. Fully in a plasma atmosphere.

After depositing the CVD oxide film, the plasma CVD oxide film is deposited on the step part using a buffered hydrofluoric acid solution, which is etched more quickly than the 111: layered film. There is a method in which the plasma CVD oxide film on AJIla is removed by removing the deposited film and then removing the A/film type 4 film. In addition to the plasma CVD oxide film, films having the above-mentioned characteristics include phosphorus silicide glass formed by a reduced FECVD method, an oxide film formed by a sputtering method, and the like.

Next, when heat treatment is performed in an oxygen atmosphere at, for example, 1000° C. (as shown in Figure c1), the silicon wire plate on the front 1 periphery is oxidized due to the action of the silicon nitride film 23.

An oxide film 27 is formed. It was further surrounded by a recess.

The silicon substrate near the interface between the plasma CVD oxide film 26 and the silicon substrate is oxidized.

Next, as shown in Figure d1, a polycrystalline silicon film (
28) is deposited to a thickness of, for example, about 1/2 of the depth of the field recess.

Next, as shown in FIG. te1, the polycrystalline silicon film is etched using an anisotropic dry etching technique, so that the polycrystalline silicon 29 can be left only on the side surfaces of the narrow grooves.

Next) As shown in the figure, for example, after heat treatment for about 30 minutes in a steam atmosphere of 1000°C, the remaining polycrystalline silicon 2
Reference numeral 9 is oxidized and the narrow groove is filled with a silicon oxide film so that the surface is substantially flat.

Thereafter, the silicon nitride film 23 and the silicon oxide layer on the device region are sequentially removed to expose the surface of the device region. next! g
As shown in FIG. 1, a gate oxide film 31 and a gate m-pole 32 are formed in accordance with a conventional method for forming an MO8 type semiconductor device.

According to this embodiment, since the oxide film obtained by thermally oxidizing polycrystalline silicon is buried in the narrow grooves around the field, CVD
Compared to the conventional method using an oxide film, the reliability of child bearing performance is the same as above. Furthermore, the thickness loss of the field oxide film is also reduced, and device characteristics are improved.

Further, in the present invention, polycrystalline silicon is left behind.

Although the method of changing to an insulating oxide film has been described, one example of the present invention is A.
It is also possible to leave the I film and replace it with an alumina film, and then embed the alumina film. If an alumina film is used, field thinning is reduced and excellent U gas insulation properties can be obtained, so it is possible to improve device characteristics.

According to this embodiment, a silicon nitride film 24 is used, and this silicon nitride film selectively forms a thermal oxide film 27 on the side surface of the recess as shown in FIG. can oxidize the interface between silicon and silicon. Therefore, the interface characteristics between the field oxide film and the silicon substrate can be improved, which is also effective in improving device characteristics.

Furthermore, when the polycrystalline silicon film is subjected to anisotropic dry etching as shown in FIG.

(12) Furthermore, the MO8 type semiconductor device has been described above.

Of course, the present invention can also be applied to element isolation of bipolar semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 (at~(gl) is a process cross-sectional view showing an example of the element isolation process of the conventional method %@2I\I (a1~(g) is a process cross-sectional view showing the element isolation process of an example of the present invention. Yes. 11.21...Silicon substrate, 12,22.27...
・Thermal oxide film, 13.24...AIt film, 14...resist film. 15.25...Boron ion implantation layer, 16.26.3
0...Oxide film, 17...Resist film, IFI, 31
...gate oxide film, 19.32...gate t'+b
, 23...Silicon nitride M1.28.29...Polycrystalline silicon film. Representative Patent Attorney Noriyuki Chika (and 1 other person) Figure 1 Figure 1 IE

Claims (1)

[Claims] The first insulator II is formed with an empty groove left around the recess.
'(r filling step, forming a second film thereon, and leaving the second film on at least the side wall of the groove by anisotropic etching the second film, a step of burying a small portion of the second film left in the insulating third film with a third film, and leaving the first and third insulating films in the “interval” portion; exposing the surface of the substrate in the area where the element is to be formed; 1)
A method for manufacturing a semiconductor device, comprising the step of forming an element on the substrate. (2) The semiconductor device described in the patent is characterized in that the first insulating film is a plasma CVD5iO film, a plasma CVD5 fsNnN'J film, a sputter-deposited 810° film, or a phosphosilicate glass film formed by an LPCVD method. Production method. (3) The mask material for forming the recess in the element isolation region includes at least an oxidation-resistant film, and after burying the first insulating film, the oxidation-resistant film is used to cover at least the side walls of the recess and the first insulating film. (4) The mask material contains at least a small amount of oxidation-resistant Li-. A method of manufacturing a semiconductor device according to the present invention, wherein a polycrystalline silicon film is left on a side wall around four parts. (5) A step of meeting areas other than the element isolation region on the semiconductor body with a mask material, a step of forming four parts in the isolation region using the mask material, and a step of forming four parts in the isolation region using the former mask material as an impurity implantation mask. A step of injecting impurities into the substrate, a step of forming an insulating film on the surface over the entire substrate, and a step of selectively etching away the insulating film deposited on the regular walls of the recess to form a pattern around the recess. a step of etching the mask material and simultaneously removing the insulating film deposited on the mask material; and a step of depositing a polycrystalline silicon film over the entire surface of the substrate; The polycrystalline silicon film is anisotropically dry etched to leave at least the polycrystalline silicon film on the side walls of the recess, and the remaining polycrystalline silicon film is removed by thermal oxidation treatment. A semiconductor device comprising the steps of: converting a part of the base body into a thermal oxide film to fill the groove around the recess; dropping the element formation region of the base body; and forming an element on the base body that has fallen off. 1!L manufacturing method for each pattern. (6) The first insulation 1 pattern is a plasma CVD 5IOt film, a plasma CVD SI s N4 n%, or a sputter-deposited StO film or a phosphorus silicide film formed by the LPCVD method. A method for manufacturing a semiconductor device according to Paragraph 45 of the patent claim, characterized in that the film is a glass film. (7) The mask material for forming the four parts in the element isolation region includes at least an oxidation-resistant film. , after embedding the first insulating film, thermally oxidize at least the side walls of the four parts and the semiconductor substrate in the interface region between the first insulating film and the base at the bottom of the recess using an oxidation-resistant layer (8) mask; A method of manufacturing a semiconductor device in which the material includes at least an oxidation-resistant film, and a polycrystalline silicon film is left on the sidewalls around the four parts.