JPS59112498A - Duplex shared memory device - Google Patents

Abstract

PURPOSE:To reduce the delay of an access time at a fault by providing a memory for storing a faulty state with the respective shared memories in a memory device and actuating an access to the shared memory basing on said memory. CONSTITUTION:A master side memory block 23 is started when accessed first to clear the contents of a memory in a logical block 25 and to produce a state having no fault. If an error which cannot be restored is generated in the master side memory block 23, a faulty state signal is sent back to the logical block 25, therefore, when the faulty state signal from the master side memory block 23 is received, the logical block 25 stores it in a memory part 22 basing on an address in that case, and simultaneously, starts a slave side memory block 24. Also, if an error which cannot be restored is generated in the slave side memory block 24, too, the faulty state is sent back to the logical block 25. In this way, the delay of the access time when a fault occurs can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an access method in a memory device such as a duplex shared memory device that is accessed (called) by a plurality of computers, for example.

[Prior art]

FIG. 1 is a 70-chart of the access method in a conventional duplex shared memory device of this type. When a fetch instruction (1) is given to the duplexed shared memory device from , if correct, transfer the 7-etch data to the outside; if incorrect, start the slave side memory block (5), and then transfer the 7-etch data to the outside.
Air check to see if the data is correct (3)
b), and if correct, the fetch data is transferred to the outside; if incorrect, the process moves to an error handling routine (6).

Conventional duplex shared memory devices use the access method described above, so when a 7 etch command is given to the duplex shared memory device, the memory block (2) on the mask side is first uniquely activated. At the same time, since the configuration was such that the slave side memory block (5) is activated only when an unrecoverable error, that is, a failure, occurs in the mask side memory block (2), the mask side memory block ( If a failure occurs in 2), there is a drawback that the access time of the duplex shared memory device becomes extremely slow.

[Summary of the invention]

This invention was made with attention to this point, and it stores the fault status signal from the previous 7-etch operation in the memory in the logic block, and when the 7-etch command is given again at the same address. Before starting the shared memory block, read the memory in the above logic block and access only the shared memory block that is in a normal state based on the fault status signal from the previous 7-step operation. To access a shared memory block that is
It is an object of the present invention to provide a duplex shared memory device that can reduce the delay in access time of the duplex shared memory device.

[Embodiments of the invention]

That is, FIG. 2 is a flowchart showing an embodiment of the access method in the duplex shared memory device of the present invention. When a fetch instruction (1) is given to the duplex shared memory device from the computer side, the logical block of the duplex shared memory is By reading the memory in the OQl and checking the memory contents (01), the failure information (12) of the memory block corresponding to the accessed address waiting for the previous access is obtained.
+ is obtained. If a failure occurred during the previous access based on this failure information, check to see if the other side of the duplex shared memory device is out of order, and if both the other side is out of order, the process goes to error handling routine (6) and returns to error handling routine (6). If not, activate memory block α4 indicating the normal state,
Next, an error check (3C) is performed, and an error (4C) is detected.
), if there is no 7
If an error has occurred, a failure state signal is written to the memory in the logic pull (15b), and then the error processing routine (6) is executed. Then, as a result of checking the memory in the logical block, if no error has occurred,
Activate the mask side memory block (2), perform an error check (3a), and if no error (4a) has occurred, transfer the 7-etch data to the outside (7), and if an error has occurred, send a failure status signal. is sent to the logical block and written to the memory in this logical block (15a), and the slave side memory block (5) is activated to perform an error check (3b), and if no error occurs, the fetch data is sent. If an error has occurred that cannot be transferred to the outside, a fault status signal is sent to the logic block and written to the memory within this logic block (15b), and the process proceeds to the error handling routine (6). ing.

Next, FIG. 3 is a block diagram showing the configuration of a duplex shared memory device for implementing the access method of the present invention. It is composed of a duplicated master-side memory block (c) and a slave-side memory block (c) connected to the CPU bus, and this logical block (c) is further connected to the CPU bus.
Bus interface section and timing generation section (a)
, a memory bus interface section H connected to the shared memory block, and a memory section (2) for storing fault status signals.
). Note that the master side memory block Q:1 and the slave side memory block C! (
A) has a built-in error check circuit.

In the duplex shared memory device described above, when the power is turned on, the memory contents of the logical block (c) are cleared,
The duplex shared memory device is in a state of waiting for access.
When there is an access for the first time, the contents of the memory in the logical block (c) are cleared and there is no failure, so the mask side memory block 123) is activated.

When an unrecoverable error occurs in this mask-side memory block C (capital), a fault state signal is sent back to the logic block 51, so that this logic block (c) is transferred from the mask-side memory block e3) to a fault state signal. When a signal is received, the memory section (2
When stored in 2, the slave side memory block Ca is activated in In.

When an unrecoverable error occurs in this slave side memory block ea, a failure state signal is returned to the logic block (251).Next, this logic block (25) The system performs the same processing as above and moves to the error handling routine.

The failure state of the memory block can be determined by the above-mentioned procedure.
When an address stored in memory section e2 in a logical block Q and where a failure occurred in the previous access is accessed again, the memory in the logical block is read and the failure occurs before the memory block is started. If the failure is on the mask side, slave side, or its partner, it is determined whether the failure is on the mask side, the slave side, or its partner. If the failure is not in the partner, the memory block in the normal state is activated, and if both the partner is in failure, the error processing routine is executed. Since the access time is shifted, the delay in access time when a failure occurs can be reduced.

〔Effect of the invention〕

As described above, in the duplex shared memory device of the present invention, a memory is provided in the memory device to store the failure status of each shared memory, and access to the shared memory is activated based on this memory, so that when a failure occurs This has the excellent effect of reducing the delay in access time.

In the above-mentioned embodiment, the memory in the logical block is read out when the duplex shared memory device is accessed, but it is also possible to read out the memory from the computer side via the CPU bus. By doing so, a map indicating the failure state of the memory block can be obtained, which has the effect of facilitating maintenance. In addition, if the capacity of the duplex shared memory device is large, the capacity of the memory in the logical block will also be large, so failure conditions can be detected in appropriate address units, for example, in units of the capacity of the storage elements used in the duplex shared memory device. It goes without saying that a similar effect can be obtained by storing the signal.

[Brief Description of the Drawings] Fig. 1 is a flowchart of a conventional access method in a duplex shared memory device, Fig. 2 is a 70-chart of an access method in a duplex shared memory device of the present invention, and Fig. 3 is a flowchart of a conventional access method in a duplex shared memory device of the present invention. FIG. 2 is a four-dimensional diagram illustrating a shared memory device. In the drawing, (20 is a CPU bus interface section and a timing generation section, (21) is a memory bus interface, (2 is a memory section, (c) is a master side memory block, C (a) is a slave side memory block, Q51 is a logic block. Note that the same reference numerals in the figure indicate the same or equivalent parts. Agent Shin Kuzuno - Procedural amendment to the Commissioner of the Japan Patent Office 1, Indication of case Patent Application No. 1986-223286 2
, Name of the invention Duplicated shared memory device 3, Relationship with the case of the person making the amendment Hitoshi Katayama, representative of the patent applicant, Department 4, Agent 5, ``Detailed description of the invention'' column of the specification to be amended. 6. Contents of the amendment 1) "This kind" on page 2, line 8 of the specification is amended to "this kind". Above (2)

Claims (2)

[Claims] (1) Input a fault status signal indicating whether or not there is a fault from each duplexed shared memory block to the logic block and store it in the memory within this logic block,
When the duplex shared memory device is accessed, prior to activation of the shared memory block, the failure status signal of each memory block is read from the memory in the logical block corresponding to the accessed address, and based on this content, the normal status is shared. A duplex shared memory device characterized in that only memory blocks are accessed. (2) Duplicated mask side memory block, slave side memory block, CPU bus interface section,
2. A duplex shared memory device according to claim 1, comprising a timing generator, a memory bus interface, and a logic block comprising a memory section.