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JPS59108322U - frequency modulation circuit - Google Patents

frequency modulation circuit

Info

Publication number
JPS59108322U
JPS59108322U JP139983U JP139983U JPS59108322U JP S59108322 U JPS59108322 U JP S59108322U JP 139983 U JP139983 U JP 139983U JP 139983 U JP139983 U JP 139983U JP S59108322 U JPS59108322 U JP S59108322U
Authority
JP
Japan
Prior art keywords
variable capacitance
capacitance diode
frequency
circuit
oscillation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP139983U
Other languages
Japanese (ja)
Inventor
勝裕 亀田
正彦 浅川
Original Assignee
太陽誘電株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 太陽誘電株式会社 filed Critical 太陽誘電株式会社
Priority to JP139983U priority Critical patent/JPS59108322U/en
Publication of JPS59108322U publication Critical patent/JPS59108322U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の周波数変調回路を示す回路図、第2図は
本考案の周波数変調回路を示す回路図、第3図は第2図
の回路を利用したPLL回路を示すブロック図、第4図
は変形例の変調回路の一部を示す回路図、第5図は変形
例のバーl−シー発振回路を示す回路図である。 1・・・制御電圧入力端子、2・・・信号入力端子、3
・・・直流周波数制御電圧供給回路、4・・・信号供給
回路、E・・・直流周波数制御電圧源、e・・・情報信
号源、VC・・・可変容量ダイオード、R11・・・抵
抗、C□1・・・コンデンサ、Q・・・トランジスタ。
FIG. 1 is a circuit diagram showing a conventional frequency modulation circuit, FIG. 2 is a circuit diagram showing a frequency modulation circuit of the present invention, FIG. 3 is a block diagram showing a PLL circuit using the circuit in FIG. 2, and FIG. The figure is a circuit diagram showing a part of a modulation circuit of a modified example, and FIG. 5 is a circuit diagram showing a Versi oscillation circuit of a modified example. 1... Control voltage input terminal, 2... Signal input terminal, 3
... DC frequency control voltage supply circuit, 4 ... Signal supply circuit, E ... DC frequency control voltage source, e ... Information signal source, VC ... Variable capacitance diode, R11 ... Resistor, C□1...Capacitor, Q...Transistor.

Claims (3)

【実用新案登録請求の範囲】[Scope of utility model registration request] (1)可変容量ダイオードVCの容量値の変化に対応し
て発振周波数が変化する発振回路と、前記発振回路の出
力周波数の中心周波数を決定するために前記可変容量ダ
イオードVCを逆バイアスする方向の直流周波数制御電
圧を前記可変容量ダイオードVCの一端に供給する直流
周波数制御電圧供給回路3と、 前記可変容量ダイオードVCの他端と接地又は共通ライ
ンとの間に接続されたコンデンサC11と、 前記コンデンサC1、に並列に接続された抵抗R11と
、 信号波の電圧変化に対応させて前記可変容量ダイオード
VCの容量を変化させるために前記可変容量ダイオード
VCと前記コンデンサC1□との間に前記信号波を供給
する信号供給回路4と、から成ることを特徴とする周波
数変調回路。
(1) An oscillation circuit whose oscillation frequency changes in response to a change in the capacitance value of a variable capacitance diode VC, and a direction in which the variable capacitance diode VC is reverse biased to determine the center frequency of the output frequency of the oscillation circuit. a DC frequency control voltage supply circuit 3 that supplies a DC frequency control voltage to one end of the variable capacitance diode VC; a capacitor C11 connected between the other end of the variable capacitance diode VC and ground or a common line; A resistor R11 is connected in parallel to C1, and the signal wave is connected between the variable capacitance diode VC and the capacitor C1□ in order to change the capacitance of the variable capacitance diode VC in accordance with the voltage change of the signal wave. A frequency modulation circuit characterized by comprising: a signal supply circuit 4 that supplies a signal.
(2)前記発振回路はコルピッツ型発振回路である  
。 実用新案登録請求の範囲第1項記載の周波数変調回路。
(2) The oscillation circuit is a Colpitts type oscillation circuit.
. A frequency modulation circuit according to claim 1 of the utility model registration claim.
(3)前記発振回路はハートレー型発振回路である実用
新案登録請求の範囲第1項記載の周波数変調回路。
(3) The frequency modulation circuit according to claim 1, wherein the oscillation circuit is a Hartley type oscillation circuit.
JP139983U 1983-01-10 1983-01-10 frequency modulation circuit Pending JPS59108322U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP139983U JPS59108322U (en) 1983-01-10 1983-01-10 frequency modulation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP139983U JPS59108322U (en) 1983-01-10 1983-01-10 frequency modulation circuit

Publications (1)

Publication Number Publication Date
JPS59108322U true JPS59108322U (en) 1984-07-21

Family

ID=30133128

Family Applications (1)

Application Number Title Priority Date Filing Date
JP139983U Pending JPS59108322U (en) 1983-01-10 1983-01-10 frequency modulation circuit

Country Status (1)

Country Link
JP (1) JPS59108322U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516824B2 (en) * 1976-12-31 1980-05-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5516824B2 (en) * 1976-12-31 1980-05-07

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