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JPS5899910U - Muting circuit - Google Patents

Muting circuit

Info

Publication number
JPS5899910U
JPS5899910U JP19162481U JP19162481U JPS5899910U JP S5899910 U JPS5899910 U JP S5899910U JP 19162481 U JP19162481 U JP 19162481U JP 19162481 U JP19162481 U JP 19162481U JP S5899910 U JPS5899910 U JP S5899910U
Authority
JP
Japan
Prior art keywords
muting
differential amplifier
circuit
potential
muting circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19162481U
Other languages
Japanese (ja)
Inventor
芳郎 功力
渡辺 良彦
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP19162481U priority Critical patent/JPS5899910U/en
Publication of JPS5899910U publication Critical patent/JPS5899910U/en
Pending legal-status Critical Current

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  • Amplifiers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のミューティング回路を示す回路図、及び
第2図は本考案によるミューティング回路の一実施例を
示す回路図である。 Q、〜Q、・・・・・・トランジスタ、Q7・・・・・
・スイッチン   ゛グトランジスタ、3・・・・・・
カレントミラー回路、4・・・・・・制御端子。 −一」−
FIG. 1 is a circuit diagram showing a conventional muting circuit, and FIG. 2 is a circuit diagram showing an embodiment of a muting circuit according to the present invention. Q, ~Q,...transistor, Q7...
・Switching transistor, 3...
Current mirror circuit, 4... Control terminal. −1”−

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 差動増幅器を構成する一対のトランジスタのそれぞれと
並列に同一導電形のトランジスタをそれぞれ接続すると
共にそれらのベースを相互接続してなり、前記差動増幅
器の信号入力となるトランジスタのベースの電位と前記
相互接続したベースの電位との間の電位差を切換えてミ
ューティング動作を行わせるようにしたミューティング
回路において、ミューティング信号に応答して、前記差
動増幅器の信号入力となるトランジスタのベースの電位
を略電源電圧まで引上げる回路を備えることを特徴とす
るミューティング回路。
Transistors of the same conductivity type are connected in parallel with each of a pair of transistors constituting a differential amplifier, and their bases are interconnected, and the potential of the base of the transistor serving as the signal input of the differential amplifier and the In a muting circuit that performs a muting operation by switching the potential difference between the potentials of interconnected bases, the potential of the base of the transistor serving as the signal input of the differential amplifier is changed in response to a muting signal. A muting circuit characterized by comprising a circuit that raises the voltage to approximately the power supply voltage.
JP19162481U 1981-12-24 1981-12-24 Muting circuit Pending JPS5899910U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19162481U JPS5899910U (en) 1981-12-24 1981-12-24 Muting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19162481U JPS5899910U (en) 1981-12-24 1981-12-24 Muting circuit

Publications (1)

Publication Number Publication Date
JPS5899910U true JPS5899910U (en) 1983-07-07

Family

ID=30105075

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19162481U Pending JPS5899910U (en) 1981-12-24 1981-12-24 Muting circuit

Country Status (1)

Country Link
JP (1) JPS5899910U (en)

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