JPS5898924A - Minute pattern forming method - Google Patents
Minute pattern forming methodInfo
- Publication number
- JPS5898924A JPS5898924A JP19811481A JP19811481A JPS5898924A JP S5898924 A JPS5898924 A JP S5898924A JP 19811481 A JP19811481 A JP 19811481A JP 19811481 A JP19811481 A JP 19811481A JP S5898924 A JPS5898924 A JP S5898924A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- film
- exposure
- resist
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/26—Processing photosensitive materials; Apparatus therefor
- G03F7/36—Imagewise removal not covered by groups G03F7/30 - G03F7/34, e.g. using gas streams, using plasma
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は微細パターンの形成方法に関するものである。[Detailed description of the invention] The present invention relates to a method for forming fine patterns.
近年の半導体装置には、高密度、低消費電力化が強く要
望されている。このため半導体素子寸法(各素子構成部
材の寸法)は、微細化の方向にある。このような微細寸
法加工には、従来の紫外線露光、クエソトエツチング法
を用いる写真食刻法では困離であり、電子線、X線を用
いる露光法やドライエツチング法が用いられるようにな
っている。しかし、電子線露光やX線露光は、装置力;
高価かつ工程が複雑で時間がかかるという欠点があるた
め、1〜2ミクロン以上の寸法加工には必ずしも十分で
なかった。In recent years, there has been a strong demand for high density and low power consumption for semiconductor devices. For this reason, the dimensions of semiconductor elements (the dimensions of each element component) are trending toward miniaturization. For such micro-dimensional processing, conventional photolithography methods using ultraviolet light exposure and quesothoetching methods are difficult, and exposure methods using electron beams and X-rays and dry etching methods have come to be used. There is. However, electron beam exposure and X-ray exposure require limited equipment power;
Because of the disadvantages of being expensive and requiring complicated and time-consuming processes, it has not always been sufficient for processing dimensions of 1 to 2 microns or more.
本発明は、従来の光露光法による・(ターン形成の寸法
の限界を一層微細にすることを目的としてなされたもの
である。The present invention has been made for the purpose of further reducing the limit of the dimension of turn formation by the conventional light exposure method.
微細パターン形成に用いる感光性膜(以下、ホトレジス
トと総称する)には、ポジ型、ネガ型の両種とも、数多
くの種類が市販されているが、ポジ型ホトレジストのメ
リットは、露光された部分が分解、中和反応しながら現
像液中に溶けこんでイキ、ネガ型ゴム糸ホトレジストの
露光、現像に見られるような、重合、架橋反応によるブ
リッジや膨潤のないことである。そのために微細ノ;タ
ーン形成には、一般にポジ型ホトレジストが多く用いら
れている。There are many types of photosensitive films (hereinafter collectively referred to as photoresists) used for forming fine patterns on the market, both positive and negative types.The advantage of positive photoresists is that the exposed areas There is no bridging or swelling caused by polymerization or cross-linking reactions, as is seen in the exposure and development of negative-type rubber thread photoresists. For this reason, positive photoresists are generally used to form fine turns.
しかし、ポジ型ホトレジストにおいても、従来の光露法
においては、ホトレジスト膜にある・ζり−ンの光潜像
を形成する場合ホトレジスト膜厚にわたって十分である
量の露光がおこなわれていた。However, even in the case of positive-type photoresists, in the conventional light exposure method, a sufficient amount of exposure is performed over the thickness of the photoresist film when forming a latent optical image of ζ-line in the photoresist film.
このような露光では、ホトレジスト膜における光の回折
、散乱やホトレジストと基板界面での光の反射などの現
象により、パターン輪郭の劣化が完全に避けられない。In such exposure, deterioration of the pattern contour cannot be completely avoided due to phenomena such as diffraction and scattering of light in the photoresist film and reflection of light at the interface between the photoresist and the substrate.
本発明は、従来の露光、現像にドライエツチングを附加
した新規なホトレジスト微細パターン形成法で、さらに
詳しく述べると、露光、現像をホトレジスト膜の所定深
さの層にとどめ、以降をドライエツチングすることであ
る。The present invention is a novel photoresist fine pattern forming method that adds dry etching to conventional exposure and development. More specifically, the method involves limiting exposure and development to a predetermined depth layer of the photoresist film, and then dry etching the remaining layers. It is.
以下、本発明の実施例を図面を用いて説明する。Embodiments of the present invention will be described below with reference to the drawings.
第1図の1は例えば半導体基板またはフォトマスク用ガ
ラス基板である。本実施例は、半導体シリコン基板10
0flLfllφ を用いた。その上は、パターン形成
用被膜2 (8102、ム!、クロム、ポリシリコン、
窒化膜など、通常の半導体装置あるいは同装置の製造工
程に用いる被膜)でおおわれている。なお、本実施例で
は5102を用いた。さらにプ
ポジ型ホトレジスト3を衆知のスビ/本−塗布法によす
1.6ミクロン〜2.6ミクロンの厚さで塗布する。Reference numeral 1 in FIG. 1 is, for example, a semiconductor substrate or a glass substrate for a photomask. In this embodiment, a semiconductor silicon substrate 10
0flLfllφ was used. On top of that, pattern forming film 2 (8102, M!, chromium, polysilicon,
It is covered with a film such as a nitride film used in normal semiconductor devices or the manufacturing process of such devices. Note that 5102 was used in this example. Further, a positive type photoresist 3 is applied to a thickness of 1.6 to 2.6 microns by a well-known strip/line coating method.
次に第2図のごとくフォトマスクを用い、露光。Next, expose using a photomask as shown in Figure 2.
現像を行う。このときの露光、現像の処理工程では、被
膜界面4まで完全に現像を行い像形成することをせず、
露光時間を従来のに〜晃とし、レジスト表面下1.0ミ
クロン程度を感光せしめる。次に従来と同一時間で現像
液を用いてホトレジストを第2図のごとく溶解し除去部
6を形成しその直下のレジスト6を0.6ミクロン〜1
.6ミクロン程度残す。なお、レジスト膜厚は、1.0
ミクロン以上が望ましい。Perform development. In the exposure and development processing steps at this time, the film is not completely developed up to the film interface 4 and no image is formed.
The exposure time is set to the conventional range, and about 1.0 micron below the surface of the resist is exposed. Next, in the same time as conventional methods, the photoresist is dissolved using a developer as shown in FIG.
.. Leave about 6 microns. Note that the resist film thickness is 1.0
A diameter of micron or more is desirable.
次に第3図に示すように、基板バイアスプラズマエツチ
ング装置を用い、上述の直下のレジスト6を被膜2の界
面までエツチングして除去する。Next, as shown in FIG. 3, using a substrate bias plasma etching apparatus, the resist 6 directly below the above-mentioned resist 6 is etched to the interface of the coating 2 and removed.
このとき、レジスト開口部7の側壁がほぼ垂直になるよ
うに形成する。At this time, the side walls of the resist opening 7 are formed to be substantially vertical.
次に、残ったレジスト3をマスクとして第4図に示すよ
うに、異方性ドライエツチング装置を用いて、レジスト
と下地被膜の選択性良好なガスを用い、下地被膜2をエ
ツチングする。Next, using the remaining resist 3 as a mask, as shown in FIG. 4, the base film 2 is etched using an anisotropic dry etching apparatus using a gas with good selectivity between the resist and the base film.
第6図は、下地被膜2のエツチングのときk、エツチン
グマスクとしたホトレジストを除去した状態である。FIG. 6 shows a state in which the photoresist used as an etching mask during etching of the base film 2 has been removed.
以上に示した本発明の方法では、ホトレジスト膜の感光
領域を表面層に限定するため、光の散乱。In the method of the present invention described above, since the photosensitive area of the photoresist film is limited to the surface layer, light scattering occurs.
回折あるいは反射をできるだけ防ぐので、光像の忠実度
、コントラストが向上する。またその後、ホトレジスト
を、続いて被膜をドライエツチング装置を用いてエツチ
ングすれば、従来の輪〜確程度の微細パターン形成が容
易にできる。なお、本発明の方法は、可視光露光にとど
まらず、電子線露光などにも用いられ、ることはいうま
でもないiまだ、本発明の方法を紫外線露光に用いれば
、高価な装置を要せず、2ミクロン以下の微細パターン
形成ができ、高密度、高集積度あるいは低消潰電力用の
半導体装置製造のためのホトマスク及d製造工程に応用
して大きな効果を発揮できる。Since diffraction or reflection is prevented as much as possible, the fidelity and contrast of the optical image are improved. Furthermore, if the photoresist and then the film are etched using a dry etching device, it is possible to easily form a fine pattern of the conventional circular to precise size. It goes without saying that the method of the present invention can be used not only for visible light exposure, but also for electron beam exposure, etc. However, if the method of the present invention is used for ultraviolet exposure, it will not require expensive equipment. It is possible to form a fine pattern of 2 microns or less without using the method, and it can be applied to photomasks and d manufacturing processes for manufacturing semiconductor devices with high density, high degree of integration, or low dissipation power, and can exhibit great effects.
第1図〜第6図は本発明の一実施例の製造工程を示す断
面図である。
1・・・・・・半導体基板、2・・・・・・半導体被膜
、3・・・・・・ポジ型ホトレジスト、4・・・・・・
被膜界面。
代理人の氏名 弁理士 中 尾 歓 男 ほか1名第1
図
131!! □
第4図
第5図1 to 6 are cross-sectional views showing the manufacturing process of an embodiment of the present invention. 1...Semiconductor substrate, 2...Semiconductor film, 3...Positive photoresist, 4...
Film interface. Name of agent: Patent attorney Ken Nakao and 1 other person 1st
Figure 131! ! □ Figure 4 Figure 5
Claims (1)
さに塗布する工程と、前記ホトレジスト膜の表面から前
記所定の厚さ以下の前記ホトレジスト部分を露光、現像
してパターン形成する工程と、異方性ドライエツチング
を用いて、前記ホトレジスト膜をエツチングする工程と
を備えたことを特徴とする微細パターン形成方法。a step of applying a photoresist film to a predetermined thickness on a predetermined film provided on a substrate surface; a step of exposing and developing a portion of the photoresist film from the surface of the photoresist film to a thickness below the predetermined thickness to form a pattern; A method for forming a fine pattern, comprising the step of etching the photoresist film using anisotropic dry etching.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19811481A JPS5898924A (en) | 1981-12-08 | 1981-12-08 | Minute pattern forming method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19811481A JPS5898924A (en) | 1981-12-08 | 1981-12-08 | Minute pattern forming method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5898924A true JPS5898924A (en) | 1983-06-13 |
JPS6224941B2 JPS6224941B2 (en) | 1987-05-30 |
Family
ID=16385697
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19811481A Granted JPS5898924A (en) | 1981-12-08 | 1981-12-08 | Minute pattern forming method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5898924A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0158357A2 (en) * | 1984-04-13 | 1985-10-16 | Nippon Telegraph And Telephone Corporation | Method of forming resist micropattern |
JPH01105536A (en) * | 1987-10-19 | 1989-04-24 | Sanyo Electric Co Ltd | Photoresist pattern forming method |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5228267A (en) * | 1975-08-28 | 1977-03-03 | Nippon Telegr & Teleph Corp <Ntt> | Minute processing |
JPS5633827A (en) * | 1979-08-29 | 1981-04-04 | Seiko Epson Corp | Photo etching method including surface treatment of substrate |
-
1981
- 1981-12-08 JP JP19811481A patent/JPS5898924A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5228267A (en) * | 1975-08-28 | 1977-03-03 | Nippon Telegr & Teleph Corp <Ntt> | Minute processing |
JPS5633827A (en) * | 1979-08-29 | 1981-04-04 | Seiko Epson Corp | Photo etching method including surface treatment of substrate |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0158357A2 (en) * | 1984-04-13 | 1985-10-16 | Nippon Telegraph And Telephone Corporation | Method of forming resist micropattern |
JPH01105536A (en) * | 1987-10-19 | 1989-04-24 | Sanyo Electric Co Ltd | Photoresist pattern forming method |
Also Published As
Publication number | Publication date |
---|---|
JPS6224941B2 (en) | 1987-05-30 |
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