JPS5897758A - Controlling system of shared memory - Google Patents

Abstract

PURPOSE:To elable an automatic access control of a shared memory and to increase the using efficiency of the shared memory, by providing a master/slave type memory sharing part to each processor, and at the same time, arranging an interruption control register in a shared memory. CONSTITUTION:Both an interruption request register and an interruption reception register are provided to a specific address in a shared memory 102. Thus a parallel interruption control is carried out between the slave processors 103. At the same time, the access of each memory 1 of the memory 102 is automatically controlled through the access request reception parts 21 and 23 and an access priority circuit 24. Thus the simultaneous data transfer control is performed for the memory 102. The interruption reception register formed with a master processor 101 has an interruption masking function and an optional bit selecting structure along with the interruption request register. Therefore, a shared common memory is available for the processor 101, and at the same time plural common memories are available for the processor 103 respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a shared memory control method in a multiprocessor system.

In general, there are two main ways to configure system equipment that is controlled by a microprocessor.

One is a configuration method based on the idea of centralizing the hardware and software functions that the system should have as much as possible, and the other is a configuration method based on the idea of thoroughly dividing and distributing the functions. be.

Many of the former systems are designed based on the principle of centralization of functions with the aim of optimizing price/performance, but the system has poor scalability when changing services or introducing new software. Recent developments in LSI technology and soft programming application technology have made it clear that centralization of functions is not necessarily the best way to achieve overall system economy. Furthermore, when the target system equipment is controlling a plurality of terminals, it has drawbacks such as difficulty in timing control.

In contrast, the purpose of configuring the latter multiprocessor system is to improve the performance of the system and increase the flexibility of functions compared to the former. If a microprocessor is used for this, the processor itself is inexpensive and can be configured with several LSI chips in combination with a peripheral control IC, resulting in increased reliability compared to conventional ones that use a large number of logic elements. It has major advantages such as being relatively easy to apply compared to traditional programs that require a lot of time and money to be flexible.

In this case, especially in system equipment where multiple VOs etc. are controlled by multiple microprocessors dedicated to each control,
In controlling task execution, data transfer, etc. between these processors, a master processor is required to manage the entire system. The first problem in such a multiprocessor system is the communication method between each processor. Conventionally, the communication control means in this case was to use mutual interrupts to store data in the dedicated memory of each processor and execute the task. , from the master processor to each control program, processor 1N question"';!r 58
- 97758 (2) There were difficulties in processing both software and hardware in terms of instantaneous interrupt control to Tsusa.

Furthermore, as a data transfer method for such a multiprocessor system, a method has been proposed in which a master/slave type shared memory is provided within the multiprocessor. However, in the conventional shared memory method, when a master processor or slave processor accesses shared memory,
Only one access request can be processed at a time, so if processor access requests overlap, 1
It was necessary to accept requests from only one processor and keep the other processors waiting. Therefore, when a processor accesses shared memory, it sets a flag in the path controller indicating that the target processor will use it, prohibits other processors from using it, and resets the flag when the use is finished. Ta.

In such a system, a control unit such as a bus controller control circuit is required outside the shared memory, which results in usage management using software, resulting in a reduction in the actual usage efficiency of the shared memory.

The present invention provides a communication system between multiprocessors in which a master/slave type memory sharing unit is provided in each processor, and an interrupt control register arranged in the shared memory and automatic access control of the master/slave processors are provided. The object of the present invention is to provide a new data transfer control method that does not have the above drawbacks and can automatically control access to a shared memory.

An embodiment of the present invention will be described in detail below with reference to the drawings.
FIG. 1 shows an example of a multiprocessor system. In this configuration, a shared memory 17102 is arranged in the master processor 101 (for example, L-16), and a plurality of slave processors 103 (for example, 6802) share this memory space.
Each memory area is divided and used. Therefore, when viewed from the master processor 101 side, there is one shared memory, and when viewed from the slave processor 103 side, there is a plurality of shared memories. For example, if there are 3 slave processors
If there are, write the start address of each of the shared memory 102! As '2000', bottom address X'271F
Each memory has a fixed value of 2 bytes in L. On the other hand, the master processor 101 has a shared memory 1o2
Assuming the start address of X'8000', x'5ooo
'~X '87 F F
Allocate bytes up to 2 to slave processor Arashi 2, and allocate bytes 2 to slave processor Arashi 3 and 4 from X1 000' to x' 7FF on a byte boundary.

This situation is shown in FIG. 4, and details will be described later. This shared memory configuration will be explained below, but this master processor,
It goes without saying that the address spaces of the slave processors and the slave processors can have any configuration in design. As in the embodiment, when the master processor is L-1e and the slave processor is 6802, the shared memory interface is as shown in FIG.

Hereinafter, in this embodiment, L-16 will be used as the master processor.
A case will be explained in which a 6802 is used as a slave processor. Although the L-16 system has a 16-bit configuration, it does not use the upper 8 bits and uses only the lower s bits. In the following explanation, the master processor will simply be referred to as L-
16, the slave processor is simply expressed as 6802.

In FIG. 2, 1 is a shared memory, and in this embodiment, 2 is a byte RAM (random access memory). 1
8 is an interface unit on the slave processor 6802 side with respect to the shared memory, and 19 is an interface unit for the master processor L-
This is the interface section on the 16-system side. 2 and 6 indicate bidirectional data buffers of the data line 14v1o of each processor. 3 and 6 are address lines 15 and 11 as well.
through the address selector 8 in the address buffer of
Each is connected to the shared memory 1. Reference numeral 9 is a control circuit that connects the timing control line 16 of 6802 and the control balance line 4. Alternatively, the timing control line 12 from the L-16 system and the control buffer 7 are switched to control data writing or data reading from both processors to the shared memory. Reference numeral 13 and 17 are interrupt lines connected to an interrupt control register arranged in the shared memory, which is a feature of the present invention. This will be discussed in detail later.

FIG. 3 shows details of the shared memory automatic access control section in the present invention, including the control circuit sy control buffer 4.7 and timing control line 16 of FIG.
It is an explanatory diagram of the operation of the y12 section.

The same parts as in FIG. 2 are given the same reference numerals. In the figure, 2
2 is a shared memory access request line from 6802, 20 is a shared memory access request line from L-16, and 23.
21 is an access request reception unit of each processor;
4 is an access priority control circuit; 28 and 27 are control lines for switching between the bidirectional data buffers 2 and 5 of each processor; and 29 is a control line for writing and reading from the shared memory 1. Also, 1s' and 11' are the address lines of 6802 and L-16, respectively, and are connected to the address switching side NM30.
Then, switch the address switching circuit 8 to 6802°L-16.
Switch the address line to and from the system.

In the operation of this control unit, priority is given to the processor that issued an access request to the shared memory 1 first, and the other processors receive a signal 26. which delays the timing of the access request. or 2
5 is output from the access priority circuit 24 composed of a flip-flop or the like, and the use of the shared memory 1 is made to wait. Furthermore, if one processor is already accessing the shared memory 1, the access delay signal 26. Or output 25. This control is automatically controlled by a hardware circuit section consisting of the access request reception section 21, 23 and the access priority control circuit 24, and as in the conventional example, it is controlled by a software program such as setting a flag to an external bus controller. It does not need to be managed at all and has the feature of increasing the efficiency of shared memory access.

Next, the interrupt control method, which is a feature of the present invention, will be explained in detail. As shown in FIG.
Dedicated memory area 31 of 2046 bytes each for 02
will be established. Paying attention to one of them, if we take its first address 37 as X'2000' and multiply it by 1 degree, then among the two lowest addresses, ! Address '271E' is the interrupt request register 32 (hereinafter referred to as IRQR),! '27
7 Enter the F/address as the interrupt reception register 33 (hereinafter referred to as I RVR).
). On the other hand, when viewed from the L-16 side, if the starting address of the shared memory is x'aooo', then similarly, of the lowest two addresses of the dedicated memory area 34 in the shared memory, ! It has an interrupt reception register ss (IRVR) at address '87FK' and an interrupt request register 3e (IRQR) at address X'87FF'.

Although FIG. 4 only shows one corresponding 6802.1 among these, if there are three 6802s, the IRVR will be !'97FK' and z/-mu7F.
IC', IRQR! '97FF/ and X'mu 7F
There will be an interrupt control register corresponding to each 6802 in F/. However, considering that the addresses of the interrupt request register and interrupt acceptance register of the L-16 system are upper 46-bit addresses, this interrupt register can be represented by one address. That is, I on the 68o2 side
RQR and IRVR are 1 b of the 8 bits of the corresponding address
It uses only the data of it, but the IRQ on the L-16A side
R has an 8-bit configuration and is allocated to each 6802 interrupt line as described above.

Furthermore, only IRVR has a 16-bit configuration, and the upper 8b
It is used as a function to mask interrupts from each 68o2, and the lower 8 bits are used as interrupt reception bits from each 6802. This is shown in FIG.

(1) Interrupt from L-16m to 68o2 (a) IRQH
As shown in Figure 4, the 68 assigned IRQR32
When the corresponding bit of the o2 processor is set to L/117 and a write operation is performed to IRQH, flip-flop 4
o is set, and an interrupt occurs at 6802 via interrupt line 17.

(b) IRVR operation 68o2 performs interrupt processing, and when the IRVR 33 is echo-reset, the flip-flop 4o is reset and at the same time the corresponding bit is reset to O'' and the interrupt is canceled.

(2) Interrupt from 6802 to L-16m (a) IRQH
Operation When a write operation is performed to IRQR32, the result shown in FIG.
If the mask register corresponding to the upper s bit of IRVR35 is 71", the flip-flop 39 is set and an interrupt is generated to L-16A through the interrupt line 13. However, if the corresponding mask register of IRVRss is □
l/, the interrupt is held and the mask register is set to I
If set to I I L/, an interrupt will be placed on the L-16 system at that point.

(b) Operation of IRVR When IRVRss is echo-reset, the flip-flop 39 is reset and at the same time the corresponding bit is reset to "o" and the interrupt is canceled.

FIG. 6 shows an example of a concrete circuit for interrupt control. This will be explained below with reference to the timing diagram shown in FIG.

(1) When interrupting from L-16 to 68o2, (
(FIG. 7 (IL)) First, the interrupt request bit 65 of IRQH is read and it is checked whether or not the interrupt processing has been completed on the 6802 side. If the processing has already been completed 13, the Q output of the flip-flop 43 is o'', so if you set the necessary bit of IRQH to 1'' again and perform a write operation 51 to IRQH, the flip-flop The Q output of 43 is inverted and becomes o'', which is the target 680
An interrupt occurs at 2. IRVR signal 53 on the 6802 side
If the operation of reading and writing (echo reset 54) is performed, the output of the flip-flop 43 is inverted and the interrupt is reset.

? ) When issuing an interrupt to L-16 from the 6802 side (Fig. 7 (2L)), similarly, interrupt request bit 5 of IRQH
6 is read and it is checked whether the interrupt processing has been completed on the L-16A side. If the processing has already been completed, the Q output of the flip-flop 42 has been reset to 0", so
If the write operation 57 is performed on IRQH again, the Q output of the flip-flop 42 is set to 11'', and the output becomes L-16.
An interrupt occurs in the system. On the L-16 person side, the operation of reading and writing the IRVR signal 68 (echo reset 69)
If this is done, the Q output of the flip-flop 42 will be inverted and the interrupt will be reset.

Here, 41 is an interrupt mask register of IRVR, which is normally assigned to a specific bit of the data line on the L-16A side. Using a jumper line or the like for this bit selection is convenient for various settings.

Furthermore, as for how to use shared memory, if the memory is configured with 2 bytes, divide it into 1 bytes, and transfer data from L-16 people to 68o2 bytes on the top 1. Transfer bytes to 68o2 on the bottom 1. to L-16A, and the start address of the shared memory is set to the command register (ICMR) 37. as shown in FIG. If the first address of the byte in the second half 1 is used as the status register (ISTR) 38, for example, under software control, the ICMR
It is convenient that the L-16 system can manage the entire system by setting data in the 15TR37, activating a task by interrupting each 6802, and grasping the data in the 15TR38 after completion.

Also, it may be necessary for L-16A to interrupt each 6802 at the same time. At this time, as mentioned above, the corresponding bit of the interrupt request register (I RQ R) is
Set I L/ and press IRQR's X/-
All you have to do is perform a write operation. That is, the second upper address of L-16 address switching terminals (not shown);
When using the third interrupt register, by leaving address selection free, IRVR and IRQR can be set to
They can be grouped into one location each at address Mu7FK1 and address X/Mu7FF'. In other words, zLm7 F E',
Even if you access IRVR and IRQR at address x'mu7FF', x'87FIC', x'87FF', x'9
77'.

Address X'97F F' can also be accessed at the same time. Therefore, by setting L/2/l to the bit position of IRQH corresponding to the required 6802 and issuing an interrupt, it is possible to control parallel interrupts, and it is also possible to improve the immediacy of processing.

As described above, the interrupt register is used to control the timing of information transmission, and its operation is completely different from the conventional use of the shared memory usage right register.

Therefore, the above-mentioned automatic control effect of memory access is also added, and the efficiency of use of the shared memory is greatly increased.

In this embodiment, the master processor is L-16.

Although the case where the 6802 is used as the slave processor will be described, it goes without saying that this combination can be applied to any other microprocessor.

Furthermore, although the interrupt control register is placed at the bottom of the shared memory, it goes without saying that it may be placed at any desired location.

In a master/slave type multiprocessor as in the present invention, by configuring a shared memory having the above-mentioned interrupt control method, the following features can be obtained.

(1) Since the master processor enables parallel interrupt control for each slave processor, it is possible to improve the immediacy of multiple processing and to achieve higher efficiency and faster data transfer.

(2) 177, due to the release of the master processor bus.

Data transfer efficiency of the entire system can be improved.

(3) The software of the slave processor can be modularized with independent raw functions, and the software implementation including the master processor can be reduced.

(4) This control method is most suitable for mechanism control systems with multiple functions, and improves the immediacy of processing by clearly allocating tasks to each slave processor, reducing the burden on hardware circuits and reducing software debugging time. It becomes possible to achieve a significant reduction in

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of the configuration of a multiprocessor system used in the shared memory 'JQ control method according to the present invention, FIG. 2 is a block diagram showing the circuit configuration of the shared memory section of FIG. 1, and FIG. The figure is a detailed survey of the main part of Figure 2, Figures 4 and 5 are explanatory diagrams of the operation of the interrupt control system according to the present invention, and Figure 6 is a configuration example of the interrupt control circuit used in the present invention. The wiring diagrams shown in FIGS. 7(!L) and (b) are timing diagrams for explaining the operation of the circuit in FIG. 6. 101... Master processor, 102...
・Share memo! J, 103... Slave processor, 1. Shared memory 2, 6... Data buffer, 3, 6... Address buffer, 4.
, 7... Control buffer, 8...
・Address selector, 9... Control circuit, 18,
19...Interface, 21゜23...
. . . Access reception unit, 24 . . . Access priority control circuit, 32, 36 . . . Interrupt request register,
33.35...Interrupt reception register, 39,40
······flip flop. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Fig. 1 θ2 /θ3 Fig. 2 Fig. 3 626 Fig. 4
/(Address Jffi between b 1-/lA-+〆θρ2 fishing

Claims (2)

[Claims] (1) An interrupt request register and an interrupt reception register are provided at specific addresses in the shared memory to perform parallel interrupt control between each processor, and access to the shared memory is controlled by the access request reception unit and the access priority circuit. automatic control,
A shared memory control method characterized by controlling simultaneous data transfer of the shared memory. (2)) The interrupt reception register configured by the master processor has an interrupt masking function, and together with the interrupt request register, each has an arbitrary bit selection structure. Shared memory control method.