JPS5893268A - Photocoupling integrated circuit - Google Patents
Photocoupling integrated circuitInfo
- Publication number
- JPS5893268A JPS5893268A JP56190627A JP19062781A JPS5893268A JP S5893268 A JPS5893268 A JP S5893268A JP 56190627 A JP56190627 A JP 56190627A JP 19062781 A JP19062781 A JP 19062781A JP S5893268 A JPS5893268 A JP S5893268A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- integrated circuit
- light
- photocoupling
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 39
- 230000008054 signal transmission Effects 0.000 claims abstract description 5
- 230000008878 coupling Effects 0.000 claims description 6
- 238000010168 coupling process Methods 0.000 claims description 6
- 238000005859 coupling reaction Methods 0.000 claims description 6
- 230000003287 optical effect Effects 0.000 claims description 4
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 239000000758 substrate Substances 0.000 abstract description 5
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 230000010354 integration Effects 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/12—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof structurally associated with, e.g. formed in or on a common substrate with, one or more electric light sources, e.g. electroluminescent light sources, and electrically or optically coupled thereto
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photo Coupler, Interrupter, Optical-To-Optical Conversion Devices (AREA)
Abstract
Description
【発明の詳細な説明】
発明の属する技術分野
本発明は、半導体層と絶縁層の層状構造よりなる光結合
集積回路に関する。TECHNICAL FIELD The present invention relates to an optically coupled integrated circuit having a layered structure of a semiconductor layer and an insulating layer.
従来技術とその問題点
半導体１−と絶縁層の層状構造による半導体の集積は、
従来の平面的幾何学的寸法の縮小による集積度をはるか
に上廻り、その集積度を制限する編のは原理的には存在
しないが、現実的にはいくつかの制限要因がある。その
うちのひとつに半導体集積素子に対する信号入出力端子
がある。集積度が向上し半導体集積素子が高度化すると
、例えばメモリ各１が大になるとその続出書き込み制御
用の信号入出力数が増え、またプロセッサーにおいてそ
の機能が高度化すれば当然のことながら同様に信号の入
出力数も増加する。この信号入出力を行う信号入出力端
子は通常、半導体集積素子の表面に設けられた金属薄膜
パターンであり、これに金属細線を機械的操作で圧着溶
接するため、その二次的平面寸法は半導体系子にくらべ
てかなり大きいものにならざるを得ない。またその端子
から金属細線を接続引っばり出すため半導体集積素子表
面上でのその出力端子の配置も全面にではなくその周辺
に限られる。具体的には、出力端子の標準的な大きさは
１００ミクロン角程度で、これを１００ミクロ７間隔で
並べれば、半導体集積素子の周辺長１ ｗｉｔあたりた
かだか１０個程度の出力端子しか配置できない。Conventional technology and its problems The integration of semiconductors using a layered structure of a semiconductor 1- and an insulating layer is
The degree of integration far exceeds the degree of integration achieved by reducing the conventional planar geometric dimensions, and although in principle there is no limit to the degree of integration, in reality there are several limiting factors. One of them is a signal input/output terminal for the semiconductor integrated device. As the degree of integration improves and semiconductor integrated devices become more sophisticated, for example, as each memory becomes larger, the number of signal inputs and outputs for continuous write control will increase, and as the functions of processors become more sophisticated, the same will naturally occur. The number of signal inputs and outputs also increases. The signal input/output terminal that performs this signal input/output is usually a metal thin film pattern provided on the surface of the semiconductor integrated device, and because thin metal wires are mechanically crimped and welded to this, the secondary plane dimensions of the semiconductor integrated device are It has to be quite large compared to its descendants. Furthermore, since the thin metal wires are connected and pulled out from the terminals, the arrangement of the output terminals on the surface of the semiconductor integrated device is limited to the periphery rather than the entire surface. Specifically, the standard size of the output terminals is about 100 microns square, and if these are arranged at intervals of 100 microns, only about 10 output terminals can be arranged per 1 wit of the peripheral length of the semiconductor integrated device.
発明の目的
本発明は、半導体層と絶縁層の層状構造よりなる半導体
集積素子に対する信号入出力数の制約を大巾に取除き、
かつ信号入出力数の大きい半導体集積素子相互の結合を
容易にする光結合集積回路を提供することを目的とする
。Purpose of the Invention The present invention largely removes restrictions on the number of signal inputs and outputs for a semiconductor integrated device having a layered structure of semiconductor layers and insulating layers.
Another object of the present invention is to provide an optically coupled integrated circuit that facilitates mutual coupling of semiconductor integrated devices having a large number of signal inputs and outputs.
発明の概要
本発明は、半導体集積素子の信号入力に受光素子をまた
信号の出力には発光素子をもって行ないかつそれらを半
導体集積相互を光結合し得るように配置することを特徴
とする。SUMMARY OF THE INVENTION The present invention is characterized in that a light receiving element is used for signal input of a semiconductor integrated device, and a light emitting element is used for signal output, and these are arranged so that the semiconductor integrated devices can be optically coupled to each other.
発明の効果
本発明による入出力端子数の増加は主に発光素子の大き
さで決まり半導体中の発光の源である少数キャリヤの性
質からその最小値は５〜１０ミクロンでそれ故出力端子
としては１００個前後が可能となり、入出力端子金せて
従来の１０〜２０倍の出力端子数が可能となる。また半
導体集積素子相互を光結合することが可能なためこれら
を実装する装置が小型化されると共に半導体集積素子相
互の結合に起因する信号の遅れがなくなり、これらを実
装した装置の動作速度向上も計られる。Effects of the Invention The increase in the number of input/output terminals according to the present invention is mainly determined by the size of the light emitting element, and due to the nature of minority carriers, which are the source of light emission in semiconductors, the minimum value is 5 to 10 microns, and therefore, as an output terminal. The number of output terminals can be around 100, and the number of output terminals can be increased by 10 to 20 times compared to the conventional method. In addition, since it is possible to optically couple semiconductor integrated elements to each other, the equipment that mounts them can be miniaturized, and signal delays caused by mutual coupling between semiconductor integrated elements can be eliminated, increasing the operating speed of equipment that implements these elements. It is measured.
発明の実施例 本発明を実施例を用いて説明する。Examples of the invention The present invention will be explained using examples.
第１図ａ−ｃは本発明による光結合集積回路の製造過程
の断面図である。ｉ１図ａで半導体基板１例えばシリコ
ン基板に電気回路を設けた後絶縁膜２例えば酸化シリ：
コンを堆積させ、さらに半導体層３例えばシリコン層を
堆積結晶化させてこの層にも電気回路を設ける。この際
、絶縁層２は、基板１に設けられた電気回路と半導体層
３に設けられた電気回路との信号伝達経路を含んでいる
。1a-c are cross-sectional views of the manufacturing process of an optically coupled integrated circuit according to the present invention. i1 In Figure a, after an electric circuit is provided on a semiconductor substrate 1, e.g. a silicon substrate, an insulating film 2, e.g. silicon oxide:
A semiconductor layer 3, for example a silicon layer, is deposited and crystallized, and an electric circuit is provided in this layer as well. At this time, the insulating layer 2 includes a signal transmission path between the electric circuit provided on the substrate 1 and the electric circuit provided on the semiconductor layer 3.
次に絶縁層４、半導体層５を堆積した後半導体層５の領
域５′と５Ｎを残して他の部分をエツチング除去し、第
１図すのようにこの除去した部分に、他の半導体層７例
えば燐化ガリウムと絶縁層８例えば酸化シリコンを埋込
むように堆積させる。この場合も絶縁層４には半導体層
３に設けられた電気回路と半導体層５の領域５′と５”
および他の半導体層７とを結ぶ信号伝達経路を含む。こ
の後、領域５′には電気回路を５”には受光素子を、ま
た半導体層７には発光素子を形成した後絶縁膜と半導体
層の堆積ならびに半導体層への電気回路の形成をくり返
し゛電気回路を５層積層する。この時、半導体層５より
上層に設けられる電気回路は領域５′の部分より外方に
拡がらないように配置する０この後半導体層５より上層
の積１一部分の内９をエツチング除去し、先に形成させ
た発光素子と受光素子を露出させる。なお半導体層５で
は第１図Ｃに示すように領域５′の端から発行素子７ま
での距離１０と半導体集積素子の端から受光素子５“ま
での距離１１が等しいようにする。Next, after depositing the insulating layer 4 and the semiconductor layer 5, the other parts of the semiconductor layer 5 are removed by etching, leaving the regions 5' and 5N, and as shown in FIG. 7 For example, gallium phosphide and an insulating layer 8 such as silicon oxide are deposited in a buried manner. In this case as well, the insulating layer 4 includes an electric circuit provided in the semiconductor layer 3 and regions 5' and 5'' of the semiconductor layer 5.
and a signal transmission path connecting the semiconductor layer 7 and other semiconductor layers 7. After that, an electric circuit is formed in the region 5', a light receiving element is formed in the area 5'', and a light emitting element is formed in the semiconductor layer 7. After that, the deposition of the insulating film and the semiconductor layer and the formation of the electric circuit on the semiconductor layer are repeated. Five layers of electrical circuits are stacked. At this time, the electrical circuits provided in the layer above the semiconductor layer 5 are arranged so as not to extend outward beyond the region 5'. Part 9 of the area is removed by etching to expose the previously formed light emitting element and light receiving element.In addition, in the semiconductor layer 5, as shown in FIG. The distance 11 from the edge of the semiconductor integrated device to the light receiving element 5'' is made equal.
第２図は完成した光結合集積回路の斜視図である。この
図の奥行き方向に加ミクロン間隔の発光・受光素子のア
レー１０ 、１１を形成し、奥行きｌ ｔｐｒｔｐ、あ
たり素子の両側を入れて１００個の入力および出力端子
が可能となる。FIG. 2 is a perspective view of the completed optical coupling integrated circuit. Arrays 10 and 11 of light-emitting and light-receiving elements are formed at micron intervals in the depth direction of this figure, and 100 input and output terminals are possible by including both sides of the elements per depth l tprtp.
発明の他の実施例
実施例では、発光・受光素子が積層構造の最上層より下
の層のかつ素子周辺の二辺にのみ存在する例について述
べたが、発光・受光素子が積層構造の最上層にあっても
、また周辺の他の辺に配置されていても同様の効果が得
られるのは云うまでもない。Other Embodiments of the Invention In the embodiment, an example was described in which the light-emitting/light-receiving element exists only in the layer below the top layer of the laminated structure and on two sides around the element. Needless to say, the same effect can be obtained even if it is placed on the upper layer or on other sides of the periphery.
第１図（ａ）〜（Ｃ）は本発明の光結合集積回路の製造
工程断面図、第２図は光結合集積回路の一例の斜視図、
第３図は光結合集積回路の多数個の光結合状態を示す図
である。
１．３．５・・・半導体層、 ２，４．８・・・絶縁層
、７・・・発光素子、 ５” 受光素子。1(a) to (C) are cross-sectional views of the manufacturing process of the optically coupled integrated circuit of the present invention, FIG. 2 is a perspective view of an example of the optically coupled integrated circuit,
FIG. 3 is a diagram showing multiple optical coupling states of the optical coupling integrated circuit. 1.3.5...Semiconductor layer, 2,4.8...Insulating layer, 7...Light emitting element, 5" Light receiving element.
Claims (4)
層にはその内部もしくは表面に電気回路素子を含み、絶
縁層には半導体層間の信号伝達経路を含む半導体集積回
路において、回路素子の一部に発光素子もしくは受光素
子もしくは両者を含み、外界との信号の送受を光をもっ
て行うようにしたことを特徴とする光結合集積回路。(1) In a semiconductor integrated circuit, which has a layered structure of a semiconductor layer and an insulating layer, the semiconductor layer includes an electric circuit element inside or on its surface, and the insulating layer includes a signal transmission path between the semiconductor layers. 1. An optically coupled integrated circuit that includes a light emitting element, a light receiving element, or both in part, and transmits and receives signals to and from the outside world using light.
に形成されることを特徴とする特許の範囲第１項記載の
光結合集積回路っ(2) The optically coupled integrated circuit described in item 1 of the scope of the patent, characterized in that the light emitting element and the light receiving element are formed on the top of a stack of semiconductor layers.
数連に形成し、多数個のチップを光結合しうるようにし
たことを特徴とする前記特許請求の範囲第１項記載の光
結合集積回路。(3) The optical coupling integrated circuit according to claim 1, characterized in that the light emitting element and the light receiving element are formed in a plurality of series on the integrated circuit chip body so that a large number of chips can be optically coupled. circuit.
最上層よシも低い層と 一→→→８←ヲ←．シ
たことを特徴とする前記特許請求の範囲第９１記載の光
結合集積回路。(4) The light-emitting element and light-receiving element formation layer should be a layer lower than the top layer of the main body of the integrated circuit. 92. The optically coupled integrated circuit according to claim 91, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56190627A JPS5893268A (en) | 1981-11-30 | 1981-11-30 | Photocoupling integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56190627A JPS5893268A (en) | 1981-11-30 | 1981-11-30 | Photocoupling integrated circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5893268A true JPS5893268A (en) | 1983-06-02 |
Family
ID=16261210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56190627A Pending JPS5893268A (en) | 1981-11-30 | 1981-11-30 | Photocoupling integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5893268A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4695120A (en) * | 1985-09-26 | 1987-09-22 | The United States Of America As Represented By The Secretary Of The Army | Optic-coupled integrated circuits |
| JPS6484753A (en) * | 1987-09-28 | 1989-03-30 | Nec Corp | Optical connection circuit |
| US4953930A (en) * | 1989-03-15 | 1990-09-04 | Ramtech, Inc. | CPU socket supporting socket-to-socket optical communications |
| WO2009113141A1 (en) * | 2008-03-11 | 2009-09-17 | パナソニック株式会社 | Integrated circuit package |
| JP2010045410A (en) * | 2009-11-24 | 2010-02-25 | Fujitsu Ltd | Photoelectric integrated circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS566479A (en) * | 1979-06-26 | 1981-01-23 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
-
1981
- 1981-11-30 JP JP56190627A patent/JPS5893268A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS566479A (en) * | 1979-06-26 | 1981-01-23 | Mitsubishi Electric Corp | Semiconductor integrated circuit |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4695120A (en) * | 1985-09-26 | 1987-09-22 | The United States Of America As Represented By The Secretary Of The Army | Optic-coupled integrated circuits |
| JPS6484753A (en) * | 1987-09-28 | 1989-03-30 | Nec Corp | Optical connection circuit |
| US4953930A (en) * | 1989-03-15 | 1990-09-04 | Ramtech, Inc. | CPU socket supporting socket-to-socket optical communications |
| WO2009113141A1 (en) * | 2008-03-11 | 2009-09-17 | パナソニック株式会社 | Integrated circuit package |
| JP2010045410A (en) * | 2009-11-24 | 2010-02-25 | Fujitsu Ltd | Photoelectric integrated circuit |
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