JPS5884525A - Pulse generating circuit - Google Patents
Pulse generating circuitInfo
- Publication number
- JPS5884525A JPS5884525A JP18395581A JP18395581A JPS5884525A JP S5884525 A JPS5884525 A JP S5884525A JP 18395581 A JP18395581 A JP 18395581A JP 18395581 A JP18395581 A JP 18395581A JP S5884525 A JPS5884525 A JP S5884525A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- output terminal
- power supply
- gate
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/153—Arrangements in which a pulse is delivered at the instant when a predetermined characteristic of an input signal is present or at a fixed time interval after this instant
- H03K5/1534—Transition or edge detectors
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Pulse Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はワンショットパルス発生回路に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a one-shot pulse generation circuit.
従来のこの種回路としてはワンショットマルチバイブレ
ータ回路などが知られているが、いずれも回路構成が複
線であるので、簡便な回路が望まれている。One-shot multivibrator circuits and the like are known as conventional circuits of this type, but all of them have a double-wire circuit configuration, so a simple circuit is desired.
この発明は以上のような点に鑑みてなされたもので極・
めて簡単な構成でワンショットパルスを発生する回路を
提供することを目的としている。This invention was made in view of the above points, and is extremely
The purpose of this invention is to provide a circuit that generates a one-shot pulse with a simple configuration.
第１図はこの発明の一実施例を示す回路図で、図におい
て、ＧＬｌはそのソースおよびゲートが電源ｖｃｃ Ｋ
接続され、ドレインが出力端子ＯＵＴに接続された第１
のＭ０８トランジスタ（ＭＯ８Ｔ）、Ｑ２はソースが出
力端子０ＵＴＫ接続され、ゲートが内部端子Ａに接続さ
れ、ドレインが接地された第２のＭＯ８Ｔ。FIG. 1 is a circuit diagram showing an embodiment of the present invention. In the figure, GLl has its source and gate connected to the power supply vcc K
and the drain is connected to the output terminal OUT.
The M08 transistor (MO8T), Q2, is a second MO8T whose source is connected to the output terminal 0UTK, whose gate is connected to the internal terminal A, and whose drain is grounded.
Ｑ３はソースが出力端子０ＴＩＴに接続され、ケートお
よびドレインが内部端子Ａにｉ統された記３のＭＯＥＩ
Ｔ。Q3 is the MOEI of Note 3 whose source is connected to the output terminal 0TIT and whose gate and drain are connected to the internal terminal A.
T.
Ｃは入力端子ＩＮと内部端子Ａとの間に接続されたコン
デンサである。C is a capacitor connected between the input terminal IN and the internal terminal A.
次に、この実施例回路の動作についてＭＯ８Ｔはすべて
エンハンスメント形として説明する。第２図は入力端子
ＩＮに電圧ｖｃｃが印加されたときの動作を示す各端子
電圧の波形図である。最初は入力端子電圧ｖ、、Ｆｉｏ
ｖであり、内部端子Ａの電圧ｖＡも０■であるとすると
、第１のＭＯ８ＴＱ、はオン状態、第２のＭＯ８ＴＱ２
はオフ状態にあるので、出力端子ＯＵＴの電圧Ｖ。８．
はＶ。。−一となっている。但し、ｖＴＨはＭＯ８Ｔの
しきい値電圧である。そして、この時には第３のＭＯ８
Ｔ Ｑ３もオフ状態にある。このような状態で久方端子
ＩＮに電圧Ｖ。Ｃが印加されると、入力端子電圧ｖ１．
ｌはＯＶがらＶ。−ｃ、に変化する。Next, the operation of this embodiment circuit will be explained assuming that all MO8Ts are of the enhancement type. FIG. 2 is a waveform diagram of each terminal voltage showing the operation when the voltage vcc is applied to the input terminal IN. Initially, the input terminal voltage v,, Fio
v, and the voltage vA of internal terminal A is also 0■, the first MO8TQ is in the on state, and the second MO8TQ2 is in the on state.
is in the off state, so the voltage at the output terminal OUT is V. 8.
is V. . -It is one. However, vTH is the threshold voltage of MO8T. And at this time, the third MO8
TQ3 is also in the off state. In this state, voltage V is applied to Kugata terminal IN. When C is applied, the input terminal voltage v1.
l is OV to V. -c, changes.
そこで、コンデンサＣによって容量結合されている内部
端子Ａの電圧■えもＯＶからｖｏ。へと上昇する０語２
のＭＯ８ＴＱ２のゲートは内部端子ＡＫ接続されている
ので、内部端子電圧ｖＡが上昇し、はじめると導通し、
出力端子電圧Ｖ。ｕ？ｉｊ低ツペヤニする。このと春出
力端子電圧Ｖ。Ｕ、がＶＡ−Ｖ□以下になると、第３の
ＭＯ８Ｔ Ｑ３が導通し、内部端子電圧ｖＡのレベルを
低下させる。この内部端子電圧Ｖム
がしきい値電圧Ｖ□まで下ると第２のＭＯ８ＴＱ２はし
ゃ断し出力端子電圧Ｖ。Ｕ、は再びｖＣｃ−■□まで上
昇する。このようにして出力端子ＯＵＴからワンショッ
トパルスが得られる。この出力端子電圧Ｖ。Ｕ。Therefore, the voltage at internal terminal A, which is capacitively coupled by capacitor C, changes from OV to vo. 0 words rising to 2
Since the gate of MO8TQ2 is connected to the internal terminal AK, the internal terminal voltage vA rises and begins to conduct.
Output terminal voltage V. u? ij low tsupeyani. This and the spring output terminal voltage V. When U becomes less than VA-V□, the third MO8T Q3 becomes conductive, lowering the level of the internal terminal voltage vA. When this internal terminal voltage Vm falls to the threshold voltage V□, the second MO8TQ2 is cut off and the output terminal voltage V. U increases again to vCc-■□. In this way, a one-shot pulse is obtained from the output terminal OUT. This output terminal voltage V. U.
の低レベル伍および、パルス幅は各素子の大きさを適当
に選ぶことによって任意の値に設定できる。The low level 5 and the pulse width can be set to arbitrary values by appropriately selecting the size of each element.
なお、上記説明では第１のＭＯＥＩＴ Ｑ、もエンハン
スメント形としたが、これｔまデプレッション形であっ
てもよく、この場合は出力端子電圧ｖ０６．の高レベル
値はｖｃｃとなる。In the above description, the first MOEIT Q is also of the enhancement type, but it may also be of the depletion type, and in this case, the output terminal voltage v06. The high level value of is vcc.
以上のように、この発明では極めて簡単な構成でワンシ
ョットのパルス発生回路を実現することができる。As described above, according to the present invention, a one-shot pulse generation circuit can be realized with an extremely simple configuration.
第１図はこの発明の一実施例を示す回路図、第２図はこ
の夾施例回路の動作を歇明するための各部電圧の波形図
である。
図において、Ｑｌは第１のＭＯ８Ｔ、Ｑ２は第２のＭＯ
８Ｔ、 Ｑ、３ ｉｉ第３のＭＯ８Ｔ、Ｃはコンデンサ
、ＩＮ＃ｉ入力端子、ＯＵＴは出力端子である。
なお、図中同一符号は同一または相当部分を示す０
（。FIG. 1 is a circuit diagram showing one embodiment of the present invention, and FIG. 2 is a waveform diagram of voltages at various parts to explain the operation of this embodiment circuit. In the figure, Ql is the first MO8T and Q2 is the second MO8T.
8T, Q, 3 ii The third MO8T, C is a capacitor, IN#i is an input terminal, and OUT is an output terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
レインが出力端子に接続された第１のＭＯＳ ）ランジ
スタ、ソースが上記出力端子に接続されドレインが接地
されゲートがコンデンサを介して入力がともに上記第２
のＭＯＳ）ランジスタのゲートに接続された第３のＭ０
８トランジスタを備え、上記入力端子□の電位が接地電
位から上記電源の電位の方向へ上昇したときに上記出力
端子へ１個のパルス電圧を出力するようにしたことを特
徴とするパルス発生回路。ill A first MOS transistor whose source and gate are both connected to the power supply and whose drain is connected to the output terminal.
MOS) The third M0 connected to the gate of the transistor
8 transistors, and outputs one pulse voltage to the output terminal when the potential of the input terminal □ rises from the ground potential toward the potential of the power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18395581A JPS5884525A (en) | 1981-11-16 | 1981-11-16 | Pulse generating circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18395581A JPS5884525A (en) | 1981-11-16 | 1981-11-16 | Pulse generating circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5884525A true JPS5884525A (en) | 1983-05-20 |
Family
ID=16144733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18395581A Pending JPS5884525A (en) | 1981-11-16 | 1981-11-16 | Pulse generating circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5884525A (en) |
-
1981
- 1981-11-16 JP JP18395581A patent/JPS5884525A/en active Pending
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