JPS588361A - Microprogram controller - Google Patents

Abstract

PURPOSE:To improve the reliability and maintainability of a device, by providing a microinstruction readout address being in idle state separately from normal readout addresses and performing the test of a control storage section in parallel with the normal operation. CONSTITUTION:A microinstruction address register 2 giving a readout address for a microinstruction stored in a control storage device 1 and a test address register 6 giving readout address for the test of the device 1 are provided. Further, an idle state display device 8 indicating the idle state of the device 1 is provided, and when the device 8 displays the idling state, the control with the microinstruction word read out from the device 1 is suppressed. The microinstruction in the device 1 is read out with the address of the register 6 revised with an adder 7. Thus, if correctable or incorrectable error is detected, the error is reported to an error report control circuit 5 in advance.

Description

[Detailed description of the invention] The present invention relates to a program control device.

Conventionally, in microprogram-controlled information processing devices, one-bit or multiple-bit errors in data are detected and corrected by checking nine Hamming code data added to microinstruction word data read from a control storage unit. Generally, a method is used in which any possible error is corrected and used for control.

However, under normal device operating conditions, 12-bit detection is performed only at the point when the read data is actually about to be used as a microinstruction. Even if the error does not affect the system, if it is an uncorrectable multi-bit error, depending on the program being executed, there is a good chance that it will cause the system to go down, which can have a large impact.

In addition, in the so-called idle state, when a central processing unit issues an input/output request to another device and waits for a response, or until it receives an instruction to be executed or necessary data from main memory, the microprocessor Since the instructions do not require any particular internal arithmetic control, a method is often used in which microinstructions that are prepared for the idle state and that do not contain any effective operations are repeatedly executed and waited for, and the control memory is used for rounding. Access to the same address is performed over and over again, which is wasteful.

The purpose of the present invention is to utilize this idle state to detect failures in the control storage unit at an early stage, thereby preventing data containing errors from being used, and preventing serious failures such as system failure from occurring. An object of the present invention is to provide a microprogram control device that allows appropriate measures such as disconnecting the device from the system.

In order to achieve the above object, a microprogram control device according to the present invention includes a control storage section for storing microprograms, and a microinstruction address register for providing successive addresses and addresses of microinstructions stored in the control storage section. The test address register that provides the read address for testing the control storage section, and the output of the previous 1ev (el instruction address register - the test address register) are selected, and the selected output is Address switching means for determining the successive address of the control storage; and error detection and correction means for detecting correctable errors and uncorrectable errors in the microinstruction word data successively received from the control storage and correcting the correctable errors. and address addition means for adding a constant given in advance to one capacity of the test address register, and registering the address and bit position information of the error detected by the error detection and correction means, and transmitting the information to an external diagnostic device, etc. an error reporting means for reporting an error; and an idle state display means for indicating that the device is in an idle state due to waiting for data at an interface with the outside;
When the idle state display means displays an idle state, it inhibits the control based on the nine microinstructions successively issued from the control storage unit, and also inhibits the microcontroller in the control storage unit based on the address of the test address register updated by the adder. If an instruction is read and a correctable or uncorrectable error is detected, the error is reported in advance.

According to the above configuration, the object of the present invention can be completely achieved since it is easy to disconnect the device in which the error has occurred and reinstall it after repair.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.

In the figure, the registers for providing the read address of the control memory 1 are the i microinstruction address register 2 and the test address register 6, and the output of one of them is selected by the address switching circuit 3. The error detection and correction circuit 4 detects the presence or absence of correctable errors, -■ stopperable errors, in the data successively read out from the control memory 1, and if there is no error, the read data up to t is corrected to any correctable error. The data is supplied via the microinstruction supply control circuit 9 to an arithmetic control section (not shown) where the microinstructions are actually used. Further, if an error occurs, the microinstruction address and bit position information of the error occurrence are registered in the error report control circuit S. This error report control circuit S has an interface for reporting errors to an external diagnostic device or operating software.

The address adder 7 is for adding a predetermined constant to the test address register 6.

Furthermore, the device of the present invention includes an idle flag 8, a flip-flop for indicating the idle state. When this idle flag 8 is on, the data read from the control memory 1 is not supplied to the arithmetic control unit as a microinstruction, and an i microinstruction pattern in the form of "valid operation is not specified" is controlled to be supplied as a microinstruction. It is supplied from the circuit 9 to the arithmetic control section. First, the idle flag 8 controls the access switching circuit 3 to select the output of the test address register 6 as the read address of the control memory 1, and also serves as an update instruction signal for the test address register 6. The error report control circuit S is also controlled by the idle flag 8 to change the Scherer report timing.

FIG. 2 is a timing chart showing one example of the operation of the device of this embodiment.

As shown in the figure, it is assumed that in cycle 0, 11 people are stored in the microinstruction address register □ register 2 and the test address register 6, respectively, and that the idle flag 6# is off. At this time, the microinstruction address register 20 output pin "al" is selected by the address switching circuit 3, the microinstruction at address a is successively outputted from the control memory 1, and the error detection and correction circuit 4 and the microinstruction supply control circuit 9 to the arithmetic control unit. If there is a correctable error in the Mitaro instruction data at address a, the address (address 1a1) information and NIL bit position information are supplied to the error reporting control circuit S.
will be registered. However, without reporting the error to an external diagnostic device or the like to a friend, the error detection and correction circuit 4 corrects it and uses the nine data as a microinstruction to continue processing.

Information such as the number of occurrences, addresses, and bit positions of correctable errors registered in the error report control circuit 5 can be collected by an external diagnostic device at regular intervals, or can be collected by the error report control circuit S itself. It is also possible to collect information by adding an automatic reporting function when errors occur more than a certain frequency. An error report is made to the i microinstruction data device at address a, and measures are taken such as rewiping the instruction or disconnecting the error device from the system.

Now, in cycle 1, address b! The test address register 6 also holds the value 1A1 during execution of the current instruction.
This is because the test address register 6 is configured to be inhibited from being updated while the row idle flag 8 is off.

Assume that when the V Italo instruction at address 11@ is subsequently executed in cycle 2, the idle flag 8 is turned on by an instruction from the arithmetic control unit because the data required to execute the arithmetic operation is not ready. .

Due to this, from the microinstruction supply control circuit 9,
Regardless of the read data from the control memory 1, an idle state microinstruction pattern is supplied to the arithmetic control section;
The arithmetic control section does nothing other than control for canceling the idle state. At the same time, the address switching circuit 3
selects the test address register 6, so the microinstruction at address A is read out and becomes an input to the error detection/correction circuit 4.

If there is no error in the data at address A, the idle flag is set to 8.
is on, the test address register 6 is updated to "A+N" at the end of cycle 2 and the process moves to cycle 3.

Thereafter, in the same way until cycle 5 when idle flag 8 is on, A, A+N, A+2N 1 person + 3N
The presence or absence of an error is checked by issuing microinstructions at each address one after another.

At this time, if there is an error in the data, it is registered in the error report control circuit 5.

However, even if the error that is detected is an error that cannot be corrected, it should be reported to an external diagnostic device immediately, and before processing the error, it should be limited to only reporting the error, and the program that is currently being processed should be checked.

Even if you report the error after running up to the end of i, or report the error to a friend, you can minimize the impact on the entire system by reporting the idle state at the same time. It is possible.

As mentioned above, during cycles 2 to 5, after the so-called dummy O-Q instruction is generated for error checking, when the idle flag 8 is turned off from the cycle art, the original microinstruction sequence at address C is executed. In order to return to , the address switching circuit 3 selects the i-equipment instruction address register 2 side. Then, the test address register 6 remains in an update inhibited state with "4N" stored in it until the next time the idle flag 8 is turned on. In cycle 9.10, the idle flag S is turned on again. ), microinstruction data at addresses 4N and 5N are checked.

In this way, each time the device enters the idle state, the test address register 6 is updated while the control memory 1' is read out, and the error detection and correction circuit 4 can perform error detection. At the same time, control
Before the failure of the 111 has a fatal impact on the information processing system, a maintenance person or operating software can disconnect the error generating device from the system based on the report from the error report control circuit 5, and restart the system after repair. It becomes easy to incorporate into

Note that, depending on the value N to be added by the adder 7, N=1 is sufficient to search all addresses, or, taking into consideration the number of words of the memory circuit elements used in the control memory 1, for example, Even if N-=256, etc., it is effective. □ As explained in detail above, the present invention provides the i-microinstruction output address in the idle state separately from the normal subsequent output address so that the test of the control memory unit can be performed in parallel during the normal operation of the device. As a result, the reliability and maintainability of the microprogram-controlled information processing device can be improved.

[Brief explanation of drawings]

FIG. 1 is a plotter diagram showing one embodiment of the present invention, and FIG. 2 is a time chart for explaining the operation of the apparatus of the embodiment shown in FIG. l...Control storage unit 2...Micro instruction address register 3...Address switching circuit 4--Error detection and correction circuit 5...Error report control circuit 6...Test address register 7...Adder 8...Idle flag (blip-flop) 9--1
Microcommand supply control circuit

Claims (1)

[Claims] a control memory section that stores a microprogram; a microinstruction address register that provides a start address for a microinstruction stored in the control memory section; and a test address that provides a start address for testing the 1# control storage section. a register, an address switching means for selecting one of the outputs of the microinstruction address register and the test address register, and selecting the selected output as a successive address of the control storage unit; error detection and correction means for detecting correctable and uncorrectable errors and correcting correctable errors in the micro-instruction word data; and address addition means for adding nine constants given in advance to the contents of the test address register. In the error detection and correction means, a rounding error reporting means registers the address and bit position information of the detected error and reports the error to an external diagnostic device, etc., and the device waits for data at the interface with the outside. an idle state display means for indicating that the idle state is to be set; and 9, when the idle state display means indicates the idle state, suppressing control by the 'V micro command' read from the control storage unit;
A microinstruction controller configured to read microinstructions in the control storage section according to the address of the test address register updated by the adder and report the error in advance if a correctable or uncorrectable error is detected. Features i-microprogram control device.