JPS5869165A - Information reading and recording device - Google Patents

Abstract

PURPOSE:To simplify the constitution of a driving circuit of a heat generating body and to reduce the power consumption, by providing a plurality of information reading sections shifted their positions each other toward the original carrying direction, and a plurality of recording sections shifted their positions each other toward the carrying direction of recording paper. CONSTITUTION:Picture information read at a photodetector CS using a CCD linear image sensor of a prescribed bit, in a self scanning type photodetector CS, is binary coded at a digitized circuit AD and applied to a shift register SR. The information is converted in parallel at the register SR and stored in a latch circuit L1. Data of an odd number block group of the output from the circuit L1 is stored in a memory M1 and that of an even number block group is stored in a memory M2. The data selectively read out from the memories M1, M2 are stored in a latch circuit L2 once, each output is outputted to NAND gates NG1-NG36, and transistors TP1, TP32 are selectively operated with the output of a print instruction line L10 from a control circuit CC to simplify the constitution of a heater drive circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for reading and recording document information, and more particularly to an apparatus in which a reading section and a recording section are devised.

FIG. 1 is a diagram showing an example of a heating element drive circuit that can be used in the present invention, and FIG. 2 is a waveform diagram for explaining its operation.

A group is formed by the heating elements IHI to IH32,
Total of 1792 heating elements IHI ~ 561 in 56 groups
'132, one end of each heating element is connected to a control element, for example, 56 groups of diodes ldl to 1d32, a total of 1792 diodes ldl to 56d3.
Connected to 2. Each diode is connected to pixel information input terminals P1 to P32. Heating element IHI~I
The other end of H32 is connected to group selection signal input terminal D1. Heating element 2H1~2■32,...56H1~
56H32 are similarly connected to the group selection signal input terminals D2 to D56, respectively. In this case, each group is time-divisionally driven by a duty 1156 as shown in Figure 2 of the cylinder, driving each heating element to generate heat. As shown in Figure 2, in the case of DI where pixel information PI etc. are sparsely generated, the power to drive them simultaneously is not so great, but when driving 32 heating elements at the same time in D2, it is strange. This results in power consumption.

Figure 3 is an example of a circuit that solves this problem.
G is an image information generator, Dpad group selection signal generator, RGC is a signal generator consisting of a ring counter or ROM, etc., and the heating elements to be driven at the same time are, for example, Hl, H9.
, Hl 7, H2S, and then four more at the next timing (for example, ii'H2, ) 110.1118, H26
This is a rounding circuit that drives . That is, andgutom 1~
The heating element 32 is provided, and only four of every eight heating elements are driven at the same time. With this configuration, the electric power required to simultaneously drive 32 heating elements is 1/8 compared to the case of the example shown in FIG. That is, as shown in Fig. 4, 4 out of 8 of the 32 heating elements are driven to first print 4 dots, then print 4 dots adjacent to each dot, and this is completed. .

FIG. 5 is a perspective view of an example in which a recording liquid portion is formed by the above-described heating element drive circuit.

This example is an example of A4 size full multi 8 dots)/IIB. Fifty-six substrates each having 32 heating elements are bonded to two areas of approximately equal area on the top and bottom of a metal plate H8 that also serves as a heat sink, and 32 grooves are cut on each of the substrates 881 to 8856 with heating elements. da play) JBI~JB50
are joined. Ink introduction vias 'OP1 to 0P56 are connected to each grate, and each ink introduction pipe is connected through ink supply pipes op and Ep connected to an ink tank IT. ]) A1~pm5
Reference numeral 6 denotes a control element array, such as a diode chip, which is connected to each lead wire on the substrate with a heating element. As shown in the figure, the control element chips are divided into two groups, an odd number group and an even number group, and the third chip is placed next to the first chip, and the 40th chip is placed next to the second chip (the same applies hereafter). It is preferable that the dot spacing Q of 8 dots)/M can be uniformly maintained as shown in FIG.

Figure 7.8 is a schematic diagram of a copier or facsimile device to which the above-mentioned full multi-recording head and time-division drive circuit are applied. It has a section RD. A document table PG made of glass or the like is formed above the reading section RD, and a document is placed on this document table PG.

At the top of the document platen PG is a document platen cover PK that fixes the original.
is provided.

At the bottom of the document platen PG, there is a light source BL that illuminates the document, a reflector RM installed so that the light emitted from the light source BL can effectively illuminate the document platen PG, and a self-contained light source with a large number of light receiving elements arranged in a straight line. An optical unit (LS) that meets a scanning light receiver CS and an optical lens for forming an image of a document on the light receiver CS is provided integrally with the light receiver CS. This optical unit LS
and the light receiver CS are fixed to the carriage CA. The carriage CAu guide rail R1, 82- is moved forward in the Q direction or backward in the anti-Q direction by a screw G rotated by the drive of the motor MO. It is also assumed that the main scanning direction of the self-scanning light receiver CS sequentially scans the document surface in the P direction. Therefore, by moving to the carriage C (sub-scanning direction Q), the information of the document placed on the document platen PG is sequentially imaged on the light receiver CS, and the light-receiving elements are sequentially drawn out (main scanning)
If so, it is possible to receive sequential signals obtained by raster I scanning of the original from the light receiver CS.

In this embodiment, the document table PG is fixed and the carriage CA
Although the carriage CA is movable, a structure in which the carriage CA is fixed and the document table PC is movable may be used. When performing copy recording, the carriage CA moves in the Q direction and raster-scans the information on the document table in the P direction -\raster scan. At this time, the recording paper in the recording section records in the R direction while moving in, for example, the 6 directions in FIG. 5 at a speed equal to the moving speed of the carriage 0 in the Q direction. The image information obtained by the reading section is sent to the recording section PH in Fig. 5 via the buffer memory, and recording is performed in parallel with the gun picking. You may perform Kishu again.

The self-scanning photoreceiver CS is a tortoise that consists of a large number of light-receiving elements that convert optical input into electrical signals, and can process these signals in a time-series manner. Examples include a COD image sensor, a Mo5m image sensor, and the like. In this copying device, the width of the original platen in the P direction is 2161El.
(^4, almost equal to the width direction), and 1 as a receiver.
Consider the case where a 728-bit COD linear image sensor is used. The output recording part PH is 1 due to signal processing.
792 dots) 224w, the image sensor and head can obtain a resolution of 8 dots/m. Now, assume that the 28 block arrays above the heat sink plate are the odd number group, the 28 block arrays below the even number group, and the vertical gap interval between the odd and even groups is gsaa, 54 rai/min. . As mentioned above, the CCD cell/CS is 172
It is an 8-bit line sensor that scans each scanning line and outputs a voltage level according to image information. This voltage level is digitized by the digitizing circuit AD shown in Figure 8, and is converted into a binary signal when it has two levels of black and white, and into a multi-valued signal using an analog/digital converter, etc. when gradation (half tone) is required. . For the sake of simplicity, considering binarization, the digitizing circuit AD consists of a comparator color that compares the output voltage of the CCD sensor CS with a reference voltage (slice level). Outputs a binary signal. This digitized data is 3
It is input to a 2-bit shift register fi 8 RK serially, converted into parallel data, and output, and thereafter processed in units of 32 bits. The data output in parallel by the shift register SR is once held in a 32-bit latch circuit L1 and then transferred to the memory section. The memory section is memory M1,
It consists of a memory M2, and the memory M1 is an odd block group J.
B1. J B 3. ... data in memory M
2 is an even block group JB2. Store the data of JB4゜... The data held in latch circuit L1 is 32
Each bit is written alternately to memory M1 and memory M2. Memory M l.

M2 is, for example, RAM (random access memory) C
The memory is a CD memory, a magnetic memory, etc., and its storage capacity is M1-is3z bits, and memory M2 is 56 bits. Each of the memories M1 and M2 consists of 32 bits forming one word, so the memory M1 consists of one word and the memory M2 consists of 1792 words. In addition, the memories Ml, M
The output of L4.2 is connected to the enable signal line L4.2. When L5 is at a high level, it is assumed to be in a high impedance state, a so-called three-state state.

The data selectively read from the memory IJMI, M2 is held in the -1i32 bit latch circuit L2. At this time, the states of the memory M1 and memory M2 are such that when one is in the write state, the other is in the read state, and when one of the latch circuits Ll and L2 holds the data in the memory M1, the other holds the data in the memory M2. is held.

Therefore, the data in the memory M1 and the data in the memory M2 are alternately held in the latch circuit L2.

The data held in the latch circuit L2 is 32 NANDs.
You will be sent to Gates NG1 to NG32, but Nando Goo)
NGI-NG32 selectively operate transistors TPI-'rp32 when timing PG of print command signal line LIO is output from control circuit CC. The collector terminals of the transistors TPI to TP32 are connected to data input terminals P1 to P32 of the recording section PH. When adopting the power-saving drive system as shown in Figs.
-Mu32 may be substituted. The 56 selection signal input terminals D1 to D56 of the recording section PH are transistors TDI to TD.
56, and the transistor TD1
~TD56 is sequentially scan-controlled by the output of the decoding circuit DC. The decoding circuit DC is 6 lines route 56
6 signal lines I from control circuit CC with line decoder
・Controlled by 11. The control circuit CC is a circuit that generates signals for controlling each of the above elements, and a reference clock is generated by a crystal oscillator.

Each control signal will be explained with reference to the timing charts of FIG. 8 and FIGS. 9 and 10. ccn has a signal i as a drive pulse.
At L1, for example, a start pulse φs for starting line scanning, a reset clock φR for the output amplifier, and a two-phase shift clock φ1 for the shift register in the CCD are input. φ2(
(not shown) is given. The pulse interval of the start pulse φX in FIG. 9(1) corresponds to the scanning time of one scanning line,
During this time, 1728 reset clocks φR (2) are outputted from the CC. It is assumed that the reset clock φR is a signal corresponding to the bit of the COD, and when the reset clock φ-R is in a low level state, image information is output from the CCD.

Therefore, the control circuit CC supplies the shift register 8 with a transfer signal SCK having the same period as the reset clock φR and rising when the reset clock φR is at a low level.

In the control circuit CC, this transfer signal SCK is counted and 32
Load clock L CK is applied to latch circuit L1 and latch circuit L2 for each bit.1. LCK2 to Route 15 L3. L
Give at 9. The load clock LCK1 applied to the latch circuit L1 rises after the 32-pulse shift clock 8CK is issued, as shown in FIG. 9(4).

On the other hand, as shown in FIG. 9 (5), the memory enable signal KNB for selecting the memories M1 and M2 becomes low level after the load clock LCK1 of the latch circuit L1 rises, making the memories operable. . While this memory enable signal ENB is held at low level, the load clock LCK2 applied to the latch circuit L2 must rise.

The read/write signal R/W that controls writing and reading of memories M1 and M2 is transmitted to the CCD as shown in FIG. 9 (8).
No. 46 whose level changes every reset (32 to η and φ) pulses, and as shown in FIG. 10, the level changes 28 times between -scanning lines. As mentioned above, the memories Ml, M
2, the read operation is reversed, so the memory M
(When the g signal a/W is as shown in the figure, a signal inverted by the inverter I is given to the memory M1 through the signal line L8.

The signal PG input to the Nant gates NG1 to NG32 is a signal that determines the timing and duration of energization to the heating element, and as shown in FIG. 9 (7), the signal PG is applied to the load clock L of the latch circuit L2.
It is given on the signal line L10 after CK2. This signal P
G is also generated every four reset pulses φR32.

When using the above-mentioned driving method, the PG multiplied signal may be further time-divided using a ring counter or ROM in the CC and applied to the above-mentioned AND/GO) Al-I com. The binary signal input to the decoding circuit DC is
- This is the output of a 56-decimal counter that counts up by one every time 32 pulses of the reset signal φR of the ccD are counted. Therefore, the 56 transistors TDI to TD50 are sequentially turned on one by one for each pulse of the reset signal φ132, and sequentially generate selective drive pulses D1 to D56 in FIG. 1 to cause the heating element to generate heat. Here, the operation of FIG. 8 will be described in more detail according to FIGS. 9 and 1o. First, after the CCD start pulse φ is generated,
When the read/write signal R/W is at low level in the second half of the first cycle (at high level, the last two of the previous scanning line
0-order I writes data for the odd-numbered block ROM 10 heating element groups from 8R, Ll to the memory M1.
In the first half of the s2 cycle, the data written in the memory M1 in the first cycle is read to the latch L2, and the data written in the second cycle is read out to the latch L2.
Data for block Dm2 to memory M2! Get into it. Furthermore, in the latter half of the second cycle, data for the third block Dm3 is written to the memory M1, and data for the striped block Dm3 is written to the memory M1.
Read the data of A2 to latch L2.

Thereafter, similar operations are repeated to read out the last block DA55 of the odd block group and read and write LS for the last block DM56 of the even block group.
The next scan is performed when the CCD is scanning a line. Memory M1 is a 1 word x 32 bit memory as described above, and the written data is read out in the next cycle, whereas the memory IJ In M2, the written data is read out in 64 scanning lines (179
(2 read/write cycles) later. That is, the data given to the even block group is data 64 scanning lines before the data currently being read by the CCD. As mentioned above, there are 6 blocks between the odd block group and the even block group.
This is because there is an interval corresponding to 4 lines (8 dragons).

For this reason, it is essential to select an address for the memory M2.

FIG. 11 is a diagram schematically showing the addresses of the memory M2, in which the address decode circuit M2A is stored in the memory M2, the block counter BC and the line counter LC are stored in the control circuit CC.
configured within.

Memory M2 has a storage capacity of 1156 bits, and its contents are 3
Two bits constitute one word (one block), and a unit of 28 words is called one line (896 bits), making up 64 lines in total.

The block counter Be is a 28-decimal counter, and the input clock is assumed to operate at the falling edge of the read/write signal n/W. The state of counting by the block counter BC is shown in FIG.

The line counter LC is a 64-base counter, and counts using the digit-high output (carry) signal line 12 of the block counter BC as an input clock. Output line 73 of block counter BC. The output line 14 of the line counter LC is a signal corresponding to the address selection ML6 in FIG.
It is decoded by address decode circuit M2A to select a memory. In the memory M2, after writing η to the address of the mth block on the nth line,
The output of increases by 1 and reads the address of the (m+1)th block on the nth line.This completes one read/write cycle.) In the first read/write cycle, the address of the (m+1)th block is read out.
Write to the block address. Here the cabinet is 2
When it reaches 8, it returns to 0 and accesses the next line, and when the sieve reaches 64, it returns to 02in.

FIG. 12 shows the image information of the original GK and each latch 1.
FIG. 3 is a diagram showing how data changes in each memory.

The 32-bit data A1 loaded into the latch circuit L1 at the current side T1 is written to the memory M1 at time T2. At time T2, 32 bits of Cheatham 2 following data A1 are loaded into latch L1 at time T2.
At time T4, data A1 in memory M1 is transferred to latch L1, and datum 2 in latch L1 is stored in memory M2, and the next data A3 is loaded into latch L1.At time T4, data A1 in latch L2 is transferred to latch L1. X2 is loaded, data A3 of latch L1 is written to memory M1, and data A4 is loaded to lunch L1.The same operation is repeated thereafter.Here, data X2゜X
4a Current COD scan position ^1. This is information that was read 64 lines before A2... and stored in the memory M2.

FIG. 13 is a flowchart for explaining the operations described above in an easy-to-understand manner.

FIG. 14 shows a reading section RD and a recording section PH according to another embodiment.
It is a figure showing an example of arrangement. As mentioned above, a self-scanning photodetector consists of a large number of photodetecting elements that convert optical input into electrical signals.
The first is something that can delay those signals in chronological order.
The embodiment shown in Fig. 4 consists of four 512-bit CCD sensors CCD1 to CCD4, and the length of the effective light receiving area of one sensor is 12.8 m (25 μ x 512 m).
bit).

With this CCD sensor, 11 in the P direction of the M7 document platen is
05u, and in order to cover this, 1. It is sufficient to use a lens optical system with IM low magnification of 4 times. In this case, the resolution of the hekasei/su is 2048 bits in total. Therefore, it becomes 10 dots/ma.

Therefore, the recording section PH is also composed of 10 heating elements (10 dots)7w, that is, 10 heating elements per 1 m.

As mentioned above, the recording units PH are provided alternately on the upper and lower sides of the heat sink plate S, and these upper and lower blocks form a full-line multi-recording head 1. For example, 2048 inkjet nozzles are connected to 4 printheads. Tsuku TJBI~
It consists of TJB4, and each block consists of 512 heating elements. As shown in the figure, the heat sink plate H8
The vertical oriice gap distance between the blocks installed below (first block TJBI, third block TJB3) and the blocks installed above (second block TJB2, fourth block TJB4) is 28sI11, that is, 280
line If a copying apparatus is constructed by arranging sensors horizontally in a line as in the previous example (or using a 2048-bit digital sensor) for such a recording head, image information corresponding to the gag interval of Oriice, i.e. 280 bits must be provided. Incidentally, in the example of FIG. 5, the fact that the second memory M2 for 56 bits is required is the above-mentioned drawback.

However, in this embodiment, if the sensor arrangement corresponds to the head arrangement as shown in FIG. 14, the system configuration becomes much simpler and does not require memory. That is, the reading section RD shown in FIG.
It is sufficient to take an arrangement like this, scan the CCDC sensor in the Q direction in the figure, and drive the recording section PH using the information. Here, in FIG. 14, CCD sensors CCD2 and CCD4 and ccDI,
15 is a diagram showing a drive circuit for the recording section PH in FIG. 14. IH1
~4H512 is a heating element, ldl~4d512 is a cross
This is a talk prevention diode. There are 20 heating elements H in total.
There are 48 blocks, which are divided into 4 blocks of 512 blocks (
Fig. 14 1st block TJBI~g4 block TJB4
). The 512 heating elements in each block constitute time-division wiring with a duty of 1/16. Therefore, focusing on the first block TJBI, 3
2! (7) By time-divisionally driving the image data input terminals PII-PI32 and the 16 selection signal input terminals D1-D16, the 512 heating elements IH1-IH512 are time-divisionally driven. Therefore, the overall configuration consists of four blocks having exactly the same configuration and driving method as this first block TJBI.

FIG. 16 is a block diagram for driving this embodiment. In FIG. 1, CCD sensors CCDI to CCD4, binarization circuits D1 to AD4, shift registers 811 to SR4, and latch circuits 1 to L^4 are as follows: Since the configuration and operation are exactly the same for the four blocks shown in FIG. 14, only the circuit corresponding to one block will be explained.

As mentioned above, the CCD sensor CCDI is a 512-bit line sensor, scans a 1/4 scanning line, and outputs a voltage level according to image information. This voltage level is binarized according to black and white in a binarization circuit AD1.

The binarization circuit combines the output voltage of the CCD sensor and the reference 'magnetic pressure (
It consists of a comparator that compares the input analog voltage with the slice level (slice level), and outputs a binary signal. If gradation (half tone) is required in copying and recording, multi-value conversion is performed using an analog-to-digital converter or the like.

The data digitized by the binarization circuit D1 is input to a 32-bit shift register SRI, and is converted into a clear signal.
The data is converted into parallel data, and thereafter parallel output processing is performed in units of 32 bits. The output data of the shift register 8R1 is held in a 32-bit shift circuit 1. Latch circuit Lm1
The data held in 32 NAND gates NIL~
After establishing timing with the print command signal PG at Nl32, transistors TII to Tl32 are selectively operated. The transistors Tll to Tl32 have 32 N-
P-N) transistors, each of whose collector terminal is connected to the image flaw data input terminals PII to PI32.

On the other hand, the 16 selection signal input terminals D1 to D16 are connected to the collectors of 16 PNP transistors TDI to TD16. This transistor circuit TDI~TD1
6 is sequentially scan-controlled by the output of the decoding circuit DC. The decoding circuit DC is a 4-line to 16-line decoder, and the 1st to 16th lines of TD1 to TDI6 are sequentially selected by a signal from the control circuit CC.

The control circuit CC is a circuit that generates a drive clock for the COD, a shift clock for the shift register, a latch circuit, a timing clock for the gate circuit, a selection signal for the decoding circuit, etc. These reference clocks are generated by a crystal oscillator. .

Each control signal will be explained using the timing charts of FIGS. 16 and 17. CCD1 to CCD4 have drive pulses on signal line L1, such as a start pulse φX (Figure 17 (1) '') to start line scanning, an output amplifier reset clock φR (Figure 17 (2)), and a shift register. 2-phase shift clock φ1, φ2 (unspecified)
is given by the control circuit CC. The pulse interval of start pulse φX corresponds to the scanning time of one scanning line, and during this period, reset clock φR is generated from 512 pulses CC. This is a signal corresponding to the bit of reset clock φRFiCCD, and reset clock φR is in a low level state. It is assumed that image information is output from the CCD when

Therefore, as shown in FIG. 17 (3), the transfer signal SCK that rises at the same period as the reset clock φR when the reset clock φR is at a low level is connected to the signal line L2 that controls the shift register S81 from the control circuit CC. Given.

In the control circuit CC, the transfer signal 8CK of Jin is counted and 32
A p-clock is applied to the latch circuits LAI to LA4 for each bit via the signal line L3. The load clock (signal line L3) that can be used by the latch circuits LAI to LA4 is shown in Figure 17 (
4), the 32-pulse shift clock (first
After 5CK) in Figure 7 (3) is issued, it rises.

One signal given to the gate circuits NII to NIV32 is a signal P that determines the timing and duration of energization of the heating element.
G, as shown in FIG. 17 (5), the latch circuits LAI to LA
It is applied on the signal line Lll after the load clock of 4 (LCK in FIG. 17(4)). This signal PG is also the reset clock φ.On the other hand, the binary signal input to the decoding circuit DC is hexadecimal during the -scanning line, and is COD
This is the output of a hexadecimal counter that counts up by one every time 32 pulses of the reset signal φR are counted. Therefore 1
The six transistors TD1 to TD16 receive a reset signal φ
One by one is turned on sequentially for each R32 pulse. (See FIG. 2 D1 to D16) This embodiment is extremely preferable because it can save a large amount of memory compared to the previous example.

In this case, if manufacturing accuracy allows, CCD1 to CCD4
and TJBI~? Even if the JB4s are arranged in a straight line, the same effect as described above can be expected.

Moreover, in the event of a failure, CCD1-CCD4, TJ
BI-TJB4 is convenient because it can be separated individually. Also, it is more useful to improve surface accuracy etc. if they are manufactured individually.

Figures m18 and 19 show another embodiment of the present invention, and in this case as well, the geometrical arrangement of the recording section PH and the CCD reading section RD is the same as in the previous example. In this example, the configuration is extremely simple by reducing the number of matrix wiring lines and by sharing the data processing circuit with four CODs. That is, the first
The data processing circuit shown in FIG. 6 processes the information of four CODs in parallel, whereas the data processing circuit shown in FIGS. 1g and 19 processes the information in a serial time-sharing manner.

First, the drive circuit configuration will be explained with reference to FIG. 18. There are 1792 heating elements IHI to 448, and a diode for cross talk prevention is connected to each of them. The 1792 heating elements consist of 4 blocks, and each block has 614 scanning signal input terminals D1 to D14. In addition, the other end of the heating element is connected every 32 wires, and 3
It is connected to two image data input terminals P1 to P32.

The outputs of the four CCDs C8I to C84 in FIG. 19 are input to a 4-line to 1-line analog data selector DS. The analog data selector DS selects CC every 1/4 of one scanning line (2051111 length on the document table).
The inputs of D1 to CCD4 are switched, and the inputs of the four CCDs are sequentially connected to form one scanning line. The selection of inputs for the four CCDs is through the control signal line L12 of the control circuit CC.
This is done sequentially with the following signals.

The rest of the processing is the same as in the first example, with a binarization circuit D, a 32-bit shift register SR, and a 32-bit launch circuit L.
A, 32 Nandogoo) NGI to NG32, image data input terminal PI via transistors P1 to TP32
- Connected to P32. In this case, a 6-line to 56-line decoder is used as the decoding circuit DC.

In this embodiment, the circuit is simplified, but R'+1
Although there is a point that the recording time is four times as long as in the above example, it is not a problem considering the response frequency of the thermal inkjet.

FIG. 20 is a schematic partial cross-sectional view of another example of the recording head. A tapered metal plate H layer is placed on top of the liquid chambers Wl and W2.
are made on both sides of the metal plate H8.

The ejection direction of the recording droplets ejected from the orifice O1 of one liquid chamber W1 is 1, and the ejection direction of the recording droplets ejected from the orifice 02 of the other liquid chamber W2 is 12. The recording member PP is directed onto the same MDP.

Here, even if Gl and G2 are configured in a zigzag manner as shown in FIG.
The sensor CS in FIG. 4 also does not require a zigzag arrangement, and a commercially available one-twin sensor can be used.

Further, a simple circuit as shown in FIG. 19 can be used as the data processing circuit, which is preferable.

FIG. 21 shows another example of the configuration of the heating element, which can be easily manufactured at low cost and has improved packaging density. That is, the selection electrodes P1 to P6 are provided on the heating element resistance layer H as shown in the figure.
etc., and heat generating parts IH2, 3H2, 3H4, 5i14
, 5H6. For example, to select IO2, PI
.

A drive pulse may be selectively applied to P2.

If P5 and P4 are selected, 5H4 will generate heat. It is easy to configure the selection circuit in this way.

This configuration eliminates the need for etching the H layer, making it extremely simple. Of course, a predetermined portion may be etched if necessary.

[Brief explanation of drawings]

Fig. 1 is an example of a heating element drive circuit that can be used in the present invention, Fig. 2 is a waveform diagram explaining its operation, Fig. 3 is a waveform diagram explaining the operation of the other circuit, Fig. 4 is a waveform diagram explaining its operation, and Fig. 5 is a waveform diagram explaining its operation. 6 is a front view thereof, FIG. 7 is an overview of the document reading section, FIG. 8 is a block diagram of an example of the present invention, and FIG.
゜Figure 10 is a waveform diagram for explaining the operation, Figure 11 is a detailed diagram of a portion of the memory, Figure 12 is a diagram showing how the memory contents move during reading, and Figure 13 is a flow chart diagram for explaining the overall operation. , FIG. 14 shows other configurations of the reading section and recording section, FIG. 15 shows the sections of the drive circuit, FIG. 16 is its overall block diagram, FIG. 17 is a waveform diagram for explaining its operation, and FIG. 18 is the number of sections of other drive circuits, Fig. 19 is its overall block diagram, and Fig. 2
0 shows other sections of the recording section, and FIG. 21 shows other sections of the recording section. 15th figure

Claims (1)

[Claims] An information reading and recording device comprising: a plurality of information reading units arranged offset from each other in a document feeding direction; and a plurality of recording units arranged offset from each other in a recording paper feeding direction.