JPS5863138A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS5863138A JPS5863138A JP56162266A JP16226681A JPS5863138A JP S5863138 A JPS5863138 A JP S5863138A JP 56162266 A JP56162266 A JP 56162266A JP 16226681 A JP16226681 A JP 16226681A JP S5863138 A JPS5863138 A JP S5863138A
- Authority
- JP
- Japan
- Prior art keywords
- reactor
- film
- sih4
- phosphine
- sio2 film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
- C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
- C23C16/40—Oxides
- C23C16/401—Oxides containing silicon
- C23C16/402—Silicon dioxide
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Inorganic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Formation Of Insulating Films (AREA)
- Semiconductor Lasers (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特にガリウム砒
素(GaAs)等のI−V族化合物又はゲルマニウム(
Ge)等を主成分とする半導体基板上に二酸化シリコン
(Sing)膜を形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device, in particular a method for manufacturing a semiconductor device using a group IV compound such as gallium arsenide (GaAs) or germanium (
The present invention relates to a method of forming a silicon dioxide (Sing) film on a semiconductor substrate whose main component is Ge) or the like.
例えば0.8μ帯レーザダイオード素子を形成する場合
には、QaAs 基板にアルミニウム(Ag)及び不純
物としてのゲルマニウム(Ge) やスズ(Sn)i
適数含有する多層のエピタキシャル層全形成した後、5
i02 膜上形成して写真蝕刻技術を介して8 i 0
2膜に開孔を設け、該5i02を拡散マスクとして亜鉛
(Zn)’に所定の深さまで熱拡散してンーザダイオー
ド素子の内部構造を形成する方法がとられるが、この5
102膜の形成には通常モノシラン(8iH4)k酸素
(02)雰囲気中で300〜500℃に加熱して熱分解
せしめる気相成長法によるか、又は酸化シリコン(Si
n)等k 10−” 〜10−”Torr 程度ノアル
コン(Ar )減圧雰囲気中にて高周波スパッタリング
して前記基板上に5in2膜を堆積せしめる方法がとら
れている。For example, when forming a 0.8μ band laser diode element, aluminum (Ag) and impurities such as germanium (Ge) or tin (Sn) are added to the QaAs substrate.
After forming all the multilayer epitaxial layers containing an appropriate number, 5
8 i 0 formed on the i02 film and through photo-etching technology
A method is used in which the internal structure of the laser diode element is formed by providing an opening in the two films and using the 5i02 as a diffusion mask to thermally diffuse the zinc (Zn)' to a predetermined depth.
The 102 film is usually formed by a vapor phase growth method in which monosilane (8iH4)k is thermally decomposed by heating to 300 to 500°C in an oxygen (02) atmosphere, or silicon oxide (Si
A method has been adopted in which a 5in2 film is deposited on the substrate by high frequency sputtering in a reduced pressure atmosphere of Arcon (Ar) at about k 10-'' to 10-'' Torr.
しかしながらSiH4to2中で熱分解して8i02を
得る気相成長法では前記GaAs(e生成分とする)基
板のガリウム(Ga) が酸化する事等によって後続
のZnの熱拡散に際しGaAs 面とS10□膜間の沿
面拡散が生じ拡散パターンが拡がって段組形状からずれ
てしまい、レーザダイオード素子では主要性能の一つで
ある閾値電流が増加してしまう、父、この沿面拡散はQ
a A s 基板の板面状態や、5iH4102の分
圧比、5i02 膜の成長温度、更にZn拡散温度、Z
n拡散時のGaAs基板表面の晒れる雰囲気等々多要素
によって影響金堂けるため沿面拡散の程度を制御する事
は殆んどできない。従って設計上のレーザダイオード性
能全実現する事は至難となる。However, in the vapor phase growth method for obtaining 8i02 by thermal decomposition in SiH4to2, the gallium (Ga) on the GaAs (e-generating component) substrate is oxidized, so that during the subsequent thermal diffusion of Zn, the GaAs surface and the S10□ film are Creeping diffusion between the two occurs, causing the diffusion pattern to expand and deviate from the stepped shape, increasing the threshold current, which is one of the main performance characteristics of a laser diode element.
a A s The surface condition of the substrate, the partial pressure ratio of 5iH4102, the growth temperature of the 5i02 film, the Zn diffusion temperature, Z
It is almost impossible to control the degree of creeping diffusion because it is influenced by many factors such as the atmosphere to which the surface of the GaAs substrate is exposed during n diffusion. Therefore, it is extremely difficult to achieve the full designed laser diode performance.
又、SiO等を減圧Ar雰囲気下で高周波スパッタリン
グする事によりGaAs 基板上に形成した5iOz
膜はアモルファス(非晶質)な膜を形成する事が難しく
Zn拡散のマスクとして機能させるに十分な膜質が得ら
れない。即ち高周波スパッタリングのエネルギはGaA
s 基板表面のスパッタリング損傷音生じない程度に制
約されるため、下地加熱金少々した程度では均質なアモ
ルファス5i02 換金形成できないためであυ、拡散
時ピンホール状拡散を生じ著しい場合には設計パターン
が実現できない状態に陥る事もある。従ってスパッタリ
ングによるS i O2換金形成し友上に更に気相成長
による5i02 膜を重ねてZn拡散のマスク全形成す
る等の工夫がなされる事もあるが、この方法は二重に工
程全独る事の他に拡散に先立ち二層の5i02 膜全開
孔せねばならないが異質の8i0z 膜のエツチング速
度が異るため微細形状に於いては特に所望の拡散マスク
パターン全形成する車力り進しいという問題を含んでい
る。In addition, 5iOz was formed on a GaAs substrate by high-frequency sputtering of SiO etc. in a reduced pressure Ar atmosphere.
It is difficult to form an amorphous film, and it is difficult to obtain a film of sufficient quality to function as a mask for Zn diffusion. That is, the energy of high frequency sputtering is GaA
s Sputtering damage to the surface of the substrate is limited to a level that does not cause noise, so it is not possible to form a homogeneous amorphous 5i02 layer by slightly heating the substrate.If pinhole-like diffusion occurs during diffusion and is significant, the design pattern may be Sometimes you may find yourself in a situation where it cannot be achieved. Therefore, some measures are taken, such as forming a SiO2 conversion film by sputtering and then layering a 5i02 film by vapor phase growth to form the entire mask for Zn diffusion, but this method doubles the entire process. In addition, prior to diffusion, the two layers of 5i02 film must be completely opened, but because the etching speed of the different 8i0z film is different, it is said that it is difficult to fully form the desired diffusion mask pattern, especially in the case of fine shapes. contains problems.
上記の不具合は、GaAs 、 インジウム燐(InP
)のIN−V族化合物や、ゲルマニウム(Ge)等にS
i 02 換金形成する場合は、シリコン(St″L
J:。The above defects are caused by GaAs, Indium Phosphate (InP)
) IN-V group compounds, germanium (Ge), etc.
i 02 When forming into cash, silicon (St″L
J:.
に5i02 膜を形成した時の如き連続的結合組織が形
成されないため、広く一般的に生じる本発明は上記鑑み
なされたもので再理性よく安価にかつ製品信頼度の篩い
安定した構造を与える新規なQ a A s 基板等上
への5iOz 膜形成を主とする半導体装置の製造方法
全提供する事を目的とするものである。Since continuous connective tissue is not formed as in the case of forming a 5i02 film, the present invention, which occurs widely and generally, has been made in view of the above, and is a novel method that provides a stable structure that is efficient, inexpensive, and has high product reliability. The purpose of this invention is to provide a complete method of manufacturing a semiconductor device, which mainly involves forming a 5iOz film on a QaAs substrate or the like.
本発明によればI−V族化合物又はゲルマニウム(Ge
)’e主成分とする半導体基板上に二酸イヒシリコン(
Si02)膜を形成するに際し、不活性雰囲気又は還元
性雰囲気中で前記基板’e300〜500℃に保持して
ホスフィン(PHa)又はホスフィン混合ガスを予め反
応炉内に通気した後モノシラン(SiH4)及び酸素(
02)全通気して8102膜を形成する工程を含む裏金
特徴とする半導体装置の製造方法が得られる。According to the present invention, a group IV compound or germanium (Ge
)'e Ihi silicon dioxide (
When forming a Si02) film, the substrate is maintained at 300 to 500°C in an inert atmosphere or a reducing atmosphere, and phosphine (PHa) or a phosphine mixed gas is passed into the reactor in advance, and then monosilane (SiH4) and oxygen(
02) A method for manufacturing a semiconductor device featuring a backing metal including a step of forming an 8102 film through complete ventilation is obtained.
以下本発明について、前例のレーザダイオード素子の製
造方法に例をとって詳細に説明する。Hereinafter, the present invention will be explained in detail by taking as an example the method for manufacturing a laser diode element described above.
QaAs 基板上に八!及び添加不純物(Ge又はSn
等)全設計量含有した多層エピタキシャル層全形成した
後、該基板を石英等よシなる反応炉中に挿入し、Ar等
の不活性雰囲気下又は水素(H2)等全少量含む弱還元
性雰囲気下で300〜500 ℃程度の所定の温度に昇
温する。しかる後に、予め5iQ2 膜形成時にリン(
P)の含有率が3〜ole
10 チ程度になる様に設定したSiH,。QaAs Eight on the board! and added impurities (Ge or Sn
etc.) After forming the entire multilayer epitaxial layer containing the entire designed amount, the substrate is inserted into a reactor made of quartz or the like, and placed in an inert atmosphere such as Ar or a weakly reducing atmosphere containing a small amount of hydrogen (H2), etc. The temperature is then raised to a predetermined temperature of about 300 to 500°C. After that, phosphorus (
SiH, the content of P) is set to be about 3 to ole 10 .
5−
02、ホスフィン(PHs)ガス流量のうち、PH3を
前記反応炉内に導入する。反応炉内にPH3が行きわた
る時間経過後PH,’i通気のままSiH4及び02全
同時に反応炉内に導入して、5iFI4の熱分解酸化反
応を生ぜしめる、所定の時間を経ole
過すれば、Pが3〜10 チ程度含有する5i02
膜が得られる。5-02. Of the phosphine (PHs) gas flow rate, PH3 is introduced into the reactor. After a period of time for PH3 to spread throughout the reactor, SiH4 and 02 are introduced into the reactor at the same time while still being vented to cause a thermal decomposition oxidation reaction of 5iFI4. , 5i02 containing about 3-10% P
A membrane is obtained.
通常5iH4102系による8i02 膜成長はSiH
4熱分解によるSi微粒の析出全防止(SiH4単独の
熱分解は更に高温で生ずるか02混気により分解反応が
促進される)するためやや02リツチなガス条件下で行
われるので、前述の問題に至るが、還元性のPH,雰囲
気下に5iH4102が導入されて、Sing 形成反
応と、P2O5の形成反応とが同時進行し、QaAs
基板表面が直接加温状態の02に晒れる事がなくP成分
全含有したS Io 2 が直接生成しはじめると考え
られる、一方、P成分を3〜l Q mole%程度含
有した5i02 膜は、通常S i Ha / 02
系によって気相成長したSing 膜と殆んど同様な
化学触刻6一
性能含有する為、写真蝕刻加工時のエツチング不具合等
は全くなく再理性良くマスクパターンの形成がなされる
、又、P2O5成分を、少量含有する事によって、一層
均質な歪みの少い気相成長8i02膜が形成される事が
知られており、拡散時のピンホール状のマスク不全も生
じない。従って後続のZn拡散に於いて、G a A
s 基板狭面での沿面拡散もなく設計値通シのZn拡散
層を該基板多層エピタキシャル層内に安定して形成でき
る。Usually 8i02 film grown by 5iH4102 system is SiH
4. In order to completely prevent the precipitation of Si fine particles due to thermal decomposition (thermal decomposition of SiH4 alone occurs at an even higher temperature, or the decomposition reaction is accelerated by 02 mixed air), the process is carried out under slightly 02-rich gas conditions, which solves the above-mentioned problem. However, when 5iH4102 is introduced in a reducing PH atmosphere, the Sing formation reaction and the P2O5 formation reaction proceed simultaneously, resulting in the formation of QaAs.
It is thought that the substrate surface is not directly exposed to 02 in a heated state, and S Io 2 containing all P components begins to be generated directly. On the other hand, a 5i02 film containing about 3 to 1 Q mole% of P components, Normal S i Ha / 02
Since it contains almost the same chemical etching performance as the Sing film grown in the vapor phase depending on the system, there is no etching problem during photoetching and mask patterns can be formed efficiently. It is known that by containing a small amount of , a more homogeneous vapor-grown 8i02 film with less distortion can be formed, and pinhole-like mask defects do not occur during diffusion. Therefore, in the subsequent Zn diffusion, G a A
s It is possible to stably form a Zn diffusion layer in the multilayer epitaxial layer of the substrate with no creeping diffusion on the narrow surface of the substrate, and the Zn diffusion layer is consistent with the design value.
更に、後続のメタリゼーション工程等を経てレーザダイ
オード素子全完成すれば設計通りの性能?有し、再理性
のある安定した安価なレーザダイオード素子を実現でき
る。Furthermore, if the laser diode element is completely completed through the subsequent metallization process, will it perform as designed? Therefore, it is possible to realize a stable and inexpensive laser diode element with reproducibility.
纂1図 従来のSiO2膜形成技術を用いた場合のレー
ザダイオード素子構造概念断
面図
(a):従来の気相成長法を用いて形成した5i02膜
を拡散マスクとしてZn
n拡散性行た場合の概念図
(b):従来のスバノタリ/グ法を用いて形成した51
02膜を拡散マスクとし
てZn拡散を行った場合の概念図
第2図 本発明音用いて5i02 膜を形成した場合の
レーザダイオード素子構造の第
1図に対応する工程の概念断面図。
1.11・・・・・・GaAs 基板、2.12・・・
・・・多層エピタキシャル層GaAs (A−g、
Sn、 Qe )。
3・・・・・・従来の気相成長法による5i02 膜、
3′・・・・・・従来の高周波スパッタリングによる5
i02膜、13・・・・・・本発明(の気相成長法)に
よる5102膜、4・・・・・・8i02 膜の開孔部
、5.15・・・・・・5i02膜の開孔部4を通して
拡散され7’(Zn拡散層、5′・・・・・・S i
02 膜ピンホールを通して拡散された拡散層。Schematic diagram 1 Conceptual cross-sectional view of laser diode element structure when using conventional SiO2 film formation technology (a): When performing Zn n diffusion using a 5i02 film formed using the conventional vapor phase growth method as a diffusion mask. Conceptual diagram (b): 51 formed using the conventional Subanotari/G method
FIG. 2 is a conceptual diagram of the case where Zn is diffused using the 02 film as a diffusion mask. FIG. 1.11...GaAs substrate, 2.12...
...Multilayer epitaxial layer GaAs (A-g,
Sn, Qe). 3... 5i02 film produced by conventional vapor phase growth method,
3'...5 by conventional high frequency sputtering
i02 film, 13...5102 film by the present invention (vapor phase growth method), 4...8i02 film opening, 5.15...5i02 film opening It is diffused through the hole 4 and 7' (Zn diffusion layer, 5'...S i
02 Diffusion layer diffused through membrane pinhole.
Claims (1)
半導体基板−ヒに二酸化シリコン(SiO2)膜を形成
するに際し、不活性雰囲気又は還元性雰囲気中で前記基
板を300〜500℃に保持してホスフィン(PHa
)又はホスフィン混合ガスを予め反応炉内に通気した後
モノシラン(SiH4)及び酸素(02)Th通気して
StO,膜を形成する工程を含む事を特徴とする半導体
装置の製造方法。When forming a silicon dioxide (SiO2) film on a semiconductor substrate containing 1-V group compound or germanium (Gel) as the main component, the substrate is held at 300 to 500°C in an inert atmosphere or a reducing atmosphere and phosphine is added. (PHa
) or phosphine mixed gas into a reactor in advance, and then monosilane (SiH4) and oxygen (02)Th are vented to form a StO film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56162266A JPS5863138A (en) | 1981-10-12 | 1981-10-12 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56162266A JPS5863138A (en) | 1981-10-12 | 1981-10-12 | Semiconductor device and manufacture thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5863138A true JPS5863138A (en) | 1983-04-14 |
Family
ID=15751178
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56162266A Pending JPS5863138A (en) | 1981-10-12 | 1981-10-12 | Semiconductor device and manufacture thereof |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5863138A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112663137A (en) * | 2020-12-28 | 2021-04-16 | 中电晶华(天津)半导体材料有限公司 | Preparation method of silicon anti-epitaxial wafer |
-
1981
- 1981-10-12 JP JP56162266A patent/JPS5863138A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN112663137A (en) * | 2020-12-28 | 2021-04-16 | 中电晶华(天津)半导体材料有限公司 | Preparation method of silicon anti-epitaxial wafer |
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