JPS5860480A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To improve the package density of a semiconductor memory substantially, by providing one kind of semiconductor memory with plural kinds of word-bit constitutions through an added decoder circuit and a switching circuit, and simplifying the constitution of an information processor. CONSTITUTION:When a switching control signal (bO has a high level, an added decoder circuit 4 is not activated and pieces of informations d1-d4 of 4-bit constitution, etc., decoded by a decoder circuit 2 and read out of a memory cell array 1 are outputted to terminals D1-D4. When this signal (b) drops to a low level, the circuit 4 is activated and the pieces of information d1-d4 are further decoded into one-bit information d' according to additional addresses from address input terminals A11-A12 and then outputted to the terminal D1 through a switching circuit 5 controlled by a signal (b) and a buffer 3 to obtain various kinds of word bit information. Therefore, one semiconductor memory has plural kinds of word bit constitution and the constitution of the information processor is simplified to improve the package density of a semiconductor memory substantially.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory having two or more different word-bit configurations.

A conventional memory of this kind, for example, a read-only memory, was constructed as shown in FIG. Here 1
is a memory cell array containing N memory units that store 1-bit information, a decoder circuit that decodes 21N/M bits of information, a 3-digit output buffer, and a 0-bit address signal from A1 to AK0 that is manually generated. These are address input terminals and Dl to I) M&co data output terminals. Furthermore, K
O, M, N fd'i! ”:N by number
N, tog2 <Ko< 1 +log2 y, the article f'1? ): Qtaz. Below, N=4096, M=4, ](o=, IOi
Let me explain as two examples.

As a read operation of this memory, the decoder circuit 2 uses /Io96 address signals a1 to alo of ← self 0 bits.
Connect the 4-bit information d4''-(14 in the binoto to the output buffer 3, i.e., 4Q4-pinoI's tnt t
Decode Qi. After that, the output buffer: (Read information of 1 to D44 bits is output on the C data output terminal through the output terminal, the word bit configuration is 1024 words)
・×4 node (operates as R-format memory. Conventional memory of this kind 1i-1)
It had the disadvantage that it was impossible to operate the tobinodo.For this reason, for example, [124-hood x i
In order to realize two types of word bit configurations, 1 hen and 40969-1 x 1 bit, semiconductor memories with configurations corresponding to each are required, and information processing devices containing these semiconductor memories are expensive and expensive. Since the occupied space increases, the packaging density decreases.

In order to solve these drawbacks, the present invention provides a semiconductor memory in which one semiconductor memory has a plurality of types of word hits.

The present invention will be explained in detail below with reference to the drawings.

FIG. 2 shows a first embodiment of the present invention, 1 to 3.

Al corresponding to A1~AKO~AIO+Dl'
-D4 corresponds to -DM, -D4 is the same as in Fig. 1, and A
KO+I ~A1□~A12 corresponding to 1 for AKO+
To decode the M/L bit information, 1 bit additional address signal aKO+□ to aKO+ is set to 1, that is, "I".
An additional address input terminal inputs I + aII + a12 + a12, 4 is an additional decoder circuit, and 5 is a switching circuit. Also, KI + ” is log2M/L≦
B is an integer that satisfies the conditions of + < 1 + log2, L < M, and B is a control signal input terminal A that inputs a switching control signal.
096, M=4, Ko=IO, ], = ],
Let K, = 2.

1. Use all four data outputs ψ1111.1
In order to operate this memory with a word bit configuration of 1024 words x 4 bits, the control signal 1) =
The 4-bit information d, -d4 decoded by the decoder circuit 2 as " ] " is passed through the switching circuit 5 and connected to the output buffer 3, and the data output terminal fr)+ -
The read information is output to D4. At this time, the additional decoder circuit 4 is not activated because it is ``0''.

Next, in order to operate this memory with a word bit configuration of 4096 words x 1 pinot I by using only one data output terminal for outputting information, it, l) = " (1
” to prevent d1 to d4 from being connected to the lli cover sofa 3 without being decoded, and ■= ” ]
”, activates the decoder circuit 2 and outputs 4 bits of information +1.
4dl to d4 are decoded into information d' of 1 pin 1 by additional address signals all to a+Z, and then connected to output buffer 3 to =5-A, and read information is output to data output terminal D1.

FIG. 3 shows a second embodiment of the invention. 1-5.

A1 to AKO, ie, AI-Alo + D+ and B, are the same as in FIG. The circuit operation is the same as in the first embodiment when this memory is operated in a word-bit configuration of 1024 words x 4 bits.

When this memory 'fr: operates as a word bit configuration of 4096 words x 1 bit, two of the three data output terminals D2 to D4 that are not used for information output, here D3 and D4, are used as additional address input terminals. The operation is similar to that of the first embodiment. That is, by using the data terminal as an additional address input terminal, the number of required terminals can be reduced.

In the above explanation, the operation was explained by assigning one terminal to one bit of the address signal, but by inputting the address signal in a time-sharing manner, multiple bits of address signals can be assigned to one terminal, further reducing the number of required terminals. It is also possible to do so. 1. Although a read-only memory has been described, it is easy to apply the present invention to a single read memory by decoding input information using an additional address signal.

Furthermore, if several additional decoder circuits and switching circuits are used in combination, it becomes possible to provide one semiconductor memory with three or more types of word bit configurations.

As explained above, since the semiconductor memory of the present invention (rll, l) can have multiple types of word pin I (114 configurations), each type of semiconductor memory, not including the semiconductor memory, can have
There is an advantage that the 11th information processing device can be realized at low cost and with high packaging density.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a conventional semiconductor memory; FIG. 2 is a block diagram showing an embodiment of the present invention; FIG. It is a block diagram showing 1. Memory cell array, 2. Decoder circuit, 3.
Output vanofer, 4...Additional decoder circuit, 5...Switching circuit, Ao~Al(0...Paper address human power 4i1i 1"
zAKO+1 to 1 to AKO+: Additional address input terminal, B: Control signal input terminal, D1 to DM: Data output terminal. Patent applicant: Nippon Telegraph and Telephone Public Corporation Representative: Tsune Hakusui and one other person

Claims (2)

[Claims] (1) Equipped with N memory units that store 1-bit information, and a Ko-bit address signal for decoding N7M bits of information (here, sg4≦K. There is a relationship of < 1 + tOg2 M, and N ,M.K.O.
is an integer) and M data output terminals that simultaneously output M bits of read information, so that information can be read out in an N word x M bit configuration. In the memory, an additional 1-bit address signal (where Log2 U≦
+ < 1 + log2e, L < M, where Kl and L are integers); and an additional decoder that decodes M bits of read information into L bits using the additional address signal. circuit and M
further comprising a switching circuit that selectively uses L data output terminals from among the data output terminals, and by activating the additional decoder circuit and the switching circuit, L bits of read information after decoding by the additional decoder circuit are read out. A semiconductor memory characterized in that the information is read out in a configuration of U words×L bits by simultaneously outputting the information to the L data terminals. (2) When reading information in a word x L bit configuration, part or all of the (IVI-L) data output terminals that are not used for data output are used as the additional address input terminals. Claim 1:
Semiconductor memory described in Section 1.