JPS5857910B2 - integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention comprises several circuit elements juxtaposed to each other on one side of a semiconductor body, the semiconductor regions of the circuit elements being provided on one side of the semiconductor body, and connected to a pattern of conductive strips for electrical connection of circuit elements, the pattern being provided with at least one input terminal and at least one output terminal for electrical signals;
The present invention relates to an integrated circuit having connections to one or more electrodes and supplying a bias current to one or more of the circuit elements.

The common semiconductor body of such an integrated circuit consists, for example, primarily of an insulating material on which one or more semiconductor regions are formed, or in which a number of such regions are embedded.

However, the common semiconductor body generally constitutes substantially the entire semiconductor material.

Generally, in a single-crystal semiconductor body, and in some cases in whole or in part, circuit elements such as diodes, transistors, resistors and capacitors, with different electrical properties, p-n junctions, Schottky junctions, insulating and conducting A semiconductor device is constructed with a semiconductor region having layers, etc., and circuit elements are connected using a pattern of conductive strips to form a circuit.

When increasing the number of circuit elements per integrated circuit unit,
Many problems arise.

For example, in terms of yield, this is strongly dependent on the amount of semiconductor surface area required by the circuit, such that as semiconductor surface area increases, yield decreases.

Furthermore, the dimensions of the circuit elements affect the high frequency characteristics of the circuit elements themselves.

For example, if the dimensions of the associated circuit elements are large, the cutoff frequency will generally be correspondingly small.

It is also therefore desirable to keep the dimensions of the circuit elements as small as possible and, if possible, to simplify the manufacturing technology.

Another issue concerns permissible consumption.

Although it does not immediately reduce the cost and/or value of integrated circuits, reducing the consumption and therefore the energy consumption of the circuits allows for a wider range of applications for such circuits.

However, other standards also play an important role in consumption.

For example, in the case of large-scale and complex integrated circuits, the overall energy consumption is very large, so strict requirements are placed on cooling the common semiconductor body, and the maximum temperature must be kept below a value that does not prevent the ideal operation of the circuit. is maintained.

Furthermore, for example in battery operating circuits, with regard to the life of the battery, it is desirable to use low power consumption circuits.

Generally, in low power consumption circuits, load resistors with high paper devices for transistors in the circuit are used.

However, such high resistance value resistors require significantly larger semiconductor surface areas, which, as discussed above, can significantly impact manufacturing yields and/or reduce the number of circuit elements per integrated circuit unit. The target becomes smaller.

Also, in connection with the above-mentioned contradictory requirements, conventionally in such integrated circuits the negative resistors are complementary transistors, which are provided within a common semiconductor body and isolated from the remaining other transistors. It is proposed that.

Thus, for example, when finding a compromise between the semiconductor surface area required for a circuit element and the permissible dissipation, increasing the number of circuit elements may result in interconnections and feed lines being used instead of the circuit elements themselves. The pattern of conductive strips required for biasing the circuit elements included will at least determine the required surface area.

The bias current includes all of the current to be supplied to the DC bias circuit element.

These currents, which flow through the emitter and collector of the transistor, typically the current paths of the associated circuit elements and the main electrodes of the transistor, provide the energy available for signal amplification - the ratio between the energy of the output signal and the input signal.

"Feeding strip" refers to the last-mentioned current supplying strip.

A portion of the pattern of conductive strips is formed by the connections necessary for electrically biasing the circuit elements.

In operating conditions, considerable currents flow, especially through the feed strips.

In this strip there is generally almost no voltage loss.

This is why, in particular, the feed strips are often constructed relatively widely in conventional integrated circuits.

Additionally, the associated wires are generally long due to the need to supply current to circuit elements at any location within the circuit.

Therefore, the feed strips required for biasing circuit elements require a significant portion of the space available for the pattern.

This obstructs the installation of the remaining electrically conductive connections within the confined space.

The reason is that it is preferable to avoid cross-connections.

In practice, this problem occurs not only in very large integrated circuits, but also, to a lesser extent, in circuits consisting of a small number of circuit elements.

Dutch Patent Application No. 6800881 (July 1968)
In the publication published on May 24th, an integrated circuit is proposed in which the number of surface conductive strips for supplying bias current is reduced as much as possible.

This integrated circuit is provided with an n-type semiconductor substrate instead of an n-type semiconductor substrate as usual.

Next, a first p-type layer and then an n-type layer are epitaxially grown on this n-type substrate.

Circuit elements are provided within the n-type epitaxial layer as in conventional integrated circuits.

In this case, the function of the n-type epitaxial layer is the same as that of the p-type substrate, at least electrically.

During operation, the negative electrode of an external power source is connected to the p-type layer and the positive electrode is connected to the n-type substrate.

A direct conductive connection is provided between the n-type substrate and one or more portions of the n-type epitaxial layer, and prior to growing the n-type epitaxial layer, the p-type trench layer in the relevant location is Change to n-type by diffusion.

In this way, the two polarity voltages of the voltage source can be obtained virtually at any desired location on the semiconductor surface via a direct low resistance conductive connection.

However, the manufacture of such circuits is significantly more complex than in conventional integrated circuits.

The reason for this is the external p-type epitaxial layer and out-diffusion process to form a conductive connection between the n-type substrate and the n-type epitaxial layer.

It is an object of the present invention to provide new means for circuit integration.

In particular, the present invention takes place within a transistor for a long time,
In addition, a mechanism that allows current to flow into the intermediate layer by injecting charge carriers captured from the intermediate layer through the second junction into the intermediate layer through the first junction is a multilayer structure called a current injection section. (also referred to as a structure) to supply bias current to circuit elements of an integrated circuit in a non-conventional manner, and to incorporate into the integrated circuit a current injector associated with the circuit elements to be supplied by the current injector; In the circuit, use one side of the semiconductor body that is easily available for electrical connection of the current injection part and is common to the circuit elements and opposite to the side on which the pattern of conductive strips is formed. or the current injection part should be biased 1
The technical and It is based on the fact that it is even possible to repair the structure of integrated circuits by electrical means.

According to the invention, in an important feature of an integrated circuit of the above-mentioned type, the common semiconductor body comprises a current injector for supplying a bias current, the current injectors being connected to at least three consecutive current injectors separated from each other by rectifying junctions. Consisting of a multilayer structure with layers, these layers include a first layer, referred to as the injection layer, which is separated from the circuit element to be conditioned by at least one rectifying junction, and an adjacent second layer of semiconductor material, the intermediate layer. The injection layer has a connection to the 10,000 electrodes of the voltage source, and the intermediate layer has a connection to the other electrode of the voltage source, and the injection layer has a connection between the injection layer and the intermediate layer. The rectifying junction is biased in the forward direction, and the charge carriers captured by the third layer of the current injection section adjacent to the intermediate layer are injected from the injection layer into the intermediate layer, as described below. In accordance with one or more aspects of the invention, the current injector is used in close relationship with respect to position and distance to the circuit element to be biased.

The first aspect of the invention is that, according to the invention, in an integrated circuit of the above-mentioned type in which a current injection part is incorporated:
Furthermore, one of the circuit elements is separated by at least two rectifying junctions from the injection layer and hence one power supply connection connected thereto.
One region - referred to as the region to be biased - captures charge carriers from one of the layers of the current injection and thus receives a bias current between the terminals of the rectifying junction bordering said region. Characterized by direct connection to a pattern of conductive strips.

In this way, the current injection portion is coupled to at least the one circuit element to form a compact assembly, in which a rectifying junction that is forward biased and does not essentially belong to one circuit element is formed. The injection of charge carriers between the terminals of , provides the region to be biased with a flow of charge carriers which forms the required bias current in said region.

It is particularly important that it is not absolutely necessary to connect the regions to be biased to the pattern of conductive strips to supply the bias current.

This is one reason why the pattern of conductive strips is simple.

Furthermore, the electrical bias obtained by the current injection is in the form of a supply current, so that the use of resistors is substantially unnecessary.

In addition to the bias current provided by the current injector, electrical signals can, if desired, be applied to or derived from the area to be biased via the pattern of conductive strips.

The regions to be biased of the circuit element can belong to the main electrodes, for example the emitter and collector of a transistor, but these regions can also belong to the control electrodes of the circuit element in question.

According to a second aspect of the invention, the current injection part is coupled to at least one circuit element to form a particularly compact assembly.

An integrated circuit according to a second aspect of the invention comprises a current injector and a region to be biased of one circuit element that captures charge carriers from one of the layers of the current injector, said integrated circuit further comprising: By means of said one layer of current injection part another region of one circuit element is shaped and the region to be biased is connected to another part of the integrated circuit, for example a pattern of conductive strips and/or another circuit element. This particular embodiment, which is characterized by direct connection, is particularly suitable for use in electrical biasing of control electrodes, for example base regions of transistors.

According to a third aspect of the present invention, which can be combined with the above aspects if desired, the current injection section is arranged in a lateral force direction, that is, the current injection section has layers of adjacent current injection sections and the semiconductor body The structure is adjacent to the one side surface of.

In this embodiment of the transverse current injection, the charge carriers carrying the bias current are displaced laterally, ie approximately parallel to the l-side surface of the semiconductor body.

In the integrated circuit according to the third aspect of the present invention comprising a current injection part as described above, one region of the circuit element is separated by at least two rectification matchings from the injection layer and hence one power supply connection connected thereto. - referred to as the region to be biased; these layers of current injection of the same conductivity type as the region to be biased extend adjacent to each other from said one side of the semiconductor body in the same region of opposite conductivity type; , and a surface region of one conductivity type surrounded in the semiconductor body by the region, and the region to be biased together with the region of the opposite conductivity type forms a junction bordering the region to be biased. The region to be biased via the junction captures charge carriers from the region of the opposite conductivity type and therefore receives a bias current, transferring the charge carriers to the region of the opposite conductivity type with which a rectifying junction is formed. The present invention is characterized in that the current is injected from a current injection layer located on the one side surface of the semiconductor body.

Further, according to the embodiment of the current injection part in the direction of lateral force, as will be described in detail below, the pattern of the conductive strips can be significantly simplified. In any case, integrated circuits can be produced with the aid of particularly simple techniques.

According to a fourth aspect of the invention, which can be combined with the first and second aspects if desired, the current injection section is configured in a vertical direction.

An integrated circuit according to a fourth aspect of the invention comprises a current injection part as described above, and further, an injection layer is adjacent to the other side of the semiconductor body opposite to the one side of the semiconductor, and the injection layer is therefore A layer of current injection, referred to as the opposite layer, separated from the connected l power supply connection by at least two rectifying junctions, extends on said one side of the semiconductor body opposite to the injection layer; The layer located on the opposite side captures charge carriers from the layer adjacent to the current injection part via a rectifying junction bordering said layer and thus connects the region to be biased to the layer located on the opposite side of the circuit element. It is characterized in that it receives a current as a bias current for one region, hereinafter referred to as the region to be biased.

Such a longitudinal force-directed current injection embodiment allows current to be obtained at a desired location on said one side of the common body without requiring long conductive strips on said one side.

This bias current is provided using a power connection and a forward biased junction on the opposite side of the semiconductor body.

Also, in this way, particularly simple patterns of conductive strips can be obtained.

The injection layer of the current injection part can be formed, for example, by a metal layer separated by an insulating layer thinner than the semiconductor intermediate layer, and the charge carriers are introduced into the intermediate layer by tunnel injection.

However, it is preferred that the injection layer is a semiconductor layer forming a p-n junction with the intermediate layer.

In a preferred embodiment of the integrated circuit according to the invention, which provides a particularly simple structure, the current injection part has a triple layer structure, the injection layer and the trapping third layer of the layer structure being a semiconductor layer of one conductivity type and an intermediate layer. are of opposite conductivity type, and the region to be biased belongs to the third capture layer of the current injection part.

In the absence of an applied external potential, the trapping layer, typically any layer of the current injector that captures charge carriers from an adjacent layer of the current injector, is placed at a potential that forward biases the rectifying junction between the two associated layers. do.

As a result, charge carrier injection also takes place between the terminals of the capture junction.

When equal amounts of current flow in both directions between the terminals of the capture junction, the voltage across the junction is at a maximum and approximately equal to the voltage across the injection junction of the current injection section.

In all other cases, the value of the forward voltage depends on the value of the (bias) current induced by or from the associated capture layer.

The maximum current is drawn when substantially no voltage is applied across the associated capture rectifying junction.

In this way, by using the current injection part and by supplying a bias current, it is possible to obtain a bias potential for the region to be biased, and the value of this bias potential is connected to the two power supply connections of the current injection part to the power supply. Keep it within the range limited by the voltage between the two.

The maximum bias potential obtained using the current injection part is
Equal to the potential of the highest potential power supply connection, and at least equal to the potential of the lowest potential power supply connection.

Furthermore, the voltage across the power supply connection is made equal to the voltage required to operate the rectifying junction between the injection layer and the intermediate layer in the forward direction.

This voltage is generally kept relatively low.

For example, the value of the forward voltage for a silicon p-'-n junction is typically approximately 0.6 to 0.8V.

In many cases, the entire circuit is operated at the low voltages mentioned above, so that the consumption can be significantly lower.

Also, in an example where a high voltage is to be supplied, main parts of the circuit other than one or more output transistors can be operated at the lower voltage to obtain higher power at the output of the circuit, thereby reducing consumption. You can make a profit by

The current injector can then also be used to supply a bias current to regions of the circuit element operating at a higher voltage than the aforementioned voltages.

In that case, the potential of the region to be biased connected to the current injection section may be located outside the above range to bias the rectifying junction between the region to be biased and the layer adjacent to the current injection section in the opposite force direction. can.

The number of layers in the current injection section can be either an even number or an odd number, but an odd number is preferred.

In an important embodiment of the integrated circuit according to the invention, the current injection part is a multilayer structure with at least five, preferably an odd number of connected layers, the fourth layer of the current injection part adjoining the third capture layer. is a semiconductor layer of the same conductivity type as the intermediate layer, charge carriers are injected into the fourth layer by the third layer, 2,
and the fifth layer captures charge carriers from the fourth layer via the rectifying junction bordering the fifth layer, so that the last layer of the current injection part acts as a bias current for the region to be biased of one circuit element. receives an acting current.

In this embodiment, it is preferable that the intermediate layer and the fourth layer of the current injection part form a continuous region of the same conductivity type within the main body.

A further embodiment of the integrated circuit according to the invention provides a device for controlling the bias current to be injected by the current injection by the region to be biased.

In this way, the bias current can be varied between a value of zero and a value determined by the voltage set up on the power supply connection of the current injector, or can be adjusted to a desired level.

In a five-layer current injector, said control or regulation is simply carried out using an at least temporarily conducting connection between the third layer of capture and a layer adjacent to said third layer of the current injector. be able to.

Such a connection is provided with an electronic switch, such as a transistor, for example.

The bias current to be supplied using the current injection part is supplied, for example, to a diode.

However, it is preferred that the circuit element to be biased is a transistor with at least two main electrodes and at least one control electrode, for example a field effect transistor with source and drain regions and one or more gate electrodes. .

When bipolar transistors are used in the circuit, it is particularly advantageous to use a current injector to supply a bias current to the base region of one or more transistors.

When a current injector is coupled to a transistor, it is possible to form the emitter or collector region of the transistor in question by a layer of the current injector adjacent to the base region to be biased and from which charge is captured by the base region. can.

Particularly in the first-mentioned case, a circuit arrangement of particularly simple construction can be obtained.

This is why it is recommended to provide a circuit with a number of transistors with a common emitter arrangement, so that each base region to be biased captures charge from the same layer of the current injection, said layer forming a common emitter region of the transistors. is suitable.

Therefore, in this way, bias current is supplied to several circuit elements simultaneously using one circuit element.

If the current injection layer is configured vertically, the common emitter region forms a reference potential surface for the circuit or a part thereof, which potential surface separates the circuit elements from the injection layer and the power connections connected thereto. be able to.

Furthermore, by using multiple collector transistors in a common emitter circuit, the circuit can be made much more compact and the wiring pattern can be made much simpler.

In an important embodiment of an integrated circuit in which the bias current is provided in the base region of each transistor by a single injection layer and a single intermediate layer, the collector of the first transistor is connected to the base of the second transistor through a pattern of conductive strips. Connect to.

This cascade arrangement can easily be used in low power and/or linear amplification circuits such as hearing aids or logic circuits such as NOR gates.

In this case, the bias current supplied to the base region of the second transistor may be the base current of the second transistor or the bias current supplied to the base region of the second transistor.
The currents can be supplied to the collectors of the transistors simultaneously or at different times.

Such cascaded integrated circuits can be manufactured in a very simple manner.

This means that particularly for such cascaded logic circuits a significantly simpler wiring pattern can be produced.

The reason for this is that both the control electrode bias current and the main electrode supply current can be supplied by the current injection section.

In addition, such a current supply scheme generally obviates the use of load resistors, and it is therefore possible to use a NOR gate with several input terminals, for example with a number of transistors with a common emitter region. Can be easily configured.

In this case, the collector-emitter paths of each transistor are connected in parallel by collector interconnections.

For example, it is also easy to obtain an integrated trigger circuit consisting of cross-coupled transistors with common emitters.

Such trigger circuits constructed in accordance with the present invention require relatively small semiconductor area, have simple wiring patterns, and have low power consumption, which allows these trigger circuits to be integrated into large scale storage devices. It is particularly suitable for use as a matrix element.

a number of regions to be biased are adjacent to said one side of the semiconductor body, said regions to be biased extend into the same semiconductor layer of opposite conductivity type forming a portion of the current injection portion; A surface region belonging to the layer extends at least between the two regions to be biased, and the surface region has a higher doping concentration than the region to be biased.

Preferably, this highly doped surface region extends from said single face to at least the same depth in the semiconductor body as the region to be biased.

In another preferred embodiment of the integrated circuit according to the invention, at least one region to be biased is formed by forming an injection rectifying junction of the current injection portion and/or one or more highly doped regions on said one side of the semiconductor body. Almost completely surrounded by a surface area.

Preferably, at least one region to be biased is adjacent to one or more such highly doped regions.

Furthermore, one or more surface regions of higher doping concentration extend from above the one side of the semiconductor body into the semiconductor layer and pass almost completely through this layer in the direction of the semiconductor layer.

In another preferred embodiment of the integrated circuit according to the invention, a plurality of regions to be biased are provided adjacent to said one side of said semiconductor body, said regions to be biased being opposite to each other forming part of a current injection portion. An insulating layer extending in a semiconductor layer of the same conductivity type and at least partially embedded within the semiconductor body is provided between at least two of the regions to be biased so that the It extends into the semiconductor layer over at least a portion of the thickness of this layer.

At least one region to be biased on one side of the semiconductor body is almost completely covered by the injection rectifying junction of the current injection part and/or by one or more at least partially embedded insulating layers. surround.

Furthermore, one or more insulating layers at least partially embedded within the semiconductor body extend across substantially the entire semiconductor layer in the direction of this layer.

In another preferred embodiment of the integrated circuit according to the invention, the common semiconductor body is a semiconductor body of opposite conductivity type 7, with which said region and the common emitter region are formed, and on said one side of said body there is a body 7 of opposite conductivity type. A surface layer, referred to as the substrate, is provided with a lower doping concentration than the remaining adjacent portions of the substrate, and the entire semiconductor region and current injection portion of the circuit element is adjacent to the surface of the surface layer spaced apart from the substrate.

In another embodiment of the integrated circuit according to the invention having a group of common emitter transistors, the transistors belonging to this group further form a linear amplifier circuit having two or more DC-coupled transistors; The collector of the transistor is connected to the base of the next stage transistor, and a direct current negative feedback coupling is provided in the amplifier circuit.

In another preferred embodiment of an integrated circuit according to the invention having one or more transistors belonging to a group, the linear amplifier circuit is constructed with two or more DC-coupled transistors and the base region of the first transistor of the group The main electrodes of the direction complementary transistors are arranged, and the direct current coupling is arranged to derive a direct current from the collector of the first transistor, and supplies said current to the other main electrode of the transverse force transistor.

The intermediate layer of the current injection part is a surface layer of the opposite conductivity type, and this layer has a high impurity doping concentration, and one or more buried regions of the opposite conductivity type are adjacent to the rectifying junction configured with the injection layer. The buried region is left as a hole under each region to be biased, and a portion of the intermediate layer having a lower doping concentration than the buried region is placed in this hole up to the rectifying junction with the implanted layer. Extend.

In another preferred embodiment of the integrated circuit according to the invention for at least one region to be biased, substantially all the charge carriers captured by the region to be biased are injected when supplying a bias current. The surface of the rectifying junction is made to be more biased than one or more other regions to be biased.

When the lengths of the edges of the rectifying junctions of the current injection parts facing the at least two regions on the one surface that are to be biased are different, the lateral current injection parts are covered,
Different bias currents can be easily set up for different regions to be biased.

The collector or collectors of the transistors are defined by a metal-containing layer that forms a Schottky junction with an adjacent base region.

In another preferred embodiment of the integrated circuit according to the invention, a semiconductor region of opposite conductivity type is provided in the common semiconductor body, which is adjacent to said one side, and within this semiconductor region, regions of the circuit element to be biased are provided. 1 conductivity type 1 that takes the form of
A current injection portion is provided which extends over at least one surface region and has a layer configured as successive surface regions of different conductivity types, one after the other, in the surface region of at least one conductivity type.

The intermediate layer of the current injection part is a surface region of opposite conductivity type, and a continuous connection part is formed between the region in the semiconductor body and the semiconductor region of opposite conductivity type in a direction substantially parallel to the one surface. extending over a distance such that it forms.

In another preferred embodiment of the integrated circuit of the invention, one of the circuits is
Connecting one or more collector output terminal buttons and in particular one or more collector output terminals of a logic gate circuit to a connection point via an emitter-collector path of a laterally complementary transistor to a relatively A large potential is applied and the bases of the complementary transistors are configured with a common emitter region of the group of transistors, and the emitters of the transistors receive a bias current by trapping charge carriers from the common emitter region.

In another preferred embodiment of the integrated circuit according to the invention, a DC coupling is provided between the collector output terminal of at least one of the circuits and the base region of another transistor, the main electrode of this other transistor being connected to a group of transistors. The other main electrode is connected to a connection point of a relatively large potential outside the voltage range of the current injection part.

For example, DC coupling is provided with emitter-collector paths of laterally complementary transistors.

Furthermore, it is preferable that one main electrode of another transistor is used as a collector and the other main electrode is used as an emitter of said transistor.

In another preferred embodiment of the integrated circuit according to the invention, the binary memory circuit is constructed with a group of trigger circuits in a mad I/J pattern, each trigger circuit having a first button and a second transistor; By connecting the transistor's base electrode to the collector of the other transistor, the circuit can be put into two different information states, thus making one of the transistors conductive and the other cut off or vice versa. , a current injector is provided to supply a bias current to the base of the transistor, and an intermediate layer of the current injector provides a bias current to the base of the transistor;
forming a common emitter region of the transistors and connecting the bases of the first and second transistors to a read-write conductor common to the column of trigger circuits via the emitter collector paths of the lateral complementary transistors; .

In another preferred embodiment of the integrated circuit according to the invention, the injection layer is substantially uniformly doped and extends under the entire area to be biased, viewed from the l side.

Preferably, a more or less uniform doped implant layer extends under the several regions to be biased as a common layer.

The present invention will be explained below with reference to the drawings.

Figures 1 and 2 are diagrams showing a portion of a first reference example of an integrated circuit using a current injection section.

The integrated circuit comprises a plurality of circuit elements, in this case transistors, the base regions of which are designated by 1 to 10.

A semiconductor body 12 common to these transistors as circuit elements
juxtaposed on one side of .

Most of the semiconductor body 12 is made of a semiconductor material, an insulating layer 13 is provided on one surface of the semiconductor surface 11, and a conductive strip 1 is provided on one surface of the semiconductor body 12 between both ends thereof.
Extend pattern 4.

The conductive strips are connected through the holes in the insulating layer 13, indicated by dashed lines in FIG. 1, to the portions of the circuit elements appearing on the semiconductor surface of the holes.

Said strip 14 thus serves as an electrical connection for the transistor.

Furthermore, the semiconductor body 12 is provided with a connection 15 shown diagrammatically in FIG.
ports and 16 are provided and connected to the positive and negative electrodes of a power source 17 to provide bias current to one or more circuit elements.

In the semiconductor body 12 there are in this case mutually rectifying junctions 18 and 1.
A current injection section is provided which is constructed with a multilayer structure having three successive layers 20, 21 and 5 separated by 9.

The first or injection layer 20 is separated from the circuit elements to be biased by at least one rectifying junction or junction 18.

The second or intermediate layer 21 of the current injection part is connected to the first layer and the third layer 2.
0 and 5 are semiconductor layers constituting rectifying junctions 18 and 19, respectively.

One electrode connection part 15 of the power source 17 is also connected to the injection layer 20,
The connecting portion 16 for the other electrode of the power source 17 is provided in the intermediate layer 21 .

The power supply 17 is used to forward bias the rectifying junction 18 between the injection layer 20 and the intermediate layer 21, injecting charge carriers from the injection layer 20 into the intermediate layer 21 and causing current adjacent to the intermediate layer 21. It is captured by the third layer of the injection section.

In addition, the third layer of the current injection portion
Forms the base region of one of the layer transistors 33, 5.21 to be biased.

This base region 5 to be biased is separated from the injection layer 20 and also from the power supply connection 15 connected thereto by at least two rectifying junctions, namely p-n junctions 18 and 19, which are separated by said third region 5. The charge carriers that supply the desired bias current are captured from the intermediate layer 21 of the current injection section through the junction 19 bordering the .

furthermore, connecting said third region 5 to one of the conductive strips 14;
Via this, for example, electrical signals can be supplied or received.

In this reference example, the bias currents for the other remaining base regions 1 to 4 and 6 to 10 are supplied using the injection layer 20 and the intermediate layer 21 in the same manner as described above.

For example, the layers 20, 21 and 10 constitute a current injection part for supplying the bias current to the base region 10 of the three-layer transistor 36, 10.21.

Also, the region 10 to be biased is connected to the injection layer 20.
and from the one power supply connection 15 connected thereto, separated by two rectifying junctions or junctions 38 and 18.

Further, the region 10 extends from the intermediate layer 21 of the current injection part to the junction 3.
8 to capture charge carriers, and the intermediate layer 21 forms one region of the circuit element, in this case one of the outermost regions of a three-layer transistor.

The base regions 10 of transistors 36, 10, 21 to be biased are connected to other three-layer transistors 37.10.21.
Connect to.

This connection is made internally in the semiconductor body 12,
Region 10 forms a common base region for both transistors.

Furthermore, the base region 10 is connected to one of the electrically conductive strips 14, by means of which the base region 10 is led out into the three-layer transistor 33, 5.21.

The injection layer 20 is a semiconductor layer having the same conductivity type as layers 1 to 10 constituting the third or trapping layer of the current injection section.

The layers 1 to 10 and 20 are juxtaposed from one side of the semiconductor body, and the conductive strips are provided in identical regions 21 of opposite conductivity type and are located in the semiconductor body 12 and surrounded by said region 21.

The regions 1 to 10 to be biased capture from this region 21 the charge carriers injected into the region 21 via the rectifying junction 18 from the current injection layer 20 provided on one side.

A portion of the integrated circuit shown in FIGS. 1 and 2 is a masked slave flip-flop shown in FIG.

This flip-flop has 16 transistors T forming 8 NOR gates each having two input terminals.
2□ to T37 are provided.

The collectors of these transistors T2□ to T3□ are designated by corresponding numbers 22 to 37 in FIGS. 1 and 2.

The base regions of the transistors are defined as regions 1 to 10, and regions 1, 3, 4, 6, 7 and 10 form a base region common to the two transistors.

Connect all emitters of the transistors together.

Each of these emitters is constituted by a common emitter region 21 forming an intermediate layer of the current injection section.

The current injection part with the trapping regions 1 to 10 to be biased is indicated in FIG. 3 by current source .

Furthermore, FIG. 3 shows the electrical input terminal IN, the electrical output terminal Q, and the lock pulse connections CPM and CPS for the manuta and slave flip-flop, respectively, and the corresponding conductive strips 14 are designated by the reference numerals shown in FIG. Indicated by the same symbol.

The transistor T3□ shown in FIG. 3 does not actually belong to a flip-flop.

In fact, the collector of the transistor T34 constitutes the output terminal of the flip-flop, and the transistor T3□ belongs to another gate circuit connected to said output terminal of the flip-flop.

In addition, the input terminal of the integrated circuit shown in the figure includes a transistor T2□ which belongs to a flip-flop, and a transistor N of the flip-flop.
The transistor τ37 shown by a broken line in FIG. 3, which constitutes the OR gate, is not provided.

The means for grouping just these transistors T2□ to T3□ as a unit in integrated form is the connection shown between the bases of transistors T36 and T3□.

This connection actually allows the transistor T36 to be simply formed as an extra collector region 37 in the base region 10 of the transistor T36.

As a result, the required semiconductor surface area can be saved.

For the same reason, it is also preferred to configure transistor v37 as an assembly in combination with a part of the circuit preceding the flip-flop, such as a preceding flip-flop.

The use of such multi-collector transistors with a common base region for two or more separate collectors allows for a significantly simpler construction of the integrated circuit.

This is particularly because a multi-collector transistor with, for example, three collectors requires significantly less semiconductor surface space than three separate transistors.

Furthermore, the number of connections required for a multi-collector transistor is significantly smaller than the number of connections required for the same number of isolation transistors, so that the wiring pattern can be made even simpler in the case of a multi-collector transistor.

The flip-flop described above can be a particularly compact integrated circuit.

The reason for this is, in particular, that the current injection part used is connected very closely to the circuit element to be biased.

In addition to the circuit elements used, only other regions are required for the current injection, namely the injection layer 20 and an extra rectifying junction, the p-n junction 18.

The remaining layers of the current injection part are semiconductor layers already necessary for this circuit element itself.

Furthermore, as shown in FIG.
It can be provided on the edge of the

A bias current is supplied internally through the semiconductor body using a current injector.

In this embodiment, the surface 39 of the semiconductor body opposite the surface 11 is also used as the intermediate layer connection, as shown in FIG. 2 by connection 16'.

Since the current injection part can supply not only the bias current to the base region of the transistor but also the emitter collector main current necessary for the transistor,
Integrated circuits can be made simple and compact.

For example, the base region 5 is connected via the conductive strip 14, in particular to the collector region 29.

A DC-coupled cascade connection is formed using the transistor bottom 29 button T33.

When transistor T29 is turned on, the bias current supplied to region 5 by the current injection passes through a substantial portion of said conductive strips to transistor T2. The main current and the supply current flow through the emitter-collector path of the current.

In this way, all of the bias current required for the flip-flop is obtained by a single connected power supply 17.

Furthermore, in this connection, by supplying the bias current as a current by a current injection, the usual load impedance of the emitter-collector circuit of the transistor is superseded.

Generally, this allows considerable space savings.

Another feature is to incorporate a large number of transistors with their emitters directly connected into the circuit.

These connected emitters can be configured as a common emitter region 21.

In this case, the common double-diffused three-layer structure for transistors is used in reverse.

A minimal area provided on the surface and acting as a collector looking into the surface 11 is provided on the base area and is buttoned within the semiconductor body and surrounded by the base area.

The base region is the surface region adjacent to the peripheral surface 11 of the collector region and extending from said surface in the intermediate layer 21 which acts as an emitter.

Originally, the current amplification factor β of the transistor structure used in this manner is smaller than that of a conventional non-inverting transistor.

However, in many circuits, the low current amplification factor β does not pose any problem, and by using a common emitter region in conjunction with a current injection part, an integrated circuit with a very simple structure can be obtained. In particular, no space is required for isolation regions for electrically isolating the transistors, and furthermore the manufacture of the integrated circuit is significantly simplified.

Furthermore, a method for increasing the current amplification factor β of the inversion transistor structure will be described below.

As already mentioned, flip-flops can be connected to a single power supply 1
7 to make it fully operational.

This makes it particularly important that, during operation, all voltages in the circuit are
can be within the range given by the potential difference supplied to the connections 15 and 16.

This potential difference is p −n between the injection layer 20 and the intermediate layer 21
The forward direction is between the ends of the junction 18.

The distance between the injection layer 20 and the region 5 is actually about the diffusion length of the minority charge carriers in the intermediate layer, but if this distance is not too large, the carriers are injected into the intermediate layer and directed towards it. charge carriers, which are minority charge carriers, into the injection layer 2
It can be captured by a region of the same conductivity type as 0, for example region 5.

For example, the bond 19 between the region 5 and the intermediate layer 21 may be
By connecting via the conductive strip 14 to a suitable potential point, a current can flow from the injection layer 20 to the region 5 to be biased when biasing in the reverse direction.

In this case it is necessary to use a second voltage source for this circuit.

As is known, it is not necessary to reverse bias the rectifying junction to trap charge carriers.

Due to the trapped charge carriers, a potential change occurs in region (5).

As a result, a forward voltage is also set up across junction 19.

When the forward voltage is sufficiently high, injection of charge carriers through junction 19 takes place.

As a result, due to the trapping of charge carriers, current flows through the junction in a direction opposite to the direction of current flowing across said junction.

The potential of region 5 is self-adjusted and, if desired, a current is passed through the connection in region 5 to increase the difference between the two currents to the base bias current required to operate transistors 33, 5.21. Make equal.

In such a steady state, the potential of region 5 is generally adjusted between the potentials of connections 15 and 16.

If the junction 19 is operated in the opposite direction, a three-layer transistor 33, 5.21 is used, with region 33 as emitter, region 5 as base and layer 21 as collector, to provide all or part of the base bias current. is supplied by the current injection section.

Also, when setting up a forward voltage across junction 19, i.e., junction 40 between regions 33 and 5.
If is sufficiently forward biased, layer 21 can be used as the collector of a three-layer transistor 33, 5.21.

However, it is also important that when forward biasing the junction 19, the intermediate layer 21 acts in this example as the emitter of the transistor 21, 5.33.

I will explain this in detail. Lateral force direction current injection part 20, 21.5
In this reference example, the common body 12 is an n-type semiconductor body, and the semiconductor body constitutes the intermediate layer of the current injection part. Highly resistive n-type surface layer 2 provided on top
1b.

The entire semiconductor region of the circuit element and current injection part is covered with the substrate 21a.
It is made to adjoin the surface 11 of the surface layer 21b which is further apart.

The implantation layer 20 and the base regions 1 to 10 are formed at the same time, and the doping concentration of both is in this case the same as that of the p-type surface region in the epitaxial surface layer 2ib.

This relatively simple fabrication technique makes the doping concentrations and slopes near p-n junctions 18 and 19 approximately equal.

This equivalence of the two junctions 18 and 19 makes it unnecessary to use the intermediate layer 21 as the emitter of the n-p-n transistor 21.5.33.

In fact, since the junction 18 constitutes the injection junction of the current injection part, the forward current in the junction must be composed of holes as much as possible in view of its efficiency.

For the same reason, the forward current flowing through junction 19 as the emitter-base junction of the transistor must be made up of electrons as much as possible.

In other words, in order to make the epitaxial layer 21b an intermediate layer of the current injection part, it is necessary to make the impurity doping concentration low, and it is desirable that the epitaxial layer serving as the emitter of the transistor has a high impurity doping concentration.

In order to use the intermediate layer 21 of the current injection part as the emitter of a transistor, the ratio of electron current to hole current in the injection junction is determined by the doping concentration on either side of said junction and the voltage across this junction. We take advantage of the fact that it not only depends on the minority charge carriers provided, but can also be determined by the gradient of said minority charge carrier concentration.

These concentration gradients depend in particular on the capture junction, such as the base-collector junction 40, and on the distance between the junction 40 and the injection junction 19.

In the vicinity of the trapping junction 40, the concentration of minority charge carriers in the base region 5 due to the trapping effect of the junction 40 does not depend much on the bias voltage across the junction.

If the distance between junctions 40 and 19 is smaller than one or several diffusion lengths of minority charge carriers in base region 5,
The trapping effect of junction 40 increases the gradient of minority charge carrier concentration.

This effect can also be explained as shortening the effective diffusion length of minority charge carriers in the base region 5.

As a result, in this case the voltage across junction 40 relative to junction 19 and/or the distance between junctions 19 and 40 relative to junctions 18 and 19 may be selected to provide a positive majority of the forward current across junction 18. The layer 21 as an emitter can be configured with a hole, and conducts most of the forward current across the junction 19 through the layer 21 as an emitter.
Although the impurity doping concentration is relatively low, it can be composed of electrons.

The shortened effective diffusion length of electrons in the base region 5 needs to be shorter than the effective diffusion length of holes in the intermediate layer 21.

As mentioned above, this flip-flop is constructed with a number of NOR gates consisting of a number of transistors with emitter-collector paths connected in parallel.

Figure 4 shows two or more gate transistors T401T41
. . . shows such a NOR gate.

Input terminals A, B, etc. of gate transistor T40 t T41... are connected to transistor T40
j T41 .

The current injection part is a current source ■4o. 41 and 4□, and their polarities are shown between the base and emitter, respectively.

If neither transistors T4o nor T41 are conducting, that is, both input terminals Ak and B are at ground potential or at a voltage lower than the respective internal base input limit voltage of transistors T40 and T4□. When supplied to the emitter, only transistor T4□ conducts current (this is based on the current source ■4□ operating in the forward direction).

The currents of current sources I40 and ■4□ flow to the ground, and
Since transistor T4□ is conducting, the voltage at its collector (point D) drops to approximately ground potential.

If the voltage at one or more input terminals A and B exceeds the base input limit voltage, the current of current source I42 flows through the conducting input transistor and transistor T4□
There is almost no current left in the base of the transistor, and this small current is used to energize the transistor.

In this way, the current source I42 is formed by the current injection part,
A current is reliably supplied to the main current path of the transistors T40 + T41, and the base-emitter junction of the transistor T4□ constitutes the load impedance of the transistor.

In many circuits, two gate transistors T1
The collector-emitter paths (fine) of more transistors than transistor T2 are connected between the points C and the top and the ground, and the vane-emitter paths of several transistors are connected between said points as well as transistor T42.

Each of points A and B is connected, for example, to an output terminal C of a similar gate circuit in the previous stage, and the output terminal C of the illustrated gate circuit is connected to an input terminal of a similar gate circuit in the subsequent stage.

The fan-out is limited by the collector-base current amplification factor β of the transistor used.

As is clear from the above, in addition to a conducting transistor whose emitter-base voltage is above a threshold voltage, such a circuit results in a non-conducting transistor whose emitter-base path is essentially shorted.

That is, in the integrated circuit shown in FIG. 1, a parasitic transistor that operates between each base region, for example between base regions 4 and 5, can be easily formed if the distance between the regions is not very large. Can be done.

In this connection, a surface region 21C belonging to the n-type intermediate layer 21 which is more highly doped than the base regions 4 and 5 extends between the two base regions 4 and 5 to be biased.

To save space, the highly doped surface region 21C is directly adjacent to the base region to be electrically isolated.

However, if the n+ region 21C is also provided at a certain distance from the base region to be separated, stray transistors, if any, can be effectively suppressed.

In this example, the surface region 21C is not provided only between the base regions to be separated, but the entirety of each base region 1 to 10 is provided at the surface 11 with a portion of the implanted layer 20 and an impurity doping concentration. is substantially surrounded by the combination waste comprising the higher area 21C.

Three sides of each base region are surrounded by a U-shaped region 21C.

As is apparent in the cross-sectional view shown in FIG.
Provided between the joints 44.

For clarity of illustration, this junction 44 is not shown in FIG. This makes each base region 1 to 10 an n+-n junction 4 insofar as it is adjacent to n-type material.
4 and can extend into, or at least abut, a relatively small n-type region that is almost completely surrounded by the n+-n junction 45 between the substrate 21a and the epitaxial layer 21b.

These n+-n junctions constitute a barrier to holes in the epitaxial layer 2Ib, and as a result, holes injected into the portion surrounded by the injection layer 20 or the base region 5 are transferred from the junctions 18 and 19. Spaced n-type intermediate layer 2
It does not easily flow into part 1.

Similarly to decreasing the effective diffusion length of electrons in the base region, by increasing the effective diffusion length of holes in the portion of epitaxial layer 21b adjacent to base region 5, ie on the other side of junction 19, 3 Layer transistors 21, 5, 3
The current amplification factor β of No. 3 can be increased.

In this connection, the n-type region 21 adjacent to the base region 5
It is preferable to surround b as much as possible.

Furthermore, the region 21b is made as small as possible to prevent minority charge carriers from being lost due to recombination.

Preferably, the base region button injection layer 20 extends to the n-substrate 21a, at least up to ten layers.

This has the advantage that the implantation of the implantation layer 20 can take place along the surface 11 primarily in the transverse force direction.

When the thickness of the region is made smaller than the surface layer 21b, it is preferable that the n+ surface region 21C extends up to or into the substrate 21a.

Although the small holes in the enclosure cause relatively small negative effects, n tens of surface areas of surface 11 are directly adjacent to injection layer 20.

Providing holes on either side of the injection layer, as shown in FIG. 5, relates to the method of fabricating the integrated circuit rather than to the effect of enclosing.

In connection with the manufacturing method, losses due to surface recombination become a more or less important issue.

If the characteristics of the semiconductor surface 11 and the junction between the surface and the insulating layer 13 are such that the surface recombination is relatively thick, for example, the uniformly doped region to be biased may be epitaxially The current amplification factor of the transistor is increased by forming a portion of the layer and forming, in at least a portion of the base region adjacent to the semiconductor surface to be biased, an impurity doping concentration gradient that increases in the direction from the surface toward the semiconductor surface. can be increased.

The resulting drift field holds the minority carriers away from the surface.

If the surface region 21C does not directly adjoin the base region, but the region 21b between them reaches the surface, a corresponding concentration gradient in the layer of the region 21b adjacent to the semiconductor surface is required for the same reason. .

A gradient in region 2Ib can be easily obtained, for example, by simultaneously providing a common diffusion collector region 33.

The injection layer 20 is a ribbon-like surface area juxtaposed along either side of this area with several base areas 1 to 10 separated from each other and biased.

In this way, a large number of regions to be biased can be supplied with bias current by the same injection layer.

The series resistance of such an elongated injection layer 20 can be reduced using continuous or interrupted conductive strips 46.

FIG. 6 is a cross-sectional view of a second reference example of an integrated circuit using a current injection section.

The common body 60 is made up of five continuous layers 61, 62a, 63, 62.
b, 64, and these layers are separated from each other by rectifying junctions 65.66.67 and 68.

As described for the previous embodiment, by injecting charge carriers from the injection layer 61, the third layer 63 of the current injection part
The potential is such that the junction 66 and the junction 67 are in the forward direction.

That is, charge carriers can be injected from the second or intermediate layer 62a into the third layer 63 and captured by the fourth layer 65b.

Similarly, when the fifth layer 64 is provided, the third layer 6
Charge carriers are injected from the fourth layer 62b into the fourth layer 62b and are captured by the fourth layer 62b via a junction 68 adjacent to and bounding the fifth layer 64.

In this example, the fifth layer 64 of the current injection part also constitutes the base region to be biased of the bipolar transistor, which is stronger than the layers 69, 64 and 70, for example.

The current injectors and said layers of the transistor can be provided, for example, in a thin semiconductor layer provided on an insulating substrate, and the five layers of current injectors can, for example, extend through the thickness of said semiconductor layer. .

In the illustrated example, the intermediate layer 62a and the fourth layer 62b
constitute continuous areas of the same conductivity type within the semiconductor body.

In FIG. 6, the remaining portions 62C to 6 of said area
It is shown as 2f.

At least a large part of the area belongs to an epitaxial layer 62 of one conductivity type provided on a semiconductor substrate 71 of a reflective conductivity type, and the area is hereinafter referred to as an island, and this island is made to belong to an epitaxial layer 62 of one conductivity type provided on a semiconductor substrate 71 of a reflective conductivity type. to separate it from the rest of epitaxial layer 62.

A buried layer 62f of one conductivity type having a concentration higher than the original impurity doping concentration of the epitaxial layer 62 is provided on the island.

This buried layer is provided on and near the boundary between the substrate and the evixial layer.

Layers 61, 63 and 64 of the current injection portion are surface regions reaching from the surface 73 to the buried layer 62.

As a result, the diffusion voltage of said portion of the p-n junction between insulating layer 62 and third layer 63 and of the island substantially parallel to surface 73 is made greater than the voltage of said portions 65, 66 and 67 of said junction.

In this connection, layers 61 and 63 provide charge carrier injection in a lateral direction approximately parallel to surface 73.

Furthermore, the layers 62a and 62b in which the injection takes place are made very small so that, as mentioned above, only relatively few injected charge carriers are lost within the islands.

Furthermore, in this example, the combined portion of the current injection portion and the circuit element is surrounded as much as possible to limit the outflow of minority charge carriers in the lateral direction.

A low resistance region 62e provided within the island is adjacent to the injection layer.

Region 62e is used to limit charge carrier injection in the lateral direction of the injection layer on that side of the injection layer remote from the region to be biased by increasing the diffusion voltage.

Further, the region 62e is used as a contact region for the connection portion 74 that connects one electrode of the external power source 75 to the intermediate layer 62a of the current injection portion.

The desired enclosure of the base region 64 to be biased is provided in this example by an insulating layer 62 provided partially within the semiconductor body 60 and extending from the surface 73 into the semiconductor layer 62 in which the region to be biased is provided. This is obtained using layer 76.

In this example, insulating layer 76 only extends over a portion of the thickness of layer 62.

This buried insulating layer 76 surrounds most of the base region 64, and makes this layer 76 as close as possible to the third layer or injection layer 61 or region 62e.

Therefore, a bias current can be supplied simultaneously to the third layer 63 and/or the injection layer 61 and only to a few juxtaposed regions or base regions 64 to be biased.

The injection layer 61 is provided with the other electrode connection portion 7T of the power source 75.

Furthermore, a device is provided for controlling or adjusting the bias current to be supplied to the base region 64 which is to be biased to the illustrated current injection.

Such control can be achieved using, for example, insulated electrodes to be provided on the insulating layer 78 above the intermediate layer 62a and/or the fourth layer 62b.

In this case, the potential of the electrode controls the recombination of minority charge carriers at the surface of the layer.

In this example, another bias current control scheme is used.

That is, control is performed by taking back the current from the third layer 63 of the current injection section.

For this purpose, a conductive connection portion 79 is provided in this third layer 63.

For example, if the third layer is shorted to the fourth layer 62b or intermediate layer 62a through the connection, the voltage across junctions 66 and 67 is so small that although the third layer 63 captures it, there is no Or almost no injection is performed from the third layer.

Therefore, no bias current is supplied to the base region 64.

It is always desirable that the current injector not supply any bias current to one or more circuit elements of the circuit.

In this case, the junction 66 and/or the junction 67 can simply be shorted to the electrically conductive layer at the surface 73.

However, the bias current for the base region 64, e.g.
If an electronic switch is provided between connections 79 and 74, it may be temporarily turned on or off.

Such a switch is shown diagrammatically in FIG. 6 by a transistor 80, the base of which can be controlled, for example, by other parts of the circuit and easily integrated into the semiconductor body 60.

Also, of course, only a portion of the current that flows through the current injection part and can be obtained as a bias current is transferred to the transistor 8.
It can be recovered after passing through 0.

The island provided with the current injection layer can form an emitter region common to a number of transistors.

In this case, the illustrated transistor is a multi-collector transistor having two collectors 69 and 70.

The injection layer 61 is, for example, in the shape of a nopon, with several base regions not visible in the cross-sectional view juxtaposed along the ribbon-like surface region.

For example, a triple-layer current injection part can be formed with one or more of the base regions, the injection layer 61, and an intermediate layer formed by an island.

Both layers are common.

One or more other base regions, including region 64, form part of a five-layer current injection region such that layer 63 extends between common injection layer 61 and the associated base region.

Although the layer 63 is common to the base regions to be biased, it can also be constructed with separate regions separated from each other, so that the bias current can be controlled for each individual base region.

The integrated circuit is provided with other islands in addition to the illustrated islands provided with current injection and one or more transistors.

The islands are insulated from each other and circuit elements are similarly provided inside them.

Additionally, circuit elements can be provided within one or more islands and bias currents can be supplied to these circuit elements in a conventional manner without the use of current injectors.

An important advantage of the gate circuit described above is that it can be operated with very low currents and voltages and therefore with low power consumption.

However, since the logic signal voltages and/or signal currents are small, it is necessary to choose the signal values when combining large scale assemblies with different logic circuits, for example TTL or MO8T circuits.

This can be done particularly easily using inverters or transistors connected as emitter followers.

For example, the transistor T3□ in FIG. 3 is used as an external inverter, and its collector is connected to a relatively high potential point via, for example, a resistor.

The voltage fluctuation at the output terminal Q is made significantly larger than at any output terminal of the flip-flop, for example the collector of transistor T34.

A transistor T37 consisting of layers 21, 10 and 37 can be used, respectively, with surface region 37 as emitter and layer 21 as collector.

In that case, the transistor forms an emitter follower.

The emitter region 37 is led out to a relatively high negative potential point, for example via a resistor.

In FIG. 7, the emitter follower used for the output terminal of the circuit is shown as a transistor T70 connected to the output terminal U.

Let the transistor T,1 be, for example, a transistor of a gate circuit or an additional inverter depending on the output signal.

In this example, a low value logic signal is provided to the base of the output transistor via the emitter-collector path of complementary transistor T72.

As a result, higher voltages can be tolerated and the risk of destruction is therefore reduced.

Another method is to derive the output signal from the collector 99 of transistor T72 and omit transistor Too.

FIG. 8 shows a state for explaining a method of incorporating the circuit shown in FIG. 7 into an integrated circuit.

In the same figure, a common semiconductor body consists of a low resistance n-type semiconductor substrate 90 and a high resistance n-type surface layer 91, within which a number of p-type surface regions are provided, which are connected to the substrate 9.
0 and the surface layer 91.

The semiconductor body includes a p-type injection layer 92, an n-type intermediate layer formed by a substrate 90 and a surface layer 91, and two p-type head regions to be biased, namely the transistor T? 2 emitter region 93 and base region 9 of transistor T71
A current injection mode consisting of 4 is formed.

In FIG. 7, this current injection part is connected to two current sources I7□
and I72.

r, by means of the mold body, at the same time the emitter of transistor T71, the base of transistor T7□ and the transistor T,.

form a collector. Further, the transistor T71+ is connected to the transistor T7□ via a connecting portion 95 on its base region 94 and a conductive strip 98 provided on the insulating layer 97.
An n-type collector region 96 is provided which connects to the emitter of.

The collector of transistor T72 is formed by a p-type head 99 which also forms the base of transistor T7G.

Further, the transistor T''yo is provided with an n-type emitter region 100 connected to the output terminal U.

Highly doped n-type region 101 is placed adjacent to p-type regions 94 and 99 to limit the charge loss.

Injection layer 92 and intermediate layer 90.91 are connected to power supply 102.

The base bias current is supplied to the transistor T71 from the current injection part, and the transistor T71 is supplied via the semiconductor body.
The main or supply current is supplied to the emitter-collector path of the transistor T71 or via the strip 98 to the emitter-collector path of the transistor T71.

When transistor T71 becomes conductive, transistor T72 becomes conductive.
and T7o becomes non-conductive.

The reason is that the base current cannot be obtained while the transistor T7□ is non-conducting.

Therefore, the voltage at terminal U becomes approximately equal to -■.

When the transistor T71 becomes non-conductive, current flows from the current source ■7□ through the transistor T7□ to the transistor T7o as its base current.

This causes the transistor Too to conduct and the voltage at the terminal U to be approximately O or at least lower than the voltage -■.

FIG. 9 is a cross-sectional view showing an embodiment of an integrated circuit having complementary transistors.

In this embodiment of the integrated circuit according to the invention, the semiconductor body is intersected by a substrate 105 and an epitaxial layer 106.

This epitaxial layer includes a surface region 10 of opposite conductivity type.
7 is provided, and this region is used as the base region of the vertical transistor and the emitter of the horizontal complementary transistor.

The vertical transistor is provided with an emitter 105, 106, a base 107 and a collector 108.

In this case, the latter comprises a metal-containing layer, for example an aluminum layer, which is provided on the base region and forms a Schottky junction therewith.

As is generally known, it is not always necessary to use a layer of pure metal to form a Schottky junction; instead, it is not necessary to use a layer of pure metal to form a Schottky junction.
It is also possible to use metal 5 ilicides).

In connection with the formation of the Schottky junction, the doping concentration in the base region is in this case lower than 10<17> to 10<18> atoms/cm3.

The Schottky junction 109 is assumed to be the collector base junction of the transistor.

The lateral transistor has an emitter region 107. A base region 105° 106 and a collector region 110 are provided.

Regions 107 and 110 are the regions to be biased and together with the intermediate layer formed by semiconductor bodies 105, 106 and injection layer 111 form a triple layer current injection.

Both layers are connected to a bias current supply power source 112.

The illustrated connection 113 is provided between collectors 108 and 110, and a connection is provided in region 107.

FIG. 10 shows an equivalent circuit of the integrated circuit, in which the vertical transistors 106, 107° 108 are T9
Denoted in degrees, lateral transistor 10T.

106.110 is indicated by T91.

In this case, the current injection part is connected to two current sources ■9° and I9°.
Indicated by 1.

Current supply source 112 causes regions 111 and 105 .
The junction between 106 is now forward biased;
Region 111 will therefore supply charge carriers into regions 105, 106 by injection.

This charge carrier injection increases the bias current to the base region 1
The base region 107 (1) $i position changes based on the current reception, and at least the emitter-base coupling of the transistor becomes forward biased.

From the reference examples described so far, and the structure shown in FIG.
It is also clear that it may form part of a larger integrated circuit containing resistors and other elements.

All or some of these other transistors may be capable of receiving and taking bias current through separate current injection structures.

These current injection parts may have 3, 4.5 or more layers, and one, two or more of these layers may be a shared current injection layer.

In the integrated circuit structure of FIG. 6, for example, the semiconductor electrode region 64, which is the base region of the transistors 62f, 64.69, has current injection portions 61.62a, 63 serving as bias current sources.

A part of the three-layer structure 63, 62b, 64 is formed as a third layer, and this three-layer structure is further formed as a first layer.
It has an injection layer 63 of a conductivity type, which is located outside the range of the transistors 62f, 64, 69 and separated from the one electrode region 64 by an intermediate layer 62b of a second conductivity type. .

This three-layer structure 63, 62b, 64 further includes an injection layer 63.
and an intermediate layer 62b, and a second p-n junction 68 between the intermediate layer 62b and one electrode region 64.

Furthermore, in the reference example of FIG. 6, the first p-n junction 67
means for forward biasing the electrode region 64 to supply charge carriers to one electrode region 64? 4,77.61゜62a,
63 and means 74, 77. 61, 62a for biasing this first p-n junction 67.

63 comprises at least one further layer 61 of the first conductivity type, this further layer being the current injection part 61, 62a.

63.62b, forming part of 64 and transistors 62f, 64.69 and three-layer structure 63.62b
, 64.

This another layer 61 has a second conductivity type layer 62a adjacent to the injection layer 63 and a current injection portion 61, 623°63.62.
b, 64, forming a third p-n junction 65.

The aforementioned means 74, 77.61, 62a63 further include a third
By biasing the p-n junction 65 in the forward direction, the injection layer 63
Means 74, 77 are provided for supplying charge carriers.

Note that the above-mentioned injection layer 63 is connected to the transistors 62f and 64.6.
9 and therefore does not belong to the actual structure of this transistor, and the aforementioned another layer 61 is located outside the range of transistors 62f, 64.69 and the three-layer structure 63.62b,
Since it is located outside the range of 64, this other layer 61 does not belong to this three-layer structure let alone an actual transistor.

In the embodiment of FIGS. 9 and 10, a three-layer structure is formed by layer 111, layers 105, 106 and layer 107 and by layer 111, layers 105, 106 and layer 110.

and means for forward biasing the rectifying junction between layer 111 and layer 105.106 are schematically drawn on layer 111 and layer 105.106 and connected to the current source 112 as shown. wire means (e.g., conductive wire) that is designed to

In operation, the current injector supplies a current to the base of transistor T9o (shown in FIG. 10), which causes transistor T9o to conduct.

The relationship between the present invention and the embodiments shown in FIGS. 9 and 10 is clarified as follows.

That is, it comprises a common body on one side of which there is at least one transistor, said transistor comprising a base region 107 of a first conductivity type, said base region being said -
side adjacent to the surface of said common body and said transistor 105.106.107.

The base region 107 is in rectifying contact with the emitters 105, 106 and the collector 108 of 108, and the base region 107 has a three-layer structure 111, 105 of a current injection part serving as a bias current source.
, 106, 107 are formed as a third layer, and the three-layer structure further has an injection layer 111 as a first layer, and this injection layer 111 is a second conductivity type adjacent to this layer. The base region 1 by the second layer 105.106
07 and the injection layer 111 and the second layer 10
5.106, the injection layer 111 is separated from all the transistors, and the second layer 105.106 of the three-layer structure is connected to the injection layer 111 and the It exists between the base region 107 and shares a common semiconductor region with the emitters 105 and 106, and further biases the rectifying junction of the three-layer structure in the forward direction to provide a charge cannon to the base region 107. is supplied to the base region 107 and the emitter 1.
05.106, said base region 107 forming a Schottky junction with said base region and having a metal or metal-containing a region 108 constituted by a layer on one side of the common body, said region belonging to the collector of the transistor, and the Schottky junction forming the rectifier between the collector 108 and the base region 107; forming contact.

As a result, the current supplied from the current injection part to the collector region of transistor T91 via the semiconductor body is mainly
From the current injection part to the connection part 113 and the transistor T9o
This causes the collector voltage of the transistor T91 to drop below the voltage at the electrode of the transistor T9°, so that current begins to flow through the lateral transistor T91.

This current is extracted from the bias current supplied to the base region 107 from the current injection section.

Finally, only one of the bias currents supplied to the region 107 is used as the base current of the transistor T,
It will be in a state where it flows through o.

That is, the amount of current is so small as to operate the transistor within a linear operating range.

Such biasing prevents storage from occurring in excess of just what is necessary to operate the transistor in its strongly conductive state.

In this embodiment, the collector-base junction of the transistor is also forward biased at the same time.

However, the direction of this bias is determined by the circuit connections; for example, the collector may be connected to a suitable voltage source via a load device, in which case the collector-base junction may be biased in the opposite direction.

Further, another linear circuit can be easily formed.

For example, FIG. 11 shows a linear amplifier shown as an equivalent circuit.

This amplifier has three transistors T110 + T't
tt and T1.2 are provided.

'The collector C of the first transistor is connected to the base b of the second transistor, and the collector of the second transistor is connected to the third transistor.
Connect to the base of the transistor.

Further, the collector of the third transistor is connected to the base of the first transistor through a circuit including a loudspeaker or receiver and a microphone M through which a direct current flows.

A capacitor C is used to control the AC negative feedback coupling.

In order to perform the DC negative feedback coupling via the DC transmission circuit, the current required for each transistor explained with reference to FIGS. 9 and 10 can be obtained again (current '110).
The remaining currents in +Ill+ and T1.2 flow through the collector-emitter circuits of the previous transistors in the cascade), each of which can be adjusted within its linear operating range.

In this way, a very simple amplifier can be obtained, for example for use in hearing aids.

In an integrated circuit, transistors Tll0+T10 .
and the base regions of T1,2 are juxtaposed along the ribbon injection layer in the same manner as described with respect to FIG.

Another method is to use a vertical current injector instead of a lateral current injector.

The principle of such a configuration is shown in FIG.

In the same figure, for example, one of the circuits of the integrated circuit is
A semiconductor layer 180, which is an n-type layer, for example, is provided.

An injection contact as an n-type layer 181 is provided on one side of said layer.

A power supply 182 is connected between this layer 180 and injection contact 181 to forward bias the rectifying junction therebetween.

This makes it possible for the charge carriers injected into layer 180, in this case the charge carrier, to form an n-type on the other side of layer 180 opposite to the contacts, if this layer is not thicker than the diffusion length, for example. Layer 183 is reached.

Therefore, the potential of layer 183 is positive with respect to n-type layer 180.

In this way, an energy source is obtained on the other side of the layer 180,
This supplies current and transfers it to, for example, circuit element 1
It can be connected to one or more circuit elements such as 84.

This can be obtained via conductive wires 185 or internal connections provided in the semiconductor body.

Furthermore, if a connection is provided between the circuit element 184 and the layer 180, the current of the current injection flows through the circuit element, for example as a supply current.

Again, such connections can be made via conductive wires or, for example, within layer 180 and forming part of circuit element 184.

In this case, the circuit element is a transistor with an emitter formed by layer 180.

Furthermore, the transistor is provided with a base region 186 and a collector region 187.

Also, layer 180 can be a common emitter region for a number of transistors in a common emitter configuration.

A second injection contact 188, shown in dashed lines in the figure, can be provided on the side of the semiconductor layer opposite the base region 186 to provide a second current injection 188° 180.186 for supplying the required bias current.

In this way, the entire bias current of I.Landisk is supplied via the current injection section using the same external power supply 182.

In this case, when a circuit element is provided, the current supply wiring is not required on one side surface 7 of the semiconductor layer.

Further, the semiconductor layer 180 is grounded, and a bias current is supplied to the circuit elements through the ground layer 180.

Next, the principle shown in FIG. 12 will be explained in detail with reference to 2 to 3 reference examples.

As mentioned above, a vertical current injection section is used in the circuit integrated device shown in FIG.

In this case, the integrated circuit has the form shown in FIG.

Also, in this case, the transistors are connected to the common semiconductor body 121
juxtaposed on one side 120 of.

Conductive strips 122, 123 define the semiconductor region of each transistor.
and 124 patterns (this connects).

This pattern is provided with an electrical signal input terminal or strip 122 through which the input signal originating from the microphone M is applied to the base of the first transistor.

The pattern is further provided with an output terminal or strip 124 through which the amplified output signal of the third transistor is supplied to the loudspeaker.

A strip 123 connects the collector region 126 to the base region 125 of the next transistor.

Furthermore, a common emitter region formed by an epitaxial layer 127 of one conductivity type is provided on the opposite conductivity type substrate 128 of the transistor.

The semiconductor body 1 21 is provided with a current injection part, the injection layer of which is constituted by a substrate 128, which is adjacent to the surface 129 of the semiconductor body opposite to the side surface 120, and further includes two rectifying junctions 130 and 131 (from which A layer 125 separate from the injection layer 128 and the power connection of the power supply 133 connected thereto.
extends along one side 120 opposite the injection layer 128 , and a layer 125 disposed on the opposite side allows a junction 13 bordering the layer 127 from an adjacent layer 127 of the current injection portion to be
It captures charge carriers through 1 and therefore receives a current as 7 as a bias current of the base of the transistor and the collector of the preceding transistor connected thereto.

A power supply 1 is applied to an epitaxial layer 127 that simultaneously forms the common emitter region of the transistor and the intermediate layer of the current injection part.
A power connection 134 to the other electrode of 38 is provided.

In this example, the intermediate layer 127 is configured as a reference potential plane of the amplifier circuit.

A bias current is supplied using a current injector by a reference plane that is supplied with a reference potential, for example, a ground potential.
All of the regions 125 on the side 120 are separated from the injection layer 128 on the opposite side 129.

Similarly, electrical insulation is provided to supply the required bias current directly to the relevant area to be biased, typically via a ground layer 127.

The intermediate layer 127 is provided with a highly doped sub-region of the same conductivity type and consisting of a buried layer 135 and a rising wall portion 136 extending from the surface 120 to the buried layer 135.

Further, the entire or a portion of this rising wall portion 136 may be formed of a buried insulating layer.

This sub-region, in particular by the wall 136, juxtaposes the base region 12.
This suppresses the parasitic transistor action between 5 and 5.

Further, in this case, the portion 136 is used to form a boundary with the isolated base region 125.

That is, each of these base regions is constituted by portions of epitaxial layer 137 of opposite conductivity type separated by portions 136 provided on epitaxial layer 127 of one conductivity type.

In addition, the portion 136 together with the buried layer 135 constitutes an enclosure of the biased power region 125, so that in the highly resistive region of the intermediate layer 127, the minority implanted from said region 125 into this intermediate layer 127 is The charge carriers can be limited as much as possible and the effective wavelength of said charge carriers can be increased as desired.

In this manner, sub-regions 135 and 136 isolate each of the transistors from each other and from substrate 128.

Although it is not necessary, small holes are formed in the separation sub-regions.
For example, it is provided in the range of portions 130a and 130b of joint 130.

These portions 130a and 130b of junction 130 are provided with a lower diffusion voltage than the remaining portions of junction 130, and injection layer 1
The injection of charge carriers from 28 into the intermediate layer 127 is carried out via said portions 130a and 130b, and the injection in the opposite direction from the intermediate layer 129 into the injection layer 128 is performed as follows:
Since the intermediate layer in the above range has a relatively low doping concentration, it is relatively small.

The ratio between the bias currents provided to each base region 125 is affected by the extent of portions 130a and 130b of junction 130.

In this example, the surface area of portion 130a is
Since the current source Il! in FIG. 11 is larger than b! .

Although current is reliably supplied to the output transistor T'tt□, current sources ■111 and ■,
12.

Automatic gain adjustment, if desired, can be easily obtained, for example, using two collectors as in the transistor shown in FIG.

If one of these collectors is grounded through an adjustable resistor (for example, the internal resistance of a transistor), the signal current to the other collector becomes dependent on said resistor.
Automatic adjustment can be easily performed.

In the reference example shown in FIGS. 14 and 15, the injection layer is a lattice-like surface region 140, which is surrounded by a lattice surface region 1401 of one conductivity type on a surface 141 adjacent to a surface 141 of a semiconductor body 142. A region 144 to be biased is provided in a portion 143a of the region 143 of the opposite conductivity type, whereby the three-layer transistors 143,1
It constitutes a base area of 44°145.

The region 143 constituting the intermediate layer of the current injection section is subdivided into a low resistance substrate and a high resistance surface layer.

This subdivision is performed using a grid-like injection layer 140 extending from substrate 141 to or into substrate 143b.

As shown, transistors or other circuit elements may also be provided within the highly resistive portions 143a and 143C.

Furthermore, it is also possible to have several circuit elements juxtaposed in one or more sections, with each section having a different size.

The use of grid-like surface regions 140 as injection layers for current injection has the advantage that the series resistance of such regions can be lowered.

Similarly, deeper penetration and/or higher impurity doping concentrations may be provided for the implant layer than for the base region 144.

This actually limits the maximum allowable doping concentration of base region 144.

This is particularly because within said region it is generally necessary to provide a region 145 of the opposite conductivity type.

A DC power supply 146 is connected between the injection layer 140 and the intermediate layer 143 of the current injection section.

Therefore, if desired, such a power supply can be shunted with capacitor 147 to short AC voltage connections 148 and 149.

In another reference example of an integrated circuit, one or more three-layer transistors 150.1, as shown in FIGS.
51.152a=b is provided.

In addition to the n-type emitter or collector region 150, an n-type region 153 extends into, for example, a p-type base region 151, and this n-type region 153 connects other p-type surface regions 15.
Surround 4.

The regions 153 and 154 constitute an intermediate layer and an injection layer of the current injection section, respectively.

As shown by the broken line in FIG. 16, a hole is provided in the insulating layer 158 to expose the semiconductor surface, and the area 150, 15 is exposed through the hole.
1, 153 and 154 are connected to conductive strips for electrical connections.

Connecting parts 155 and 156 are provided in the injection layer 154 and the intermediate layer 153 of the current injection part, respectively, so that the 17th
Connect to power supply 157 as shown in the figure.

This reference example is particularly suitable when it is necessary to supply bias current to one or several circuit elements of a circuit using a current injection section.

Further, although the intermediate layer 153 is directly connected to the regions 152a and 152b of the transistor, for example, this is connected to the intermediate layer 1 on the semiconductor surface.
53' extending to or within the low resistance region 152a.

As a result, space can be saved even though connections 156 can be additionally provided on the underside of substrate 152b, if desired.

In the next reference example, circuit elements are provided on the surface 167 of the common semiconductor body.

This semiconductor body is composed of a low resistance n-type substrate 160 and an n-type epitaxial layer 16 with a low impurity doping concentration formed thereon.
1 (Fig. 18).

A number of mutually insulated circuit elements are formed in the epitaxial layer using p-type head regions 162 by methods known in semiconductor technology.

That is, for convenience of illustration, only one of the elements, namely npn transistors 163, 164, 165, is shown in the figure.

The n-type body 160 also constitutes a ground plane for the integrated circuit.
, 161 is an injection layer of a current injection section which also includes a p-type intermediate layer 166 and an n-type third layer 168 adjacent to the surface 167.

A power source 17 is connected to the injection layers 160 and 161 and the intermediate layer 166.
Connecting portions 169 and 170 for connecting 1 are provided, respectively.

Further, the injection layer 160° 161 is placed on one side 16 of the semiconductor body.
7 and adjacent to the surface 172 on the opposite side.

Also, two p-n junctions 173 and 17 are formed from the injection layer.
A third layer 168 of current injection portions separated by 4 is disposed on the surface 167 opposite the injection layer 160° 161.

A third layer 168 placed on the opposite side of the current injection traps charge carriers from the intermediate layer 166 adjacent to the current injection via junction 173 and thus transfers them via conductive strips 175 to the opposite side of the current injection. The transistors 163, 164, 165 connected to the arranged layer 168 receive a current which acts as a bias current for the emitter 163 of the transistor 165.

Via the conductive strips 175, it is also possible to simply connect several regions in which circuit elements are to be biased to the layer 168 arranged on the same opposite side of the electrical injection.

Via the connection 176, an electrical signal can be supplied to or from the base 164 of the transistor.

It is also possible to connect the collector 165 to a positive voltage +■ via a connection 177, for example an impedance 178.

The reference example is particularly suitable, for example, when it is necessary to supply a bias current to one or several circuit elements located in the center of a large-scale integrated circuit.

The required bias current is transferred from the ground plane of the circuit to the surface by a current injector which occupies a slight extra area and which is connected via a pattern of conductive strips to the adjacent area to be biased of the circuit element in question. can be applied locally using

Although no resistance is required for this supply of bias current, nevertheless no fixed potential is applied to the region to be biased, so that said region is e.g.
Flow an electrical signal current or signal voltage.

FIG. 19 shows a circuit diagram of a trigger circuit consisting of a group of trigger circuits, in which the group of trigger circuits is constructed according to a matrix pattern in the same manner as the storage circuit is constructed at the same time.

Transistor Tl0I j...T1o7 in the trigger circuit
are provided, and their emitters are all connected to ground potential.

The trigger circuit group is made up of transistors T1゜1 and TlO2.
and connect these collectors to other transistors/)
(7) Cross-connect to the base.

Furthermore, it is connected to the collector of transistor T103, and its base is connected to the collector of transistor T105.

At the same time, the base of transistor TlO2 is connected to the collector of transistor T104, and its base is connected to the collector of transistor T106.

Furthermore, transistors Tl05 and T,.

Connect the base of 6 to the write conductors R and S, in which case these conductors are common (rubbed) to the row of the trigger circuit.

To enable reading, transistor T1o1 is provided with an extra collector, which is connected to the base of transistor T107, and whose collector is connected to a read conductor O common to the row of trigger circuits.

Transistors T , T , T and Tlo
The base electrode of atol 102 105 is connected to the current source 11011 II02 + 1
105 and IIQ6 are connected to a common supply line 1 for each column of the trigger circuit, and the base electrodes of transistors T103, T104 and T107 are connected to similar current sources 1103t IIQ4 and I10
7, a selection line SE common to the column of trigger circuits
Connect to.

The current sources are configured such that they supply current only if the associated supply or selection circuit carries a positive voltage.

Since the supply line ■ is always at a positive voltage, the current source 1101.
1102 + T105 and 1106 are always activated.

During the rest period, i.e. when no selection is made for the column of trigger circuits belonging to the circuit shown, the selection line SE is brought to ground potential or low, so that the current source I 10
3 II Do not operate 104 and 1107.

As a result, in the rest state, transistor T103
+ T1041 No current is conducted by T106 and T107 and therefore the consumption is low.

In the rest state of the trigger circuit, the transistor Tl0
One of I and TlO2 becomes conductive.

Now, assume that the transistor T1o1 is conductive.

Then, the base voltage of the transistor T is equal to +V· and becomes 01.

where V is the junction voltage between the base and emitter of the saturated transistor.

The base voltage of transistor T1o2 is equal to vk.

Here vk is the voltage between the collector and emitter of the overdriven transistor.

In the case of silicon transistors, V is generally 0.7V.
, and ■ is a value between 0 and 0.4■.

That is, since the base voltage of the transistor T1゜2 is made lower than the base voltage of the transistor T1o1), that is, lower than the junction voltage ■, the transistor T10
2 is the cutoff.

The collector current of the transistor T1o1 is supplied from a current source 1102, and the base current thereof is supplied from a current source I101.

When information needs to be read from the trigger circuit or new information written, a positive pulse is applied to the selection line so that the current sources ■to31 I 104 and II0
7 works.

When writing, one of write conductors R and S is set to ground potential.

Now, for example, the write conductor R is set to the ground potential.

Then, the current from current source 1105 flows to ground, and transistor T105 is cut off.

The current from the current source 1103 flows as the base current of the transistor T103, which becomes conductive.

Therefore, since the current from the current source 1101 flows through this transistor, the transistor T1o1 is cut off.

Regarding the floating write conductor S, the transistor T1.2 becomes conductive in the same way.

The collector current of the transistor T102 is connected to the current source 110.
Supplied from 1.

Therefore, from this current source I+01, transistor Tl
Supplies the collector currents of O2 and T103, respectively.

At the end of the selection pulse on the selection line SE, the transistor T1.2 remains conductive and the transistor T10I remains in the cut-off state, so that information can be stored in the trigger circuit.

A write pulse on one of the write conductors R or S does not affect the unselected trigger circuits.

If the selection pulse is not present on the selection line SE, the current sources I In3 and T104 are not actually operating, so that the transistors T and T1040
3 is a cut-off and therefore no information can be transmitted from the write conductor to transistors T1o1 and T1o2.

When reading, write conductors R and S are floated and transistor T1 is activated when a selection pulse is received.
05 and T1o6 are made conductive.

As a result, transistors T103 and T104 are cut off, making it impossible to extract information from the trigger circuit.

Depending on the state of the trigger circuit, the transistor T'to'
Make r conductive or non-conductive.

Again, transistor T1o, is cut off, and transistor T,.

2 becomes conductive, the current source I operated by the selection pulse
10? The current supplied by the transistor T'to'
y base current, which causes the transistor to conduct.

The state of transistor T107 is read out via readout conductor O.

Although only one readout conductor is shown in the figure,
It is likewise possible to provide a second readout line, which is likewise connected to the extra collector of the transistor TlO2.

FIG. 20 shows a portion of an integrated storage circuit, in which one trigger circuit and a main I-1 are shown for clarity.
Only two adjacent multi-IJ racks of other similar trigger circuits of IJ block size are shown.

A number of p-type base regions of the transistors Tl0I to T1o7 of the circuit are provided in the surface layer of the n-type semiconductor body.

Each said base region surrounds within the semiconductor body one or, in the case of the transistor T1°, two n-type collector regions, and the semiconductor body forms an emitter region common to all transistors.

A transistor is formed using a pattern of conductive strips 192.
Connect to the trigger circuit shown in FIG.

In the figure, each trigger circuit of the matrix is connected to conductive strips R, S and O.

A current source I, OI or I 107 shown in FIG. 19 is formed in an integrated circuit together with a current injection part.

Acts as a supply line and transistors T, T
The ribbon-shaped p-type surface region V provided on either side of the base region 190 of TlO2103v 105 and T1o6 is placed adjacent to the semiconductor surface.

The surface region (1) constitutes the injection layer of the current injection section, the semiconductor body is the intermediate layer of the current injection section, and the base region is the region to be biased to which the bias current is supplied in the same manner as described above.

Similarly, the p-type surface region SE acting as a selection line
and semiconductor body and transistor T103 + TlO
4 and the base region 190 of T107 constitute a current injection part.

Additionally, two parallel n-type surface regions are defined in the semiconductor body.

These regions each extend parallel to the two implantation layers 1 and SE and are doped at a higher concentration than the adjacent portions of the p-type semiconductor body.

Since the one region, 193, is adjacent to one long side of the region SE, the injection of charge carriers from the region SE is mainly performed in the direction of the transistors Y1o3゜T1゜4 and T107. Yes, but not in the direction of transistors T1o1 and T105 of adjacent trigger circuits.

The other n-type region 194 is connected to the transistor TIQ3 + T
104 and the base region of T107 and transistor 'I
102 and the base regions of T106, said region 194 prevents parasitic transistor action between the base regions of oppositely located sides of this region.

If desired, an additional n-type region may be provided between the trigger circuits of adjacent rows, and the region may be placed between the injection layer 1 and the SE strip R.
and G extending parallel to S.

As in the embodiments described above, a large portion of the total base region may also be individually surrounded by n+ surface regions or a buried insulating layer may be used in place of the heavily doped n-type region.

In the integrated circuit described above, the transistor T 105
and T 106 are necessary because they select separate storage elements for upstream writing.

In this circuit, the emitters of all transistors are connected together, so that selection of the storage element can only be obtained via the base connection.

As a result, separate transistors are required for row and column selection.

FIG. 21 shows a second storage circuit for use in a matrix formed by a number of equal storage circuits arranged in rows and columns.

This memory circuit includes two np-H type transistors T2O1 and T2O2 whose emitters are connected to a fixed potential point such as ground potential.

To obtain a bistable element, the base of each transistor is respectively connected to the collector of the other transistor.

The supply current for the storage circuit is supplied via current sources I 201 and I 202 connected to the bases of transistors T2O1 and T2O2.

Writing and reading of information is performed using a p-n-p type transistor T2.
Performed using O3 and T2O4.

Via the main current paths of these transistors T2O3 and T2O4, a connection is made between transistors T201 and T2O2 and read and write conductors S and R, respectively.

Each of these conductors is common to a row of memory circuits.

It is preferable that these transistors T2O3 and T2O4 have a symmetrical structure.

This is because these transistors operate in both directions to perform read and write operations.

Selection of the desired storage circuit is accomplished by selecting the associated column using a selection line common to the column of storage elements and connected to the bases of transistors T2O3 and T2O4 and read and write conductors S and R. This is done by selecting the relevant row using

It is necessary to suitably choose the values of the voltage levels of the selection line and the read and write lines in both the selected and non-selected states.

For example, by supplying a voltage to the selection line in the non-selected state, the transistors T2O3 and T2O4 are connected to the conductor S or R.
The cutoff is made regardless of whether a write pulse is incoming or not in any of the write pulses.

In the selection state, the voltage on the selection line is selected to control the transistor T2O in two stable states of the storage circuit.
1 and T2O2.

In the unselected state, read and write conductors S and R
, for example, so that no information is lost regardless of the selected or unselected state of the column belonging to the associated storage element.

When writing information, the write pulse must be sufficiently positive than the voltage level of the selected selection line to cause the associated transistor T2O3 or T2O4 to conduct.
When reading information, the voltage level of the read conductor is preferably lower than the voltage level of the selected selection line.

In order to minimize the consumption of the storage circuit and to achieve high readout speeds, the supply level of the storage circuit is kept low during steady state and the current source I is used during reading.
The supply level is switched to a high level by controlling the current supplied by I 201 and I 202.

The circuit arrangement shown in FIG. 21 is particularly suitable for integration into a semiconductor body.

In that case, p-n-p type transistors T2O3 and T
2O4 as lateral transistors, in this case,
Although two directions are used, it is important, especially in the case of lateral transistors, that the electrical characteristics in both directions be approximately equal.

Furthermore, the two current sources I201 and I202 can be simply formed using electrical injection.

As a result, only a relatively small semiconductor surface is required for the integrated structure.

22 and 23 show a portion of an integrated structure of a storage matrix with current injection.

This is provided within the broken line 223 in FIG. 22, and the matrix element shown in FIG. 21 is provided in this area.

The semiconductor body 200 is provided with a semiconductor substrate 201, in this case of p-type trench type.

This p-type substrate 201 is provided with an n-type epitaxial layer 202 subdivided into islands using p-type isolation regions 203 by a conventional method.

n-p-n transistors T for all matrix elements of the column
2O1 and T2O2 are provided within the elongated island 204.

This island is grounded at the end of the semiconductor body, for example using the connection 205 shown.

The island 204G constitutes a common emitter region of the npn transistors.

A number of injection layers are provided within the island 204, only one of which is shown in the figure.

Said layer is in this case configured with a p-type surface region 206 .

Four npn transistors are provided on either side of each injection layer 206.

These transistors are provided with a p-type base region 207 and an n-type collector region 208.

This base region 207 has a surface 209 on three sides.
surrounded by a low resistance n-type surface region 210 at.

This region 210 extends from the surface 209 into the epitaxial layer and is adjacent to an n-type buried station 211 provided at the boundary between the substrate 201 and the epitaxial layer 202 .

Regions 210 and 211 belonging to the intermediate layer 204 constitute a low resistance assembly having a large number of recesses, in which the injection layer 206, the high resistance portion 212 of the intermediate layer 204 and the region 207 to be biased are placed. establish.

Furthermore, regions 210, 211 and buried layer 211 reduce the series resistance of island 204, making said layers nearly equipotential surfaces during operation.

Matrix element lateral p-n-p transistor T2
A similar island 221 that formed O3 and T2O4 is called island 20.
4 on either side.

Further, a low resistance n-type region formed by the surface region 213 and the buried layer 214 is provided in this island to reduce the series resistance.

In practice, these islands 221 constitute a common base region of the pn-p transistors of the rows of matrix elements;
It is made to act as a selection line SEL.

Furthermore, each p-n-p transistor is provided with a p-type head region 215.

This area acts as an emitter area when reading information, and acts as a collector area when writing information.

Furthermore, a p-type region 216 is provided in the transistor.

This region also acts as a collector region and an emitter region, respectively.

Each of these p-n-p transistors is surrounded by a cup-shaped portion of a low resistance region 213,214.

As a result, almost no parasitic transistor action occurs between the base regions of adjacent pn-p transistors.

An insulating layer 217 is provided on the surface 209 of the semiconductor body 200 and conductive strips 218 extend thereon.

The strips form the internal connections of the matrix element and connect it to the semiconductor region of the circuit element via holes in the insulating layer, indicated by dashed lines in FIG.

Furthermore, the insulating layer 206 is connected to the conductive strip 219 in which the connection 220 is provided, the region 216 of the transistor T2O3 of the row of the matrix element is connected to the conductive strip S, and the transistor of the row of the Mah IJ element is connected to the conductive strip S. A region 216 of T2O4 is connected to the conductive strip R.

A power source 222 is connected between connections 205 and 220 to forward bias injection layer 206, the interlayer p-n junction, and intermediate layer 204.

This layer 222 can, for example, be controllably applied to the matrix element n-
p-n) can be supplied to the transistor.

Also, since such control of the bias current is performed per unit of conductive strip 209, the bias current can be controlled individually for each of two adjacent rows of matrix elements.

The integrated structure described with reference to FIGS. 22 and 23 is particularly compact.

The desired semiconductor surface area can be reduced by replacing n+ regions 210 and 213 with a buried insulating layer extending from surface 209 to the boundary between epitaxial layer 202 and substrate 201.

In that case, in practice p-type isolation region 203 and n-type regions 210 and 213 could be provided on either side, or a single solid insulating layer could be used instead.

As a result, the distance between an npn transistor and a pnp transistor in a row and the distance between adjacent pnp transistors can be reduced.

As is clear from the examples and references described above, significant benefits can be obtained using the present invention.

In many cases, it is sufficient to use only five masks during manufacturing.

Furthermore, high packaging density of active elements can be obtained,
Resistance is almost completely unnecessary.

Since the emitters of the transistors used are directly connected to each other,
The pattern of the conductive strips is relatively simple and the collectors can be automatically separated from each other.

Furthermore, multi-collector transistors can be used in a simple manner, thereby saving a large area and a large number of conductive strips.

During operation, it is particularly advantageous to vary the total bias current supplied using the current injection in a similar manner by the voltage across the injection junction.

As a result, the functionality of the integrated circuit can be made nearly independent of the current level, resulting in a wide noise margin.

In the above-mentioned circuit, these currents are particularly supplied using a current injection part, but the reason for providing this current injection part is
This is for processing any information, including analog or digital signals, currents or voltages, or, where applicable, for storing written information.

These currents, called standby currents, include all currents in components such as logic circuits, circuits and storage elements that, in their static or dynamic state, cause these components to be in a standby state. , that is, when information occurs at the input terminal, it can be combined with a selection signal if necessary so that said information can be retrieved;
Writing information can be stored and/or said information can be communicated to an output terminal after selection, if desired.

The integrated circuits in all of the embodiments and reference examples described above can be fabricated using methods commonly used in semiconductor technology, such as epitaxial methods, formation of buried layers, doping for local diffusion and/or ion implantation, patterned insulation. It can be completely manufactured by forming a conductive layer such as a mask.

Furthermore, the integrated circuits described above can be assembled in a conventional manner within a conventional enclosure.

For example, the manufacturing method of the first reference example, that is, the manufacturing method of the flip-flop shown in FIGS. 1 to 5 will be described in detail below.

For example, the starting material is of n-type conductivity and has a resistivity of 0.00.
5 oyohi 0. Silicon substrate 21a (second
Figure).

For example, set a specific resistance of 0.2 and 0.6Ω on this substrate.
An n-type epitaxial silicon layer 21b having a thickness of approximately 5 μm, for example, is provided between the two layers.

In this context, the current amplification factor β of the inversion transistor structure used depends on the resistivity of the epitaxial layer.

The amplification factor β is about 20, and the specific resistance is about 0.1ff-
Let α be the same p and n type diffusion and about 0.6.0
In the case of a specific resistance of -, β becomes about 10 times, and from this it can be seen that it is desirable to set β to a value of 3 or more in order to ideally operate the circuit.

Next, using a mask layer of silicon dioxide, for example, a diffusion process of phosphorus as an impurity is performed to obtain a low resistance n-type portion 21C.

The surface concentration of this portion is, for example, 1021 atoms/cubic centimeter.

The holes forming the phosphorus doped region in the semiconductor body extend in parallel so that there is always a sufficient range between two adjacent extensions within which to form the desired area in the next processing step. A base region of the same size can be formed.

Furthermore, two of these holes are used, in which case the holes are arranged with their elongated portions facing each other and in line with each other.

The distance between the ends of the oppositely disposed extensions of these holes is equal to or slightly less than the final desired distance between the oppositely disposed base regions, e.g. 5 and 10. do.

The base regions 1 to 10 and the injection layer 20 are simultaneously formed by diffusion through holes of the desired size in the mask layer.

In this example, the mask pattern is constituted by two parallel strips, and these strips are arranged so that the elongated portions of the preferential area extend in the transverse direction, and between the elongated portions that are arranged opposite to each other. , each of which at one end slightly overlaps the end of said elongated portion, or such that they touch each other.

The width of the strips is matched to the desired distance between each base region and the injection layer.

For example, boron can be indiffused through the free surface to a depth of, for example, 2.5 μm, resulting in a resistance per unit area of, for example, about 15 μm.
It is set to 0.2.

Between the two mask strips, an injection layer is obtained and furthermore base regions 1 to 10 are obtained which are separated from each other.

The reason for this is that the surface concentration of the diffusion treatment is insufficient and the conductivity type that has already been formed is changed to the n+ portion 21C.

In this way, the base region is automatically made directly adjacent to the first sub-region 21C.

Each of these sub-regions is surrounded by a U-shaped n-type region on its three sides.

The collector regions 22 to 37 are, for example, filled with about 1.5 phosphorus.
formed by local diffusion to a depth of .mu.m and a resistance of 58 per unit area, then etching contact holes into the insulating layer and forming a pattern of conductive strips 14, for example by evaporating an aluminum layer. It is then formed by etching.

The width of the injection layer 20 is, for example, approximately 20 μm.

The distance from the injection layer 20 to each base region is approximately 8 μm.

The size of the base region 5 is, for example, approximately 50 μm x 80 μm.
m, and the size of the collector region 33 is 20μm×20μ
Let it be m.

The width of the total extension between adjacent base regions is, for example, 10μ.
Let it be m.

If a buried insulating layer is used in place of the whole or part of the resistive subregion 21C, the insulating layer can be obtained by, for example, a local oxidation treatment using a mask layer made of, for example, silicon nitride. be able to.

As shown by way of example in FIGS. 6 and 13, if buried layers are used, they may be doped with, for example, arsenic to give a surface concentration of about 1019 atoms/cm3 and a resistance per unit area. is approximately 209.

For example, the buried layer 135 shown in FIG. 13 is a region doped with impurities higher than the base region to be biased.

This can be particularly advantageous if the buried layer forms part of the emitter region of the associated transistor.

The present invention is not limited to the embodiments described above and can be modified in many ways.

For example, AIIIBV of germanium and semiconductor materials
Other semiconductor materials such as compounds or combinations can be used.

That is, for example, the substrate is made of a different semiconductor material than the surface region on which the circuit elements are formed.

Instead of starting from a substrate 21a (FIG. 2) on which a lightly doped layer 21b is epitaxially grown, the starting material can also be a low resistance substrate, which is then coated with a much lower doped surface layer for out-diffusion of impurities. It is also possible to provide

Furthermore, when the conductivity types in the above embodiments and reference examples are exchanged, it is necessary to exchange the voltage polarities at the same time.

It is also possible, for example, to form one or more optical signal input terminals and/or signal output terminals on the integrated circuit.

For example, an incoming optical signal can be converted into an electrical signal using a photodiode or phototransistor integrated into the circuit.

In this case, the electrical signal is used as an input signal to other parts of the circuit.

The injection layer can also be used, for example, as a layer separated from the intermediate layer of the current injection part by a thin layer of insulating material.

Tunnel injection can be used to direct charge carriers from the conductive layer through a thin insulating layer to the intermediate layer of the current injection part as minority charge carriers.

The current injection part can be constructed, for example, with four or at least an even number of layers.

However, it is preferable to use this current injection section composed of an odd number of layers.

In addition, in the case of a current injection layer consisting of four or more layers, at most one other region of the associated circuit element, spaced apart from the region to be biased, is formed together with the layer with the current injection part. .

Furthermore, the third and fifth layers in the current injection section, which may consist of, for example, seven layers, are used independently of each other to control the bias current to be supplied to the region to be biased.

The third and fifth layers can therefore, for example, be two input terminals of an AND gate whose output terminal is formed by the region to be biased.

In circuit element areas other than the illustrated bipolar transistors, such as diodes and field effect transistor areas,
Similarly, a current injection section can also be used to supply a bias current.

Furthermore, it is possible, for example, to control the gate electrode of a field effect transistor, in particular a low threshold voltage field effect transistor, using a current injection.

When using the lateral current injection shown in FIG. 1, the ratio between the bias currents supplied to each region to be biased is equal to
It is proportional to the ratio between the lengths of the portions of the p-n junction between 1 and 1 facing the injection layer 20.

In the illustrated example, the amount of bias current obtained is equal for each base region.

Differences in the length of the structures can be used to change the ratio.

In this way, for example, first and/or last stage transistors on an integrated circuit board can be supplied with relatively large currents to increase the noise margin at the board's input and output terminals.

Another way to increase this noise margin, if necessary, is to increase the current gain value β.

Such high circuit gains can be obtained by forming a relatively wide collector region in the transistor in question.

The dimensions of such a relatively wide collector area are, for example, 40
The dimensions are .mu.m x 20 .mu.m, which is different from the 20 .mu.m x 20 .mu.m used in the embodiment shown in FIG.

This extended collector region is 50 μm in the case of FIG.
Rather, it is formed within a relatively wide base region of 70 μm.

Another method of setting up different bias currents for different regions to be biased uses associated injection active junctions of the current injection section and different distances between different regions to be biased.

As this distance increases, fewer charge carriers are captured by the increasingly biased region and the effective diffusion length in the region adjacent to the increasingly biased region increases.

Furthermore, instead of impurity doping, one or more layers of the current injection part can be modified within the semiconductor body, for example by means of surface conditions and/or charges in the insulating layer and/or electrode layers provided on the insulating layer. , can be induced.

In the above-described five-layer current injection section, the third layer can be formed of an induction inversion layer, for example.

Furthermore, one or more layers of the current injection layer can be constructed by combining a portion obtained by doping with impurities and an induction portion in close contact with the portion.

For example, since the distance between the injection junction and the capture junction obtained in the current injection part is made relatively large by doping,
In the part of the current injection part, when no current flows most of the time, the distance is reduced by extending one or both layers by an inversion layer on the side surface facing the other layer. be able to.

When using the above-mentioned inversion layers, especially when these layers are formed using insulated electrode layers, the bias current supplied to the region to be biased can be controlled by the voltage of the electrode layer.

As is clear from the embodiments described above, the integrated circuit of the present invention can be made compact in structure and can be manufactured by a simple method.

According to the invention as described above, there is provided a novel integrated circuit structure comprising a Schottky collector transistor with the collector disposed on the surface of a common body and on the base region and with suitable current source means coupled to the base region. can be provided.

As a result, the transistor can be made considerably smaller and the Schottky collector can be manufactured quite simply.

This characteristic of the Schottky collector also improves the electrical performance of the integrated circuit.

Furthermore, these transistors have almost no charge storage, have small capacitance, and have considerably faster switching speeds.
Moreover, the saturation voltage is also considerably high.

[Brief explanation of the drawing]

Figure 1 is a schematic plan view showing a part of the first example of an integrated circuit using a current injection part, and Figure 2 is a diagram taken along the line ■-■ of the integrated circuit shown in Figure 1. 3 is an electrical circuit diagram showing the integrated circuit shown in FIGS. 1 and 2, FIG. 4 is a circuit diagram showing a gate circuit with a current injection part, and FIG. 5 is a circuit diagram showing the integrated circuit shown in FIGS. 1 and 2. 6 is a sectional view showing a part of a second reference example of an integrated circuit using a current injection section, and FIG. 7 is a sectional view taken along the line ■-v of the integrated circuit shown in FIG. FIG. 8 is a sectional view of the integrated circuit of FIG. 7, and FIG. 9 is an embodiment of the integrated circuit according to the present invention. FIG. 10 is a circuit diagram showing an electric circuit related to the above-mentioned embodiment O. FIG. 11 is a circuit diagram showing a fourth reference example of an integrated circuit having a current injection part. 13 is a line diagram for explaining the principle of another reference example of an integrated circuit using a current injection part, and FIG. 13 is a line sectional view showing a part of the fourth reference example of the integrated circuit shown in FIG. 11. , FIG. 14 is a schematic plan view showing a part of the fifth reference example of the integrated circuit using the current injection part, and FIG. 15 is a cross-sectional view taken along the line xv-xv in FIG. 14. , FIG. 16 is a schematic plan view showing a part of the sixth reference example of the integrated circuit using the current injection part, and FIG. 17 is a sectional view taken along the line X-■ in FIG. 16. , FIG. 18 is a schematic cross-sectional view showing a seventh reference example of an integrated circuit using a current injection section, and FIG. 19 is a schematic cross-sectional view showing an eighth reference example of an integrated circuit using a current injection section. A circuit diagram showing the circuit, FIG. 20 is a schematic plan view showing the integrated circuit of FIG. 19, and FIG. 21 is a circuit showing the electrical circuit related to the ninth reference example of the integrated circuit using the current injection part. 22 is a plan view showing the integrated circuit shown in FIG. 21, and FIG. 23 is a sectional view taken along line xxm-xxm in FIG. 22. 1-10... Circuit element, 5... Capture layer, 12... Semiconductor body, 14... Conductive strip, 15, 16° 132. ...Connection section, 17
...Power supply, 18,19°130.131...
... Rectifier junction, 20,128 ... Injection layer, 2
1... Intermediate layer, 120... One side of semiconductor body, 125... Current injection layer, 127...
...adjacent layer.

Claims (1)

[Claims] 1 a common body having at least one transistor on one side, the transistor having a base region of one conductivity type adjacent to the surface of the common body on said side and in rectifying contact with its emitter and collector, respectively; The base region also acts as the third layer of a three-layer structure of a current injection section used as a bias current source, and the three-layer structure is separated from the base region by a surface-adjacent layer of opposite conductivity type as the second layer. a first layer including an injection layer separated from the transistor by forming a rectifying junction with the second surface-adjacent layer; located between the regions and acting as the emitter, as well as forward biasing the rectifying junction of the three-layer structure to supply charge carriers to the base region, thereby creating a rectifying contact between the base region and the emitter. a metal or metal-containing layer formed on the base region of the one side of the common body to form a Schottky junction between the base region and the collector of the transistor; 1. An integrated circuit according to claim 1, further comprising a Schottky junction which forms a rectifying contact between said collector and base regions.