JPS5856454A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the delay of the propagation of a signal between semiconductor layers in a semiconductor device by communicating a signal between the layers with a contacting hole formed at an insulating layer on an oblique surface and a semiconductor element formed on the insulating layer. CONSTITUTION:An oblique surface 31 having an angle of theta (<90 deg.) to the main surface of each semiconductor layer is formed at the periphery of a chip over n-th semiconductor layer 11, (n+1)-th semiconductor layer 13 and an insulating layer 16 therebetween, a semiconductor layer 33 is formed through an insulating layer 32 thereon, and an MOS transistor having a source 34, a drain 35 and a gate 36 is formed. The source 34 of the MOS transistor is connected to the source 12 of the MOS transistor formed on the layer 11 through a through hole formed at the layer 32, a drain 35 is connected similarly to the drain 14 of the MOS transistor, the data at the n-th layer is selected at the gate 36, and is transmitted to (n+1)-th layer.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to semiconductor devices, and more particularly to an excellent signal transmission technique between layers of a semiconductor device in which functions are integrated in multiple layers.

In recent years, there has been a remarkable increase in the degree of integration in semiconductor integrated circuits, and in particular, with remarkable progress in microfabrication technology, elements and interconnections with a minimum dimension of about 1 μm can now be easily formed in one plane. Recently, in order to further increase the degree of integration, the development of so-called three-dimensional ICs, in which semiconductor layers with integrated elements are stacked in multiple layers, has become active, rather than simply integrating them on one plane. One of the basic problems in original ICs is the transmission and reception of signals between layers.

In other words, there are many problems in forming wiring that transmits signals processed in one layer to other layers.

The problems of the conventional example will be briefly explained with reference to FIG. 1st
The figure is a simplified cross-sectional view showing, as an example, the wiring between two layers in multi-layer stacked circuit board 1c. That is, a case is shown in which the drain 12 of the MOS transistor included in the n-th semiconductor layer zxVc is electrically connected to the source 14 of the MOS transistor included in the n+1-th semiconductor layer 13. For example, drain 1
2, the data processed in the semiconductor layer 11 is outputted through the select gate 15, and the data is transferred to the MOS transistor (MOS) formed in the semiconductor layer 13 formed on the top via the interlayer insulating layer 16. to the source 14 of the conductor 11
and the signal is transmitted via select r-)
18, and is taken into the circuit within this semiconductor layer 13 and subjected to signal processing.

Now, in order to form such an interlayer wiring, for example, after completing the integration of elements in the a-th semiconductor layer 11,
A glabellar insulating layer 16, such as O2, is provided thereon and through holes are formed therein.

This was doped with impurities as the conductor 17, for example. j?
Fill IJ silicon, etc., and then form a semiconductor layer 13 on top of it.
is formed, and MOS transistors and the like are built into it. In this case, as shown in the figure, a deep diffusion layer 19 or the like is used to connect the source 14 and the conductor 17.

In such conventional structures, it was first difficult to form thin through holes with a good yield, and it was also extremely difficult to properly fill the formed through holes with conductive material. An example of a three-dimensional IC constructed using such a conventional technique is shown in a conceptual diagram. That is, this consists of five semiconductor layers 21 to 2.
It is a decompiler made by laminating 5 and M.
The first layer 21 and the second #22 are each I MbitR
The third layer 23 is a microprocessor that performs signal processing, that is, a CPU (central processing unit). Furthermore, the fourth layer is a 4Mbit ROM that stores programs, and the fifth layer (the topmost layer) controls signals to each layer, and also includes the functions of a sequencer, etc. It is a controller. In order for a chip with such a configuration to function effectively, it is important to freely exchange signals between each layer, and in particular, the controller layer constantly exchanges signals with each layer. Therefore, in such a structure, a technique for forming three holes from the fifth layer to the first layer and filling the conductive material is required, which involves great technical difficulties.

Additionally, signals are often transmitted to other layers via the controller layer, and signal delay is also a major problem in conventional configurations.

The present invention provides a multilayered semiconductor device that solves the above problems.

A semiconductor device according to the present invention includes a plurality of semiconductor layers in which elements are integrated and stacked and separated from each other by an insulating layer, and has an inclined surface spanning two or more layers of the stacked semiconductor layers, and this inclined surface. A semiconductor layer is provided on top via an insulating layer,
The present invention is characterized in that signals are exchanged between the stacked semiconductor layers through semiconductor elements formed in this semiconductor layer.

According to the present invention, the hole formed in the insulating layer on the inclined surface and the semiconductor element formed on this insulating layer,
Since signals are exchanged between arbitrary laminated semiconductor layers, manufacturing is easier compared to conventional methods in which signals are exchanged between the eyebrows by passing a conductive material vertically between multiple laminated semiconductor layers. Further, the delay in signal propagation between each layer can also be reduced.

The present invention will be explained in detail below. FIG. 3 shows an embodiment of the present invention in a situation similar to that of FIG.
The same reference numerals as in FIG. 1 are given to parts corresponding to those in the figure.

Unlike FIG. 1, the n-th semiconductor layer 11, the n-th
An inclined surface 31 having an angle of θ (θ×90) with respect to the main surface of each semiconductor layer is formed around the first semiconductor layer 13 and the insulating layer 16 between the first semiconductor layer 13 and its inclination. A semiconductor layer 33 is formed on the surface 31 (eg, a MOS transistor having a source 34, a drain 35, and an r-t 36 on which a semiconductor layer 33 is formed via an insulating layer 32 such as 5tO2). This semiconductor layer 33 is made of, for example, silicon, or may be made into a single crystal by using radar annealing, EB annealing, or the like.

The source 34 of this MOS transistor is connected to the source 12 of the MOS transistor formed in the semiconductor layer 11 through a through hole 2 provided in the insulating layer 32, and the drain 35 is connected to the through hole 2 provided in the insulating layer 32. It is connected to the drain 14 of the MOS transistor formed in the semiconductor layer 13 via the MOS transistor. In this way, the data in the nth layer is selected by the r-t 36 and transmitted to the n+1th layer. In other words, the data of the n-th layer is not only transmitted to the @n+1 layer, but also has the function of selection, and it can be seen that the number of functions is increased compared to the conventional example.

Here, only the case where an MO8 transistor as a simple ff-) element is provided on a slope is illustrated, but this may also be a more complicated circuit combining two or more transistors. Although we have described the case where a single semiconductor layer is provided on an inclined surface, it goes without saying that two or more semiconductor layers may be formed to provide a more advanced function. The layer 31 is in direct contact with the laminated semiconductor layers 11 and 13 through the through holes.
Although the installation case has been described, any other connection method may be used. For example, it goes without saying that the semiconductor layer on the inclined surface and the laminated semiconductor layer may be connected separately by conductor wiring. In any case, the through holes need only be opened in the insulating layer on the inclined surface, which is extremely easy, and the yield reliability is also improved.

FIG. 4 is a conceptual diagram showing an example of realizing a one-chip combiner according to the present invention corresponding to FIG.
MbitRAM layer 42. Microprocessor layer 43
, 4 Mbit ROM layer 44, and a controller layer 45 is formed on an inclined surface spanning these four layers. Not only can all signals be sent and received between each layer through wiring within the controller layer 45, but these signals can also be subjected to arbitrary processing and transmitted to other layers.

In addition, since there is no need to transmit signals to the uppermost controller layer and then to other layers as in the past, high-speed operation can be achieved.

In addition, through-holes extending from the first layer to the fifth layer are not needed as in the past, and they only need to be opened between the controller layer and each layer, so they can be opened with a high yield and are highly reliable. Motsu.

FIG. 5 is for explaining an example of the method for manufacturing a semiconductor device of the present invention, and shows how an element pattern is formed on an inclined surface 52 formed at an angle θ with respect to the main surface of a wafer 51. This shows that. That is, wafer 5
1 by θ, the inclined surface 52 is made orthogonal to the optical axis of conventional reduced projection exposure, thereby enabling Δturn transfer. - After completing the exposure transfer of the inclined surface, by moving the Ueno S51 in parallel while tilted by θ,
All the same 4' turns can be transferred to other similar inclined surfaces.

In this case, if θ≦45°, as shown in the figure, it is possible to prevent a part of the adjacent kede from interfering with the transfer. This method of tilting the wafer and moving it parallelly may be combined with not only optical transfer but also direct writing with an electron beam. In this case, the working distance (Worklmg dl
Add sea urchin/S to conventional equipment without changing the
Exposure can be performed simply by attaching a stage that can be tilted and moved in parallel.

FIG. 6 shows one method of exposing a wafer 61 at once to X-rays. As shown in the figure,
If the exposure mask 63 is placed parallel and X-rays are irradiated perpendicularly to it, the depth of focus of the X-rays is as deep as several μm, so it is possible to form fine arm-turn elements even on the inclined surface 62. The method shown in FIG. 6 does not necessarily require the use of X-rays; it is also possible to use ultraviolet rays with a wavelength depending on the gloss turn precision, the angle of the slope, etc.

Although the controller layer 45 is provided on the inclined surface in FIG. 4, it may be a ROM layer, a micro layer, a RAM layer, or any other layer having any other function. It may be a layer.

Further, as shown in FIG. 7, sloped surfaces are formed on the four sides of the quadrilateral, and a controller layer 71 is formed on each sloped surface.
and 72. -'P microprocessor layers 13 and 1
It is also possible to arrange a configuration in which the internal stacked section 75 is made up of only RAM and ROM. Also, if necessary, during lamination in the middle! A microcontroller layer, a sublayer controller layer, etc. may be inserted. In addition, the shapes of C and D do not have to be limited to quadrilaterals; for example, they can be made hexagonal, increase the number of peripheral surfaces, provide sloped surfaces for each, and place semiconductor circuits with new functions on these. good.

Also, by arbitrarily changing the circuits formed on these surfaces,
It is also possible to realize a three-dimensional IC with different functions without changing the other components. may be provided as appropriate.

Even if it is groove-like like these scribe lines,
It may also be hole-shaped. Furthermore, the angle of the inclined surface does not need to be kept constant and may be changed as needed.As described above, according to the present invention, the angle between the layers is much smaller than when three-dimensional ICs are simply laminated as in the past. It has become easier to send and receive signals, increasing the speed4, and dramatically diversifying functions.

[Brief explanation of the drawing]

Figure 1 is a sectional view showing the glabella connection of a conventional 3D IC, and Figure 2 is the same (schematic diagram of an example of a conventional 3D IC).
FIG. 3 is a cross-sectional view showing the state of the glabella connection in an embodiment of the present invention, FIG. 4 is a schematic diagram of an embodiment to which the present invention is applied to the three-dimensional ICK corresponding to FIG. 3, and FIG. FIG. 6 is a diagram for explaining an exposure method for an inclined surface to obtain the apparatus of the invention, FIG. 6 is a diagram for explaining another exposure method, and FIG. 7 is a schematic diagram showing a modification of FIG. 4. be. 11.13... Semiconductor layer, 16 interlayer insulating layer, 31.
... Slope, 33... Semiconductor layer. Applicant's Agent: Patent Attorney Tosuzu, Takehiko E, Figure 5, Figure 7

Claims (2)

[Claims] (1) In a semiconductor device in which a plurality of semiconductor layers in which elements are integrated are stacked and separated from each other by an insulating layer,
It has an inclined surface that extends over two or more of the stacked semiconductor layers, a semiconductor layer is provided on the inclined surface with an insulating layer interposed therebetween, and the semiconductor element formed on the semiconductor layer is provided with the A semiconductor device characterized in that signals are exchanged between stacked semiconductor layers. (2) The semiconductor device according to claim 1, wherein the inclined surface is provided around the semiconductor chips.