JPS5853531B2 - stereo demodulation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement of a stereo demodulation circuit, and particularly aims to improve the SN ratio (signal-to-noise ratio) when receiving a weak electric field signal.

It is known that in an FM broadcast receiver, the SN ratio is worse when receiving a weak electric field signal than when receiving a medium electric field signal, and in particular, it is worse in a stereo reception state than in a monaural reception state.

Particularly in vehicle-mounted FM receivers, the electric field strength changes rapidly, and the SN ratio worsens when the electric field is weak, resulting in uncomfortable listening conditions.

Conventionally, in order to prevent the SN ratio from deteriorating, when a stereo signal is received in a weak electric field, the receiver is forcibly put into a monaural state in order to improve the SN ratio.

As shown in Fig. 1, when the input signal becomes small and the output signal (solid line A in Fig. 1) also becomes small, the SN ratio in the stereo reception state (dotted chain line in Fig. 1) is higher than the mono signal. It focuses on the fact that the signal-to-noise ratio of the receiver (dotted line c in Figure 1) is better.For example, by switching the receiver to monaural mode at point B in Figure 1, the signal-to-noise ratio can be greatly improved. It is done.

However, in the conventional method, the stereo reception state is forcibly and abruptly switched to a monaural state, which gives a sense of discomfort to the listener and, for example, at point A in Figure 1.
When the input signal is smaller than , the deterioration of the signal-to-noise ratio is too severe even in a monaural reception state, and the problem is that it is difficult to listen to it.

Furthermore, a method of substantially improving the signal-to-noise ratio by cutting unpleasant high-frequency noise is also conventionally known.

For example, as shown in Fig. 2, capacitors 4 and 5 for cutting high-frequency components are connected to the left and right output terminals 2 and 3 on the stereo demodulation circuit via switches 6 and 7, respectively, and the electric field strength of the input signal is When the signal becomes below a predetermined level, the switch is turned on to cut high-frequency components and improve the S/N ratio.

However, such a method has the disadvantage that the S/N ratio changes rapidly before and after the switch is turned on, and the frequency characteristics also change rapidly.Moreover, in the case of a car-mounted receiver, it is difficult to respond to changes in electric field strength. As a result, switching is performed frequently, which has the disadvantage of being extremely jarring to listeners.

The present invention has been developed in view of the above points, and will be described below based on embodiments with reference to the drawings.

FIG. 3 shows an embodiment of the present invention, in which 8 is a difference signal demodulation circuit for demodulating the sub-channel signal ((L-fl) sinωt).

The demodulation circuit 1 includes a first differential circuit L3 comprising first and second transistors 11 and 12 controlled by positive and negative 38 KHz switching signals applied to first and second control terminals 9 and 10; A second differential circuit U consisting of third and fourth transistors 14 and 15, a first differential circuit L3 whose collectors are aligned, a fifth transistor 1T whose base is connected to a bias power supply, and whose collector is connected to the second differential circuit L3; The dynamic circuit U includes a sixth transistor 19 whose base is connected to the stereo composite signal input terminal 18 and a constant current transistor 20, and a sub-channel signal in the stereo composite signal applied to the base of the sixth transistor 19. is switched by a 38 KHz switching signal, thereby sending the first stereo difference signal (L-R) to the collector of the third transistor 14 and the second stereo difference signal (R-R) to the collector of the fourth transistor 15.
L).

Further, υ and υ' are first and second sum signal circuits that generate main channel signals (stereo sum signal (L+R)) to be added to the first and second stereo difference signals, respectively;
The first sum signal circuit υ includes a third differential circuit C, which is composed of seventh and eighth transistors 22 and 23, which are controlled by third and fourth control signals t1 and t2, and a ninth and tenth) transistor 25. and 26, an eleventh transistor 28 whose collector is connected to the third differential circuit L and whose base is connected to the stereo composite signal input terminal 18, and whose collector is connected to the fourth differential circuit L. 27, the stereo composite signal input terminal 1B is connected to the stereo composite signal input terminal 1B via a high frequency cut circuit I whose base is composed of a resistor 29 and a capacitor 30.
a twelfth transistor 32 connected to the second transistor 32;
It is arranged to generate a stereo sum signal (L+R) to be added to the first stereo difference signal (LR) obtained at the collector of the third transistor 14 of the differential circuit U.

The second sum signal circuit J' includes a second stereo difference signal (
Stereo sum signal (L+R) added to R−L)
The configuration and operation are the same as those of the first sum signal circuit υ, and the explanation thereof will be omitted.

Note that the circuit elements of the second sum signal circuit J' include the corresponding first
The figure number of the sum signal circuit 1 is shown with a dash added.

Next, the operation will be explained.

When the electric field strength of the received signal is sufficiently large, that is, within the range where the input signal is lower than point B in FIG. The first stereo difference signal (L-R) obtained at the collector of the fourth transistor 14 of the two-differential circuit U and the stereo sum signal (L+R) from the first sum signal circuit υ are added,
m2L) stereo signal at the first output terminal 33, a second stereo difference signal (R-L) obtained at the collector of the fourth transistor 15 of the second differential circuit U, and a second sum signal circuit 2-
The stereo sum signal (L+R) from 1' is added, and a right (2R) stereo signal is obtained at the second output terminal 34.

The third and fourth control signals t and t2 applied to the third and fourth control terminals 35 and 36 are as shown in FIG. , IF amplifier circuit 0, FM detection circuit (2), and stereo demodulation circuit 0.

The signal passing through the IF amplifier circuit 0 has an amplitude proportional to the electric field strength.

Therefore, if the signal is extracted by the detection circuit 0 and the third and fourth control signals t1 and t2 having a predetermined relationship are generated by the control signal generation circuit 0, the third and fourth control signals t1 and t2 will be This is a signal related to electric field strength.

Incidentally, the relationship between the third control signal t1 and the fourth control signal t2 is set so that t2=(Att).

(However, A is a constant). In the first operating state, since the electric field strength is sufficiently large, the relationship tl>t2 holds, and therefore, with respect to the first sum signal circuit υ, the seventh transistor 22 of the third differential circuit L4 and the fourth differential circuit L4 The first of the dynamic circuit H
Since the zero transistor 26 is conductive and the eighth and ninth transistors 23 and 25 are non-conductive, the signal is applied from the stereo composite signal input terminal 18 to the third differential circuit L4 via the base-collector path of the eleventh transistor 28. The resulting stereo sum signal (L+R) is transmitted to the seventh transistor 22
is supplied to the collector of the third transistor 14 of the second differential circuit t from which the first stereo difference signal (L-R) is obtained, and the left stereo signal (2L) is supplied to the first output terminal 33.
) is obtained.

The same applies to the second sum signal circuit 1', and the third sum signal circuit 1' in the above state
By applying the fourth control signals t1 and t2, a stereo sum signal (L+R) is obtained at the output terminal, which is a second stereo difference signal obtained at the collector of the fourth transistor 15 of the second differential circuit t. (L), and a right stereo signal (2R) is obtained at the second output terminal 34.

When the electric field strength decreases and the input signal becomes smaller than point B in FIG. 1, the output signal of the difference signal demodulation circuit becomes smaller.

That is, the signals obtained at the first and second output terminals 46 and 47 of the 38 KHz switching signal level control circuit shown in FIG. 5 are applied to the first and second control terminals 9 and 10 in FIG. 3.

The level control circuit includes differentially connected transistors 48 and 49, a constant current transistor 50, and a control terminal 51 to which a signal for controlling the collector current of the constant current transistor 50 is applied. 38K applied to the bases of differentially connected transistors 48 and 49, respectively, in response to a control signal applied to terminal 51.
This is for attenuating the Hz switching signal.

The control signal corresponds to the electric field strength of the received signal, and is taken out from the IF amplifier circuit 41 in FIG. 4 to the output terminal 53 via the detection circuit 44 and the processing circuit 52.

Therefore, when the input signal becomes smaller than point B in FIG. 1, the control signal applied to the control terminal 51 also becomes smaller, and the control signals applied to the first and second control terminals 9 and 10 in FIG. The 38KHz switching signal of the demodulated first and second stereo difference signals (L-R) and (R-L) also becomes small.
The value of is also small.

Therefore, when added to the stereo sum signal (L+R) from the first and second sum signal circuits 1 and LP, the first output terminal 33
The right stereo signal remains at the second output terminal 34, and the left stereo signal remains at the second output terminal 34 as crosstalk, deteriorating the degree of separation.

As the input signal further decreases, the crosstalk component further increases, and eventually the generation of the stereo difference signal stops, and the stereo sum signal (L+R) is output to the first and second output terminals 33 and 34. They occur equally, resulting in a monaural listening condition.

The output signals generated at the first and second output terminals 33 and 34 continuously shift from a stereo state to a monaural state, and accordingly, the SN ratio also continuously shifts from a stereo state to a monaural state, and the SN ratio changes continuously from a stereo state to a monaural state. Since the improvement can be made smoothly rather than suddenly, it is possible to prevent the listener from feeling uncomfortable or uncomfortable.

During this time, the state of the sum signal circuit does not change at all.

In the range (A-B) in FIG. 1, an improvement in the SN ratio is achieved by transitioning from a stereo state to a monaural state and maintaining the monaural state, as described above.

When the electric field strength of the received signal becomes even smaller and the deterioration of the S/N ratio becomes noticeable even in the monaural state, the first and second
The states of the sum signal circuits υ and υ' begin to change.

That is, when the input signal reaches point A in FIG. 23,
And the ninth transistor 25 of the fourth differential circuit 27 starts conducting.

Then, with the start of conduction of the ninth transistor 25,
The high-frequency cut main channel signal power applied to the base of the twelfth transistor 32 from the stereo composite signal input terminal 18 via the high-frequency cut circuit I begins to be led out to the collector of the ninth transistor 25, and the first sum signal circuit I
The high-frequency cut main channel signal is obtained in the output signal of , together with the main channel signal led out to the collector of the seventh transistor 22 of the third differential circuit C.

In response to a decrease in the level of the input signal, the third control signal t1
decreases more and more, and the fourth control signal t2 increases the profit, so
The proportion of the high-frequency cut main channel signal included in the output signal of the first sum signal circuit J increases more and more.

For example, when it comes to tl-t2, the ratio of the high frequency cut main channel signal to the main channel signal is 1:1.

When the input signal becomes extremely small, tl(t2), the seventh transistor 22 of the third differential circuit U becomes non-conductive, and the fourth
The ninth transistor 25 in the differential circuit becomes saturated.

Therefore, the output signal of the first sum signal circuit F is only the high-frequency cut main channel signal, and a sufficient improvement in the S/N ratio is achieved.

FIG. 6 is a characteristic diagram showing the relationship between the ratio of the third control signal t1 to the main channel signal and the high-frequency cut main channel signal, where the dashed line 2 represents the main channel signal and the solid line H represents the high-frequency cut main channel signal. shows.

The second sum signal circuit υ' operates in exactly the same way as the first sum signal circuit and provides the same output signal, so a description thereof will be omitted.

In a preferred embodiment, the reduction of the output signal for the stereo subchannel signal demodulation circuit begins when the input signal is on the order of about 30 dB at the antenna input;
dB, the high-frequency cut main channel signal begins to mix into the output signals of the first and second sum signal circuits υ and υ'.

As described above, the stereo demodulation circuit according to the present invention improves the SN ratio in two stages in the case of a weak electric field, so it has the advantage of being able to achieve a wide and reliable improvement in the SN ratio.

Further, the stereo demodulation circuit according to the present invention has the above-mentioned two attacks.
When improving the N ratio, the switching is done smoothly rather than abruptly, so the S/N ratio can be improved without causing any discomfort or discomfort to the listener. It is particularly effective and excellent for use in receivers where the electric field strength changes frequently, such as those used in vehicles.

[Brief explanation of drawings]

Fig. 1 is a characteristic diagram showing the relationship between input and output and the relationship between input and S/N, Fig. 2 is a circuit diagram showing an example of a conventional SN ratio improvement circuit, and Fig. 3 is a diagram showing an example of the present invention. Circuit diagram shown, 4th
The figure is a block diagram showing how the third and fourth control signals t1 and t2 in FIG. 3 are generated, and FIG. 5 is a circuit diagram showing how the first and second control signals in FIG. 3 are generated. , and FIG. 6 are characteristic diagrams for explaining the present invention. Explanation of main figure numbers, 1...--Difference signal demodulation circuit, U. IJ, 24, 24', seat, N'...differential circuit,
Ll...First sum signal circuit, υ'...Second sum signal circuit, I...High frequency cut circuit.

Claims (1)

[Claims] 1 Stereo demodulation having a first circuit that demodulates a sub-channel signal, a second circuit that transmits a main channel signal, and an addition circuit that adds the output signals of the first and second circuits to obtain left and right stereo signals. In the circuit, the second circuit includes a circuit for varying the ratio of the main channel signal and the high-frequency cut main channel signal obtained by cutting the high-frequency components of the main channel signal, which are included in the output signal, and When receiving a signal higher than the level, the output signal of the second circuit is approximately only the main channel signal, and the output signal of the first and second circuit is
The output signal levels of the circuits are made approximately equal to achieve a normal stereo reception state, and when a signal is received that is below the first predetermined level and above the second predetermined level, the output signal of the first circuit is continuously reduced as the signal level decreases. As a result, the degree of separation is deteriorated, resulting in a monaural reception state or a state close to monaural reception, and below the second predetermined level, as the signal level decreases, the high frequency cut main channel included in the output signal of the second circuit is A stereo demodulation circuit characterized in that the SN ratio of a received signal is improved by increasing the signal ratio.