JPS584506B2 - clock control system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an apparatus for receiving data transmitted over a transmission medium, and more particularly to an automatically adaptive equalizer for correcting distortions occurring during transmission. The present invention relates to a synchronization device in a data receiving device using.

Note that the term "synchronization" refers to the significant points of the data signal,
This means adjusting the clock to determine as accurately as possible the point in time when the information contained in the signal can best be detected.

The problem of synchronization has been considered for some time, and the most widely used technique today is to use a clock that produces a clock signal that has the same frequency as that of the clock signal used to determine the data transmission rate at the transmitter. A signal generator is provided at the receiving end, and the signals sent before and during the transmission of data ensure the correct adjustment of the frequency and phase of the output of the clock signal generator.

This adjustment is performed by multiple independent iterations.

First, before the transmission of the first data, the initialization of the phase of the receive clock is performed, then before the transmission of each data, the resynchronization of the phase of the clock is performed, and finally, the phase of the clock is resynchronized before the transmission of each data. During transmission, successive modifications of the clock are made based on information extracted from the received signal.

This last modification operation is the most subtle.

The present invention relates to this corrective operation.

Traditionally, this problem has been solved when the signal is transmitted at a relatively low rate, or when the distortion during transmission is so low that it is not necessary to use an adaptive equalizer.

Recently, there has been a trend towards higher and higher speed transmission, and in this case an equalizer is required.

These equalizers have the characteristic that the transfer function can be continuously changed depending on the error signal occurring at their output.

However, at the high speeds currently applied,
The resulting distortion is such that the information needed to correct the clock cannot be extracted directly from the received data signal.

One previously proposed solution to this problem is to derive the clock control information not from the data signal, but from a signal superimposed on the data signal.

For example, French Patent Application No. 7120097 shows an application of this technique to phase modulation transmission, in which a weak amplitude modulation is applied to the phase modulated signal.

However, this technique also has the disadvantage of introducing additional noise sources and indirectly limiting the transmission rate.

This is because this technique cannot be applied to multi-phase and multi-level transmission.

Another similar technique is to send two pilot tones with spectra on either side of the data signal's frequency spectrum and extract clock information therefrom.

However, in this case as well, the effective bandwidth of the transmission medium is considerably limited.

It has also been proposed to extract information necessary for clock control from the equalized data signal.

In this case, it is possible to use the usual techniques, since the same situation is obtained in which the signal was only slightly distorted during transmission.

However, this does not apply when using an adaptive equalizer.

The configuration of the adaptive equalizer-clock circuit is a feedback loop circuit consisting of two subsystems, each of which is designed independently to reduce the errors introduced when detecting data from the equalized signal. Do the same thing.

In some cases, such feedback loops
When instability occurs, and even under steady state conditions, the time required to make sufficient corrections at both the equalizer level and the clock control circuit level, ie, the response time, is lengthened considerably.

On the other hand, such systems have significant drawbacks if it is desired to operate on sampled signals in digital techniques.

Adaptive equalizers (at least modern ones) require only one sample each modulation time to perform their correction function.

However, in order to obtain the information necessary for clock control, several samples are required for each modulation time defined to better define the equalized signal.

Therefore, the equalizer must operate on more samples per modulation time than it needs to perform its function.

This further complicates the operation of the calculation circuitry and equalizer.It is a primary objective of the present invention to clock the receiver by directly utilizing the data signals received from the transmission medium before the adaptive equalizer. The object of the present invention is to provide a block control system for controlling.

It is another object of the present invention to provide a receiver synchronous clock control system which is cascaded rather than feedback loop connected to the adaptive equalizer, thereby increasing system stability and reducing overall response time. The goal is to provide the following.

Yet another object of the present invention is to provide a receiver synchronous clock control system that does not require superimposing all or part of the control information on the data signal.

In the system according to the invention, according to the transmission mode, a standard signal representing the envelope of the signal elements used during transmission, i.e. the envelope of the basic baseband signal itself, is based on the received data signal and the detection information. It is formed.

The time position information of this standard signal with respect to the time reference produces a synchronization error indication, which is used to adjust the operation of the receive clock.

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 shows the general structure of a data receiver in accordance with the principles of the present invention.

This receiver has an equalizer of the type shown in French Patent Application No. 7326-04.

Also, with regard to the embodiments to be described, it is assumed that the transmission mode, ie, the modulation method, being used is a multi-level differential phase modulation method.

According to this modulation scheme, data information is indicated by the amplitude ρ and phase φ of the transmitted signal at a given time.

The transmitted signal is received by the receiver as an analog signal r(f) and, after passing through an automatic gain control circuit 1, is sampled by a sampling device 2 at a time ti determined by a clock 3.

If the data transmission rate is 1/T (baud), then the sampling frequency determined by the clock 3 is M/T, so that the plurality of samples ri collected at each time T correctly transmits the signal r (f). is sufficient to specify.

Note that M is a fixed integer of 2 or more, and is arbitrarily selected depending on the embodiment.

The samples ri are then provided to a phase shifter 4.

The phase shifter 4 produces two signal samples xi and xi having a phase difference of 90 degrees from each other.

An example of such a phase shifter is disclosed in the aforementioned French patent application no.
Samples xi and xi shown at 3 2 6 4 04 are sent to equalizer 5.

The samples yk and yk of the Cartesian coordinate components of the equalized signal are sent to a detection and decoding device 6.

More specifically, the detection and decoding device operates according to a data clock signal having a frequency of 1/M of the sampling frequency M/T of the sampling device 2.

That is, the clock 3 provides the sampling device 2 with a sampling pulse having a frequency M times the frequency of the internally generated data clock signal.

Equalizer 5 also operates according to the data clock signal.

Therefore, the suspensions xi and xi generated at each time T/M are not all provided to the equalizer 5, but are provided to the equalizer 5 at a rate of one per time T.

Note that the time point determined by the data clock signal will be referred to as data clock time point Ti.

Therefore, the sampling instants ti for the sampling device 2 are times when the time between successive data clock instants Ti is divided into M equal parts.

The detection and decoding device 6 generates data and a signal expressed by the following equation 1 by converting Cartesian coordinates yk and yk into polar coordinates ρk and φk.

These two signals are sent to the clock control circuit 7.

Circuit 7 also receives samples xi and XI and provides a control signal CS to clock 3 for correcting its operation.

FIG. 2 shows the configuration of the clock control circuit 7 in FIG. 1 in detail.

Note that the equalizer 5 in FIG. 1 is also shown incidentally as equalizers 8 and 9 in FIG.

M samples x obtained from the phase shifter 4 per each modulation time T
i is subjected to a second sampling process with a rate of 1/T.

The samples xk thus obtained at a rate of one per modulation time are sent to the transversal equalizer 8.

A transversal equalizer 8 produces samples yk of the components of the equalized signal.

Similarly, the sample xi is also subjected to the second sampling process at a rate of 1/T, and the sample yk thus obtained is processed in the transversal equalizer 9, whereby the sample yk of the other component of the equalized signal is can get.

For ease of explanation, it is assumed that the length of the delay lines of equalizers 8 and 9 is 2NT.

Note that N is a positive integer.The operation of equalizers 8 and 9 as described above is the operation of equalizer 5 in FIG.

The sample xi is composed of delay elements 10 and 2 which provide a delay of θ.
A delay section consisting of a delay element 11 providing a delay τ is also provided.

Taps P1 and P2 are provided on both sides of the delay element 11.

The value of θ is selected such that the two taps P1 and P2 are symmetrical in time with respect to the reference tap (main tap) of the equalizer 8.

If the reference tap of equalizer 8 is a center tap with a time difference of NT with respect to input point A, then θ is NT-τ
is selected to be equal to

Therefore, when viewed from input point A, tap P has a time lag of NT-τ, and tap P2 has a time lag of NT+τ.

The value of τ is chosen to be significantly smaller than T.

The reason will be explained later. As an example, τ=T
It is convenient to set it as /M.

Similarly, samples xi are applied to a delay section consisting of delay element 12 providing a delay of θ and delay element 13 providing a delay of 2τ.

The values of θ and t are the same as defined for delay elements 10 and 11.

Also, taps P3 and P4 are input points B to N, respectively.
T−τ and NT+? I'm just delayed in terms of time.

Tap P1 is connected to two multipliers 14 and 15.

Multiplier 14 receives the signal from detection and decoding device 6 (FIG. 1), and multiplier 15 receives signal 1.

Similarly, tap P3 is connected to two multipliers 16 and 17.

Multiplier 16 receives the signal ゜''φ゜, and multiplier 17 receives the signal ゜''φ゜.

The outputs of multipliers 14 and 17 are connected separately to the input and output of adder 18.

On the output side of the adder 18, an integrator (in the case of digital technology, an averaging circuit) 19 and a squaring circuit 20 are connected in series.

On the other hand, the output of the multiplier 15 is connected to the 10 input of the adder 21, and the output of the multiplier 16 is connected to the other + input of the adder 21.

An integrator (or averaging circuit) is installed on the output side of the adder 21.
22 and a square circuit 23 are connected in series.

The outputs of squaring circuits 20 and 23 are added together in adder 24.

The output signal of adder 24 is the first signal on the curve representing the standard signal.
shows the amplitude d1 at the point (see Fig. 3).

With a similar circuit arrangement, it is possible to obtain the amplitude d2 of the second point of this curve from the signals at taps P2 and P4.

The circuitry is the same as disclosed for the signals at tabs P and P3, and has therefore been omitted to simplify the drawing.

The information element d, is given to the − input of the adder 25,
Since the information element d2 is connected to the +input of the adder 25, the difference between the two is obtained as a result.

The difference is appropriately corrected in the calibration circuit 26 and then used to change the contents of the counter 27.

Counter 27 is part of a clock circuit which also includes a high frequency oscillator 28 which provides a signal to the counter.

Counter 27 acts as a frequency divider and its output pulse defines the sampling instant ti.

Note that the data for the detection and decoding device 6 (Fig. 1)
The clock signal is applied to the counter 2 by a frequency multiplier, for example.
7 by multiplying the frequency by M times, the control of the counter modifies not only the sampling pulse but also the timing of the data clock signal.

Also, instead of dividing the output of the high frequency oscillator 28 by the counter 2T to first generate a sampling pulse and multiplying it by M to obtain the data clock signal, the output of the high frequency oscillator 28 is first divided by the counter 27 to obtain the data clock signal. It is also possible to create a data clock signal and further divide it by a factor of M to create a sampling pulse.

The operating principle of the circuit described so far will now be described.

To that end, some mathematical expressions regarding the multi-level differential phase modulation scheme in this example are recalled.

First, it is well known that a signal on a transmission line is expressed by the following equation.

r(t))-E pk (S (t k T )c
osφk+S(t. −kT) Sinφk) (
1) Various symbols in this formula have the following meanings.

S(t): Signal (element) obtained by modulating carrier wave (angular frequency wc) with baseband signal g(t)
.

That is, S(t)-g(tOSwct 0g/t)
: A signal with the phase of S(t) shifted by 90 degrees.

That is, S(t) - g(t) sinwc t ρk and φ
k: amplitude and phase values used to encode data at time kT.

These values are composed of multiple discrete values (ρJ
) and (φj).

Equation (1) shows a signal resulting from the superposition of a plurality of signals corresponding to information elements that are successively transmitted.

This represents a phenomenon called intersymbol interference.

Assuming that the center tap of an equalizer (e.g. equalizers 8 and 9 in FIG. 2) is the time reference, the signal r(t
) includes not only the signal based on the transmission of the information element to which the time T is assigned, but also the interference based on the information elements sent before and after this information element.

Note that in equation (1), k varies from -■ to +(3), or from 1n to +n when the transmission includes 2n+1 information elements.

The transporter 4 generates signals X(1) and x(t) having a phase difference of 90 degrees from each other based on the signal r(t).

To make the explanation easier to understand, x(t) is r(t)
, and therefore x(1) is assumed to be r(t) out of phase by 90 degrees.

For the same purpose, we will not take into account the sampling operation performed on the signal r(1).

That is, this does not affect the mathematical theory at all.

Therefore, x(t) and x(t) are expressed as follows.

x(t)-ζρk (S C t-kT) cosφ
k+S(t-1(T)sinφk,l
(2) x(t) 1zoρk(t-kT)c
osφk-S(t-kT) sinφk Referring to FIG. 2, multiplier 1 4 . 17, adder 18, and integrator 19 perform calculations expressed by the following equation.

This corresponds to the taps P1 and P over p times the time T.
Correlation of signals in 3 (corr-ela
tion ).

That is, for each time T, (x(t+τ)) and (x(t±τ)
]? , correlation with data detected during the same time period is performed.

The difficulty to note here is that the time reference is fixed to the center tap of the equalizer, so the values of φ0 and ρ0 are
It is variable according to the time T under consideration.

When considering this correlation operation, (2
) It can be seen that in the sum of the elements forming the signal x (t), the elements that are correlated are those corresponding to k=o, ie the elements to which the time T under consideration is assigned.

All other elements corresponding to values of k other than O, ie, the preceding and succeeding intersymbol interference terms, do not show any significant correlation.

Therefore, these are equations (3)? does not contribute to the determined average value.

The same thing applies to the correlation between X(1) and Tosa.

That is, in the sum of elements forming x(t), the only element that is correlated is the one corresponding to k=0; all other elements are uncorrelated;
Therefore, it does not contribute to the average value defined by equation (3).

Thus, equation (3) can be replaced as follows.

A term of X(t) corresponding to k=o at each time T A term of ↑(i) corresponding to k=o at each time T The result of this calculation is simply expressed as S(t+τ).

The matters described here include the multipliers 15 and 16, the adder 21,
This also applies to a correlation configuration consisting of an integrator 22 and an integrator 22 and performing calculations expressed by the following equation.

The result of this calculation is denoted S(t+τ).

This value is available at the output of integrator 22.

S(t+τ) and Miya(t+τ) are each square circuit 2
After being squared at 0 and 23, it is applied to an adder 24.

Adder 24 produces a signal expressed by the following equation.

d1=(S(t+τ))2+(S(t+τ))]2 The envelope of the transmitted signal element is usually expressed by the following equation.

R(t) = (S(t)) 2+ C (t)
) 2 Therefore, the output d1 of the adder 24 is the time + τ of the square of the envelope of the transmitted signal element.
is known to represent the amplitude at .

In fact, the envelope amplitude itself at time +τ is
This is obtained by providing a square root calculation circuit after the adder 24.

However, for the present invention it is immaterial whether the envelope itself or its square is obtained.

For simplicity of explanation, the signal representing the squared envelope is referred to as the standard signal.

A circuit (not shown) for processing the signals at taps P2 and P4 operates in a similar manner to obtain a value representing the amplitude of the standard signal at time -.tau., as shown by the following equation.

a2=(S(t-τ))2+(S(t-τ))]2 Figure 3 schematically shows the state of the standard signal near the time reference set at the center tap of the equalizer as described above. This is shown below.

The values d1 and d2 correspond to the amplitudes at times 10 and -τ, respectively.

It has been observed that when the received signal is subjected to proper sampling (the receive clock is properly adjusted), the signal at the center tap of the equalizer corresponds to the maximum amplitude point of the envelope and its square. , and confirmed by simulation.

However, if the sampling process is not done properly, the envelope white will be offset with respect to the center tap of the equalizer.

That is, if the sampling timing is too early, the envelope will shift to the left as shown, and if the sampling timing is too late, the envelope will shift to the right.

The difference d2d is proportional to the time difference Δt between the maximum point of the Jt standard signal and the center tap of the equalizer.

The difference d2-d, is determined in an adder 25 and, after being suitably corrected in a subsequent circuit 26, is used to correct the instant ti of the sampling pulse.

Corrective actions may be performed in a variety of conventional ways.

A sampling clock is used here, consisting of a high-frequency oscillator 28 and a counter 27 dependent thereon which acts as a frequency divider.

Sampling time, i.e. clock pulse generation time ti
is corrected by forcibly changing the contents of counter 27.

A forced change of the contents of the counter, i.e. a skip, is λ(d2
-d,).

λ is the calibration factor, which depends on the characteristics of the counter selected and the speed desired at making the correction.

The value of λ is such that the system does not oscillate (i.e., λ is not too large) and the time difference can be eliminated quickly enough (i.e., λ is not too small).
must be selected.

Choosing the optimal value of λ for a given application is easy for a person skilled in the art.

By this technique, the clock that defines the sampling instant ti is continuously maintained during transmission in such a way as to reduce the difference in amplitude of two points of the contrasting standard belief curve with respect to the time reference given by the center tap of the equalizer. adjusted.

Although a preferred embodiment of the present invention applied to a phase modulation method has been disclosed above, it goes without saying that the present invention is not limited to this specific embodiment.

As a modification to the preferred embodiment, it is also possible to limit the time relationships of the standard signals by more than two points.

Furthermore, by providing a tap in the center of the delay element providing a delay of 2τ and assigning circuitry to it as described for taps P1 and P3, the amplitude of the standard signal at the reference time corresponding to the center tap of the equalizer is It is also possible to take into account.

Similarly, the taps can be increased by introducing additional τ time delay elements on either side of the reference time.

In any case, when more than two points of the standard signal are defined, the information for adjusting the clock is the distance between the center of gravity and the reference position for these points.

Conversely, it is also possible to take only a single point into account.

In this case, that point is the amplitude of the standard signal at the reference instant corresponding to the center tap of the equalizer.

Adjustments are made based on comparing this amplitude to a reference threshold.

However, the preferred embodiment takes into account two points as described above.

That is, this embodiment provides the best trade-off between circuit complexity and achievable accuracy.

Note that in this embodiment, the main tap of the equalizer is located at the center of the equalizer, but this is not limiting.

In fact, in some transmission lines, subsequent intersymbol interference may be more important than preceding intersymbol interference, or vice versa, so that the main
The taps may be placed near the equalizer input or further away from the input.

It is clear that this does not depart from the principles of the invention.

Furthermore, the information used as the adjustment reference is the difference d2−d,
However, various methods for performing clock adjustment are known.

Only one preferred example has been disclosed.

For example, it is also possible to use an alternative operation that only takes into account the sign of the adjustment information.

In this case, two oscillators or one oscillator with two frequency dividers are used, and the switching from one frequency to the other takes place according to the sign of the adjustment information.

Regarding the correlation operation, the above-mentioned (3)
) and (4) provide the highest correlation speed.

However, at the expense of correlation speed, x(
t+τ) and (t+r) as ゜゜゛φ゜ (or ゜1゛φ
It is also possible to simplify the circuit by correlating only with ゜).

In that case, the following equation is used instead of the above-mentioned equations (3) and (4).

That is, by replacing x(t+τ) and x(t+τ) with the complete expressions specified by equation (2) above, and considering the term corresponding to k\0 as having a zero average value, the following equation is obtained. can get.

The average value of the terms sinφ0 and COSφ0 at pT time is 0 (because φ0 is a set of values uniformly distributed from 0 to 2π).

On the other hand, the average value of the COS2φ0 term is 1.

Therefore, the formula (3y) corresponds to 1S(t+τ), and the formula (4) corresponds to 2S(t+τ).

Since, except for the factor 100, the principles remain unchanged, the correlation results are the same as obtained in the disclosed system, and the explanations regarding that system apply exactly.

Another method is to correlate X(1) with one and one.

In this case, x(t) is not used for clock adjustment.

From the foregoing, it is clear that the particular embodiments for illustrating the invention are not intended to be limiting.

The present invention is applicable even when the receiver does not have an equalizer.

The time reference in that case is the time of data detection.

In this case, the proposed technique does not appear to be better than other conventional techniques, but the present invention can still be applied to it.

Furthermore, if an equalizer is used, it can be of any type.

For example, with respect to phase modulation schemes, equalizers such as those shown in French patent application no. When using an equalizer using elements, S(t±τ) and S(t±τ) can be obtained by correlating r(t±τ) with one and -.
is obtained.

Another method is to form the signal ↑(1) from the signal r (t) and provide it to the disclosed system.

In this case, if the fundamental delay used in the equalizer delay line is sufficiently small compared to T, the signals r(t-τ) and r(t+τ) can be obtained directly from the delay line.

Similarly, when applying the invention to amplitude modulation, the data information ε0 detected during a given modulation time is the signal r(t−
τ) and r(t+τ) and are correlated after demodulation to the base bird.

The standard signal that is formed is then no longer a transmitted signal element (or its squared version) but a baseband signal.

However, the principles of the invention apply equally.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a receiver according to the invention, FIG. 2 is a diagram showing a circuit included in a specific embodiment of the invention, and FIG. 3 is a diagram showing a standard signal as a result of correlation in the embodiment. It is a diagram. In FIG. 1, 1... automatic gain control circuit, 2
... Sampling device, 3 ... Clock, 4 ... Phase shifter, 5 ... Equalizer, 6
. . . Detection decoding circuit, 7 . . . Clock control circuit. In Fig. 2, 8, 9... Equalizer, 10, 1
'1, 12.13... Delay element, 14, 15
, 16, 17... Multiplier, 18, 21...
...Adder, 19.22...Integrator, 20,2
3... Square circuit, 24.25... Adder, 26... Calibration circuit, 27.
... Counter, 28 ... Oscillator.

Claims (1)

[Claims] 1. Amplitude ρk and phase φ of carrier wave having angular frequency wc
At least one of k is a data signal determined according to data at each time T, and the baseband signal is g(t)
and g(t) cos wct=S(t)
, g(t)sin wct Jt), then r
(t)=Epk(.S(t-kT)cos
A data signal expressed as φk + S (t − kT ) sin φk] is received via a transmission medium that has the characteristic of distorting the signal due to its limited bandwidth, and
For a receiving device which determines the amplitude and phase values according to samples of the data signal at every data clock time Ti determined by a data clock signal having a frequency T, and reproduces the original data based on the values. , a system for controlling said data clock signal, the system comprising: an M/T-1/
means for successively producing sample signals by sampling the data signal in accordance with a sampling signal having a frequency of τ (M is a positive integer of 2 or more); means for generating a series of sample signals and a second series of sample signals in parallel; and calculating an amplitude value ρ0 and a phase value φ0 of the data signal at each time point Ti from the first series of sample signals and the second series of sample signals. means for generating a first signal representing sin φ0/ρ0 and a second signal representing COS φ0/ρ0 using the first signal; A first delay means receives the sample signal of the second series and delays it by the predetermined time, and a second delay means produces the signal generated at the tap and delayed by the predetermined time by the predetermined time. 3 taps and 2 more hours than the above predetermined time
a second delay means that generates a signal delayed by τ at a fourth tap; the first signal and the second signal; a first series of sample signals generated from the first tap of the first delay means; and the second delay means. means for generating in parallel a third signal corresponding to S(t+τ) and a fourth signal corresponding to S(t+τ) by correlation with a second series of sample signals arising from a third tap of the first signal; and S-(,t
- τ) and a means for generating a sixth signal corresponding to S(t - τ); l) means for generating a signal d1 representing [S(t-τ)]2 using the fifth and sixth signals;
+[S(t-τ)]2; means for producing a difference signal representing the difference between said signal d1 and said signal d2; and means for producing a difference signal representing the difference between said signal d1 and said signal d2; A clock control system characterized by a clock having means for modifying the timing of occurrence.