JPS5844841A - Synchronizing device for sampling frequency - Google Patents

Abstract

PURPOSE:To synchronize a sampling frequency independently of a transmitted clock and a data frame, by transmitting relative information representing the relation of a transmission sampling clock to a reference frequency through multiplex with other information in a PCM transmission system. CONSTITUTION:An analog signal applied to an input terminal 1 is converted at an A/D converter 2 and an encoder 4, multiplexed to relative information DELTAS at a multiplexer 6 and transmitted to a transmission line 10 via a buffer memory 7. A reference signal phi1 from the 1st reference oscillator 8 is compared with a sampling clock phi5 from a VCO3 and the relative information DELTAS is picked up. At a reception side, a transmitted signal is converted into an analog signal via a buffer memory 17, a demultiplexer 16, a decoder 14 and a D/A converter 12 and outputted to an output terminal 11. A reference signal phi'1 from the 2nd reference oscillator 18 is compared with a sampling clock phiR from the VCO13 and relative information DELTAR is picked up. The difference DELTA=DELTAR-DELTAS is obtained at a subtractor 19 from the information DELTAR and the DELTAS separated from the demultiplexer 16 and becomes a control voltage of the VCO13 via a limiter 25, an integrator 20 and a D/A converter.

Description

Detailed Description of the Invention The present invention provides a digital transmission system in which an analog signal is sampled, encoded, and transmitted through a digital transmission path, and when the sampling clock frequency and the clock frequency of the transmission path are independent, the transmission/reception sampling clock The present invention relates to a synchronization device that synchronizes frequencies.

When converting an analog signal into a digital signal and transmitting it through a digital transmission path, the sampling clock frequency of the analog signal and the cross-crossing frequency of the digital transmission path may be determined independently. For example, in digital transmission of television signals, it is often done to set the sampling clock frequency of the television signal to be synchronized with the unique synchronization signal of the television signal. This also applies when the sampling frequency is selected to be three or four times the subcarrier frequency. On the other hand, the transmission line clock frequency of the digital transmission line is often determined in advance by the transmission system, and is generally unrelated to the synchronization frequency of the television signal.

In this way, if the sampling clock frequency of the analog signal to be transmitted and the transmission line clock frequency are independent, the asynchronous clock frequency can be adjusted by sending the digitally converted signal to the transmission line via a buffer memory, etc. It is normal to achieve consistency between the two. A buffer memory is prepared for the same purpose on the receiving side, but the receiving sampling frequency must match the transmitting sampling frequency. If the transmission sampling frequency and the reception sampling frequency do not match, not only will it be impossible to faithfully reproduce the analog signal, but also the reception buffer memory will overflow and cause a cyan undertone, making it impossible to reproduce the reception signal.

In order to match the transmission sampling clock frequency with the asynchronous transmission line clock and to match the reception sampling clock frequency with that on the transmitting side, stuffing has conventionally been performed. Stuff Ink compares the phases of the data frame on the transmission path and the pseudo data frame created by dividing the sampling clock, and changes the length of the data frame so that they match on average. Information is added to a part of the data frame. However, conventional stuffing requires a pseudo data frame close to the data frame of the transmission line, and therefore has the drawback that the transmission line clock frequency cannot be changed arbitrarily.

Furthermore, in digital transmission, relay transmission is also performed through a plurality of transmission paths having different transmission speeds.

For example, a signal transmitted at 45 Mb/s over a terrestrial micro line may be multiplexed with other information and transmitted over a 60 Mb/s satellite line, and then further relayed to a city via a 90 Mb/s optical transmission line. You can do it.

When such relaying is performed, the transmission line clock frequency and data frame structure do not match between transmission and reception, so it is no longer possible to synchronize the sampling clock frequencies of transmission and reception using the transmission line clock frequency as a medium.

SUMMARY OF THE INVENTION An object of the present invention is to provide a sampling frequency synchronization device that eliminates the above-mentioned drawbacks and can match the sampling frequencies of transmission and reception for any digital transmission path.

That is, the present invention provides a transmission sampling clock generation method on the transmitting side at the same 1υ1& position in which the sampling clock frequency of the analog signal to be transmitted is synchronized with the sampling clock frequency of the transmission and reception of a digital transmission system in which the clock frequency of the transmission line is independent. a first comparison means that compares the transmission sampling clock frequency 18 and the reference oscillation frequency f1 and obtains the relative relationship between f3 and 11 as relative information Δ8; and a means for multiplexing the information with other information and sending it out to the transmission line via a buffer = 5-1 memory, and on the receiving side, means for detecting the relative information △8, a clock generator for receiving sampling, and a highly stable a reference oscillator, the received sampling clock frequency fe, and the reference oscillation frequency f1;
a second comparison means that compares 9 and fl and obtains the relative relationship between 9 and fl as relative information ΔR in the same manner as on the sending side, and relative information Δ8.
and means for controlling the reception sampling clock frequency 9 so that the transmission and reception sampling frequencies coincide with each other.

According to the present invention, since the information for synchronizing the sampling frequency of transmission and reception is transmitted regardless of the clock frequency of the transmission path and the data frame, it is possible to synchronize the sampling frequency with respect to an arbitrary transmission path clock frequency. It can be applied to a wide range of digital transmission systems.

Next, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

6- In the figure, an analog signal to be transmitted is applied to an input terminal 1 and converted into a digital signal by an analog/digital (A/D) converter 2. In the present invention, the analog signal to be transmitted can be any arbitrary signal, such as a television signal, an audio signal, or a facsimile signal, but the following description will be made using a television signal as an example.

The sampling clock generator 3 uses an input television controlled oscillator (VCO).

The A/D converted television signal is further converted into an appropriate code by being transmitted by an encoder 4, and multiplexed with relative information ΔS by a multiplexer 6.

The multiplexed signal is once written into the buffer memory 7, speed matched, and sent out to the transmission line 10. In the case of television signals, an intra-frame encoder, an inter-frame encoder, a ΔM encoder, etc. are used as the encoder 4, but P obtained by A/D conversion without using an encoder is
A CM (pulse code modulation) signal may be transmitted as is.

When using an advanced band compression device as an encoder for the purpose of removing redundancy in television signals, it is necessary to precisely synchronize the sampling clock frequency of A/D conversion with the synchronization frequency or subcarrier of the television signal. There is. Since the periodic frequency of a television signal differs slightly depending on the television station or television camera, the sampling clock frequency synchronously oscillated by the vCO will change depending on the input tenvision signal.

Reference numeral 8 denotes a first reference oscillator, which is an oscillator with sufficiently high oscillation frequency accuracy and stability, such as a crystal oscillator whose temperature is controlled in a constant temperature bath.

The oscillation frequency fl of the reference oscillator 8 may be arbitrary or may be chosen approximately equal to the sampling clock frequency.

In the case of television signals, fl is preferably about 5 to 30 MHz.

The reference signal φl generated by the first reference oscillator 8 is transmitted to the comparator 5.
FIG. 2 is a block diagram showing an example of a specific configuration of the comparator 5. FIG. 2 is a block diagram showing an example of a specific configuration of the comparator 5.

The frequency of the transmission sampling clock φ8 is divided by l/N by the frequency divider 2j to generate a frequency-divided pulse φN with a period of N/fs, and the frequency-divided pulse φN is sent to the clear terminal of the counter 22 and the clock terminal of the register 23. give to A reference clock φl is applied to a clock terminal of the counter 22, and the number of reference clocks included in the period N/fs is counted. By inputting this count value into the register 23 using the frequency division pulse φN, relative information ΔS indicating the relative relationship with the sampling clock frequency fti is obtained as an output. That is, the relative information ΔS in this case is given by. Note that the frequency division number N is an integer, but if it is selected to match the frame frequency or line frequency of the fs/Nt input television signal, △8 is generated every time the television signal is synchronized, so the multiplexer 6 divides the television signal. It becomes easy to multiplex Δ8 to .DELTA.8.

Next, the operation on the receiving side will be explained with reference to FIG.

The signal sent through the transmission path 10 is separated into a television signal and relative information ΔS by a demultiplexer 16 via a buffer memory 17.

The television signal is sent to a decoder 1 which operates inversely to the encoder 4.
4, the signal is converted into the original PCM signal, and the digital/analog (D/A) converter 2 converts the signal into an analog signal, which is output through the output terminal 11.

The sampling clock generator 13 for generating the reception sampling clock φ wing is composed of a voltage controlled oscillator (VCO) whose oscillation frequency can be controlled. Second reference oscillator 18
can use the same configuration as the first reference oscillator 8.

The oscillation frequency of the second reference oscillator 18 must be adjusted to be equal to the oscillation frequency f1 of the first reference oscillator 8. The reference signal φ'1 generated by the second reference oscillator 18 is compared in the comparator 15 with the sampling clock φR generated by the VCO'13.

10- The configuration of the comparator 15 is exactly the same as the configuration on the transmitting side shown in FIG. Therefore, the relative information ΔilU is taken out as the output of the comparator 15.

The signal 8 separated by the demultiplexer 16 and ΔR obtained by the comparator 15 are subtracted by a subtracter 19, and the difference Δ is taken out as an output. The difference is amplitude limited by a limiter 25, integrated by a digital integrator 20, and then D/A converted 1f3 o
is converted to x rivcOt3omIJH3nV. The difference Δ is zero, and the control voltage ■ is V=Vo+kf(f6-7,)dt (4) where k is a constant.

The limiter 25 has the function of limiting to ttill 6M when the absolute value of Δ is larger than Mt to a certain threshold value.

By providing the limiter 25, it is possible to prevent a large error from occurring in △ due to a sign error υ in the transmission path, limit the magnitude of instantaneous fluctuations in the control voltage V, and stabilize the reception sampling clock frequency. You can increase the degree.

The VCO control #I voltage to the receiving sample clock frequency is Vo
If 9 is about to become louder than f8, a control rs+ voltage such as V<Vo is added to prevent this, and conversely, when fR is about to become smaller than fs, V
>Vo is added to prevent this, so it is always controlled to be 8-f8.

If the accuracy of the transmission sampling clock frequency is 8 degrees, the comparator shown in Figure 2 can be simplified, so
This will be explained as a second embodiment.

In Fig. 2, the frequency (-f, /N) of φ is, for example, the television frame frequency, that is, 30Hz.
When the transmission path clock frequency ft is set to 30 MHz, Δ8 becomes, and the required number of bits for the counter 22 and the register 23 in FIG. 2 is 20 bits9, resulting in a large circuit scale.

However, if the transmission sampling frequency f8 is limited to the range H of fll(1-δ')<fs <fo (1+δ), then Δ6 is limited to the range H.

In this case, the variable range of the reception sampling clock frequency is also fo(1-J)<7. <fo(1+a) (7)
Therefore, δ can be limited to a range of Δ8.

The range of information used for VCO control on the receiving side is (6)
, From equation (8), it becomes 13-. For example, when the precision δ of the transmission sampling frequency is 10-5, calculating the numerical value of equation (9) yields -20〈Δ
<+20 (10). Therefore, the number of bits of the counter and register used in the comparator was set to 6.
Even if the 6 bits of the remainder value of Δ8 are transmitted as Δ'8 after being reduced to 6 bits, and the receiving side also calculates the 6 bits of the remainder of Δ8 as Δ'' and calculates Δ'8 - Δ'8, correct control will not occur. However, the calculation of Δ', -Δ'8 is 1Δ',
-Δ', 1 (in case of 32, Δ=Δ'8-Δ'1.Δ',
When −Δ′8≧32, Δ=Δ′8−Δ′, −64, Δ
When '8-Δ'8≦-32, △=Δ'8-Δ', +6
Calculate as 4.

Generally, when 1Δl<n, 2m)2n (11) is satisfied. The m-bit remainder value may be calculated for Δ8 and Δ8. That is, in this embodiment, the number of bits of the counter 22 and register 230 in the comparator of FIG.
The reception sampling frequency is controlled by the relative information Δ'8 and Δ' of 6 bits and 14 bits. It has the feature of reducing the number of bits. Note that the subtracter indicated by reference numeral 19 in FIG. 1 may also be performed for the rn bit.

FIG. 3 shows an embodiment in which the present invention is applied to a television signal transmission system for transmitting and receiving. In this case, transmission is performed from station A to station B and from station B to station A, but it is sufficient to prepare one reference oscillator 8 for station A and one for station B, and the transmitter of each station Can be shared by receiving devices. Figure 3 shows its configuration, with reference numbers 100 and 200 representing the first
The transmitter and receiver are shown surrounded by broken lines in the figure. Reference numerals 100' and 200' indicate the transmitting and receiving parts of the corresponding B stations. In the figure, a television signal applied to terminal l enters a transmitter 100, uses a reference signal from a reference oscillator 8 to multiplex relative information Δ8 onto the television signal,
A signal is transmitted to the B station via the transmission path 10. Similarly, in the B station, the television signal applied to the terminal l' is multiplexed with relative information by the reference signal from the reference oscillator 8' in the transmitter 100', and is transmitted to the A station through the transmission line 10'.

The signal transmitted through the transmission path 10 is decoded by a receiving device 200' at station B and outputted to a terminal 11' as an analog television signal. Synchronization of the sampling frequency in receiver 200' is performed using a reference signal from reference oscillator 8'.

The present invention is characterized in that information for synchronizing the sampling clock frequency is transmitted regardless of the clock frequency of the transmission path or the data frame. Therefore, the present invention can be easily applied to the case where multiple channels of television signals are multiplexed by time-sharing one transmission path. That is, even if the sampling clock frequency differs for each channel, the relative information Δ8 is sent to each channel together with the data, so the sampling frequencies of transmission and reception can be synchronized on the receiving side. In this case as well, it is sufficient to install one reference oscillator in each station, and it is possible to share the reference oscillator with each channel.

[Brief explanation of the drawing]

A block diagram showing an example of a specific configuration of a comparator indicated by numeral 5, No. 31, 1 is a block diagram of a device configuration when the present invention is applied to a transmitting/receiving dual transmission system. In the figure, 2...A/l converter, 3...sampling clock generator, 4...encoder, 5...
・Comparator, 6...Multiplexer 17...
...Transmission buffer memory, 8°18...
Reference oscillator, 12...D/A converter, 13...
... Sampling clock generator, 14 ... Decoder, 15 ... Comparator, 16 ... Demarterxer, 17 ... Receive buffer Memory, 25...Limiter, 19...Subtractor, 20...Digital integrator, 3011 Figure 02 Figure 2

Claims (1)

[Claims] In a synchronization device that synchronizes the sampling clock frequency of transmitting and receiving in a digital transmission system where the sampling clock frequency of the analog signal to be transmitted and the clock frequency of the transmission line are independent,
On the transmitting side, a first clock generator that generates a transmitting side sampling clock, a first reference oscillator that generates a transmitting side reference frequency, and comparing the transmitting side sampling clock frequency and the transmitting side reference frequency. a first comparing means for obtaining a relative relationship between the transmitting side sampling clock frequency and the transmitting side reference frequency as first relative information; and a transmission path for multiplexing the first relative information with other information. a second clock generator for generating a clock for sampling on the receiving side; a second clock generator for generating a clock for sampling on the receiving side; A second reference oscillator that generates a reference frequency compares the receiving-side sampling clock frequency and the receiving-side reference frequency, and determines the relative relationship between the receiving-side sampling clock frequency and the receiving-side reference frequency using a second reference oscillator. a second comparison means obtained as relative information; and a second comparison means obtained as relative information;
and means for controlling the sampling clock frequency on the receiving side so that the second relative information matches each other, and the sampling frequency synchronization is characterized in that the sampling frequency is automatically controlled to match the sampling frequency of transmission and reception. Device.